CN116501117A - Low-dropout linear voltage regulator - Google Patents
Low-dropout linear voltage regulator Download PDFInfo
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- CN116501117A CN116501117A CN202310186692.2A CN202310186692A CN116501117A CN 116501117 A CN116501117 A CN 116501117A CN 202310186692 A CN202310186692 A CN 202310186692A CN 116501117 A CN116501117 A CN 116501117A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
Embodiments of the present disclosure provide a low dropout linear regulator, comprising: the first and second bias voltage generating circuits, the error amplifier, the output power transistor, the feedback circuit, and the first capacitor. The first bias voltage generating circuit generates a first bias voltage and supplies the first bias voltage to a first load circuit in the error amplifier. The second bias voltage generating circuit generates a second bias voltage and supplies the second bias voltage to a second load circuit in the error amplifier. The error amplifier generates an error voltage according to the reference voltage and a feedback voltage from the feedback circuit and provides the error voltage to the control electrode of the output power tube. The first pole of the output power tube is coupled with the input voltage end. The second pole of the output power tube is coupled with the output voltage end. The feedback circuit divides an output voltage of the low dropout linear regulator to generate a feedback voltage. The first end of the first capacitor is coupled to the output voltage end. The second terminal of the first capacitor is coupled to the second node.
Description
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to low dropout linear regulators.
Background
A low dropout linear regulator (low dropout regulator, LDO for short) is capable of generating a regulated output voltage to power the chip. In power management chips, LDO circuits are widely used to power internal circuits. Conventional LDO circuits have an internal compensation capacitor arranged to ensure the stability of the LDO circuit. The larger the capacitance value of the internal compensation capacitor, the larger the chip area is occupied. Therefore, it is desirable to reduce the capacitance value of the internal compensation capacitor as much as possible without affecting the stability of the LDO circuit.
Disclosure of Invention
Embodiments described herein provide a low dropout linear regulator.
According to a first aspect of the present disclosure, a low dropout linear regulator is provided. The low dropout linear regulator includes: the power supply circuit comprises a first bias voltage generating circuit, a second bias voltage generating circuit, an error amplifier, an output power tube, a feedback circuit and a first capacitor. Wherein the first bias voltage generating circuit is configured to: a first bias voltage is generated and provided to a first load circuit in the error amplifier via a first node. The second bias voltage generating circuit is configured to: a second bias voltage is generated and provided to a second load circuit in the error amplifier via a second node. The error amplifier is configured to: an error voltage is generated based on the reference voltage from the reference voltage terminal and the feedback voltage from the feedback circuit, and is provided to the control electrode of the output power tube. The first pole of the output power tube is coupled with the input voltage end. The second pole of the output power tube is coupled with the output voltage end. The feedback circuit is configured to: the output voltage of the low dropout linear regulator is divided to generate a feedback voltage. The first end of the first capacitor is coupled to the output voltage end. The second terminal of the first capacitor is coupled to the second node.
In some embodiments of the present disclosure, the error amplifier includes: a first constant current source, a differential input circuit, a first load circuit, a second load circuit, and an error voltage generation circuit. Wherein the differential input circuit is configured to: the first and second branches are generated from the reference voltage, the feedback voltage, and the first constant current from the first constant current source, the first branch is output via the third node, and the second branch is output via the fourth node. Wherein the sum of the first shunt and the second shunt is equal to the first constant current. The ratio of the first and second branches is inversely proportional to the voltage difference between the reference voltage and the feedback voltage. The first load circuit is configured to: a first load current is generated from the voltage of the first node and is output via the third node. The second load circuit is configured to: a second load current is generated according to the voltage of the second node, and the second load current is output via the fourth node. The error voltage generation circuit is configured to: an error voltage is generated from the voltage of the third node and the voltage of the fourth node.
In some embodiments of the present disclosure, a differential input circuit includes: a first transistor, and a second transistor. The control electrode of the first transistor is coupled to the reference voltage terminal. The first pole of the first transistor is coupled to the first pole of the second transistor and the first constant current source. The second pole of the first transistor is coupled to the third node. The control electrode of the second transistor is coupled to the feedback circuit. The second electrode of the second transistor is coupled to the fourth node.
In some embodiments of the present disclosure, the first load circuit includes: and a third transistor. The control electrode of the third transistor is coupled to the first node. The first electrode of the third transistor is coupled to the second voltage terminal.
The second pole of the third transistor is coupled to the third node.
In some embodiments of the present disclosure, the second load circuit includes: and a fourth transistor. The control electrode of the fourth transistor is coupled to the second node. The first electrode of the fourth transistor is coupled to the second voltage terminal.
The second pole of the fourth transistor is coupled to the fourth node.
In some embodiments of the present disclosure, the error voltage generation circuit includes: fifth to tenth transistors. The control electrode of the fifth transistor is coupled to the third bias voltage terminal. The first pole of the fifth transistor is coupled to the fourth node. The second pole of the fifth transistor is coupled to the first pole of the seventh transistor. The control electrode of the sixth transistor is coupled to the third bias voltage terminal. The first electrode of the sixth transistor is coupled to the third node. The second pole of the sixth transistor is coupled to the first pole of the eighth transistor. The control electrode of the seventh transistor is coupled to the first voltage terminal. The second pole of the seventh transistor is coupled to the control pole of the ninth transistor and the control poles of the second and tenth transistors. The control electrode of the eighth transistor is coupled to the first voltage terminal. The second pole of the eighth transistor is coupled to the second pole of the tenth transistor and the control pole of the output power transistor. A first pole of the ninth transistor is coupled to the input voltage terminal and a first pole of the tenth transistor.
In some embodiments of the present disclosure, the first bias voltage generating circuit includes: an eleventh transistor, a twelfth transistor, and a first resistor. Wherein a first terminal of the first resistor is coupled to the first reference current source and the gate of the eleventh transistor. The second terminal of the first resistor is coupled to the second pole of the eleventh transistor, the control pole of the twelfth transistor, and the first node. The first pole of the eleventh transistor is coupled to the second pole of the twelfth transistor. The first pole of the twelfth transistor is coupled to the second voltage terminal.
In some embodiments of the present disclosure, the second bias voltage generating circuit includes: a thirteenth transistor, a fourteenth transistor, and a second resistor. Wherein a first terminal of the second resistor is coupled to the second reference current source and the gate of the thirteenth transistor. The second terminal of the second resistor is coupled to the second pole of the thirteenth transistor, the control pole of the fourteenth transistor and the second node. The first pole of the thirteenth transistor is coupled to the second pole of the fourteenth transistor. The first pole of the fourteenth transistor is coupled to the second voltage terminal.
In some embodiments of the present disclosure, the ratio of the width to length ratio of the fourteenth transistor to the fourth transistor is 1: K. the ratio of the width to length ratio of the twelfth transistor to the third transistor is 1: K. the ratio of the width to length ratio of the fourteenth transistor to the twelfth transistor is 1:1.k is greater than 1.
In some embodiments of the present disclosure, the feedback circuit includes: a third resistor and a fourth resistor. The first end of the third resistor is coupled to the first end of the fourth resistor and the output end of the feedback circuit. The second end of the third resistor is coupled to the output voltage end. The second terminal of the fourth resistor is coupled to the second voltage terminal.
In some embodiments of the present disclosure, the low dropout linear regulator further comprises: and a protection circuit. Wherein the protection circuit is configured to: the voltage difference between the control pole and the first pole of the output power tube is limited.
In some embodiments of the present disclosure, the protection circuit includes: a fifteenth transistor and a sixteenth transistor. The control electrode of the fifteenth transistor is coupled to the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor. The first pole of the fifteenth transistor is coupled to the input voltage terminal. The control electrode of the sixteenth transistor is coupled to the second electrode of the sixteenth transistor and the control electrode of the output power transistor.
In some embodiments of the present disclosure, the protection circuit further comprises: a zener diode. The anode of the zener diode is coupled with the control electrode of the output power tube. The cathode of the zener diode is coupled to the input voltage terminal.
According to a second aspect of the present disclosure, a low dropout linear regulator is provided. The low dropout linear regulator includes: an output power transistor, first to sixteenth transistors, a first capacitor, first to fourth resistors, and a first constant current source. The control electrode of the first transistor is coupled to the reference voltage terminal. The first pole of the first transistor is coupled to the first pole of the second transistor and the first constant current source. The second pole of the first transistor is coupled to the second pole of the third transistor and the first pole of the sixth transistor. The control electrode of the second transistor is coupled to the first end of the third resistor and the first end of the fourth resistor. The second pole of the second transistor is coupled to the second pole of the fourth transistor and the first pole of the fifth transistor. The control electrode of the third transistor is coupled to the second electrode of the eleventh transistor and the control electrode of the twelfth transistor. The first electrode of the third transistor is coupled to the second voltage terminal. The control electrode of the fourth transistor is coupled to the second electrode of the thirteenth transistor and the control electrode of the fourteenth transistor. The first electrode of the fourth transistor is coupled to the second voltage terminal. The control electrode of the fifth transistor is coupled to the third bias voltage terminal. The second pole of the fifth transistor is coupled to the first pole of the seventh transistor. The control electrode of the sixth transistor is coupled to the third bias voltage terminal. The second pole of the sixth transistor is coupled to the first pole of the eighth transistor. The control electrode of the seventh transistor is coupled to the first voltage terminal. The second pole of the seventh transistor is coupled to the control pole of the ninth transistor and the control poles of the second and tenth transistors. The control electrode of the eighth transistor is coupled to the first voltage terminal. The second pole of the eighth transistor is coupled to the second pole of the tenth transistor and the control pole of the output power transistor. A first pole of the ninth transistor is coupled to the input voltage terminal and a first pole of the tenth transistor. A first terminal of the first resistor is coupled to the first reference current source and the gate of the eleventh transistor. The second terminal of the first resistor is coupled to the second pole of the eleventh transistor. The first pole of the eleventh transistor is coupled to the second pole of the twelfth transistor. The first pole of the twelfth transistor is coupled to the second voltage terminal. The first terminal of the second resistor is coupled to the second reference current source and the gate of the thirteenth transistor. The second end of the second resistor is coupled to the second pole of the thirteenth transistor. The first pole of the thirteenth transistor is coupled to the second pole of the fourteenth transistor. The first pole of the fourteenth transistor is coupled to the second voltage terminal. The first pole of the output power tube is coupled with the input voltage end. The second pole of the output power tube is coupled with the output voltage end and the second end of the third resistor. The second terminal of the fourth resistor is coupled to the second voltage terminal. The control electrode of the fifteenth transistor is coupled to the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor. The first pole of the fifteenth transistor is coupled to the input voltage terminal. The control electrode of the sixteenth transistor is coupled to the second electrode of the sixteenth transistor and the control electrode of the output power transistor. The first end of the first capacitor is coupled to the output voltage end. The second terminal of the first capacitor is coupled to the control electrode of the fourth transistor.
In some embodiments of the present disclosure, the ratio of the width to length ratio of the fourteenth transistor to the fourth transistor is 1: K. the ratio of the width to length ratio of the twelfth transistor to the third transistor is 1: K. the ratio of the width to length ratio of the fourteenth transistor to the twelfth transistor is 1:1.k is greater than 1.
In some embodiments of the present disclosure, the low dropout linear regulator further comprises: a zener diode. The anode of the zener diode is coupled with the control electrode of the output power tube. The cathode of the zener diode is coupled to the input voltage terminal.
According to a third aspect of the present disclosure, a chip is provided. The chip comprises a low dropout linear regulator according to the first or second aspect of the present disclosure.
According to a fourth aspect of the present disclosure, an electronic device is provided. The electronic device comprises a chip according to the third aspect of the present disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:
FIG. 1 is an exemplary circuit diagram of a low dropout linear regulator;
FIG. 2 is a schematic block diagram of a low dropout linear regulator according to an embodiment of the present disclosure;
FIG. 3 is an exemplary circuit diagram of a low dropout linear regulator according to an embodiment of the present disclosure; and
fig. 4 is another exemplary circuit diagram of a low dropout linear regulator according to an embodiment of the present disclosure.
In the drawings, the last two digits are identical to the elements. It is noted that the elements in the drawings are schematic and are not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
In all embodiments of the present disclosure, since the source and drain of a Metal Oxide Semiconductor (MOS) transistor are symmetrical and the on-current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control pole and the remaining two terminals of the MOS transistor are referred to as the first pole and the second pole, respectively. In addition, for convenience of unified expression, in the context, the base of a bipolar transistor (BJT) is referred to as a control electrode, the emitter of the BJT is referred to as a first electrode, and the collector of the BJT is referred to as a second electrode. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
Fig. 1 shows an exemplary circuit diagram of a low dropout linear regulator. The low dropout linear regulator 100 includes: error amplifier 110, output power tube Mout, resistor Rf1, resistor Rf2, and miller capacitor Cc. The error amplifier 110 includes a current source I1, and first to tenth transistors M1 to M10. In the example of fig. 1, vdd a represents the power supply of the error amplifier 110, vssa represents the ground potential, AVCC represents the input voltage of the low dropout linear regulator 100, and Vreg represents the output voltage of the low dropout linear regulator 100. The gates of the fifth transistor M5 and the sixth transistor M6 are coupled to the third bias voltage terminal Vb3. The gates of the third transistor M3 and the fourth transistor M4 are coupled to the fourth bias voltage terminal Vb4. Also shown in the example of fig. 1 are an external load current source Iload and an external load capacitor Cload.
In the low dropout linear regulator 100, there are two poles, one at the control pole of the output power tube Mout and the other at the second pole of the output power tube Mout. The miller capacitor Cc is coupled to the output voltage terminal (i.e., the second pole of the output power transistor Mout) and the second pole of the third transistor M3. The placement of the miller capacitor Cc (as an internal compensation capacitor) in the low dropout linear regulator 100 can separate the two poles in the low dropout linear regulator 100 from each other in the frequency domain to maintain the stability of the output voltage Vreg.
The equivalent capacitance value of the miller capacitor Cc can be calculated as: c (C) req1 Gm_out×ro×cc. Where gm_out represents the transconductance of the output power tube Mout, ro represents the equivalent output resistance value of the output voltage terminal, and Cc represents the capacitance value of the miller capacitor Cc.
The capacitance value of the miller capacitor Cc is generally large. If the capacitance value of the miller capacitor Cc can be reduced without affecting the stability of the output voltage Vreg, the area of a chip using the low dropout linear regulator can be reduced.
Embodiments of the present disclosure provide a low dropout linear regulator capable of ensuring stable and normal operation of the low dropout linear regulator while significantly reducing an internal compensation capacitance value (capacitance value of a miller capacitor). Fig. 2 shows a schematic block diagram of a low dropout linear regulator 200 according to an embodiment of the present disclosure. The low dropout linear regulator 200 includes: a first bias voltage generating circuit 220, a second bias voltage generating circuit 230, an error amplifier 210, an output power tube Mout, a feedback circuit 240, and a first capacitor Cc.
The first bias voltage generating circuit 220 is coupled to a first load circuit (not shown in fig. 2) in the error amplifier 210 via a first node N1. The first bias voltage generating circuit 220 is configured to: a first bias voltage is generated and provided to a first load circuit in the error amplifier 210 via a first node N1. In some embodiments of the present disclosure, the first bias voltage generating circuit 220 may generate the first bias voltage according to the first reference current Iref 1.
The second bias voltage generating circuit 230 is coupled to a second load circuit (not shown in fig. 2) in the error amplifier 210 via a second node N2. The second bias voltage generating circuit 230 is configured to: a second bias voltage is generated and provided to a second load circuit in error amplifier 210 via a second node N2. In some embodiments of the present disclosure, the second bias voltage generating circuit 230 may generate the second bias voltage according to the second reference current Iref 2.
The error amplifier 210 is coupled to the first bias voltage generating circuit 220 via the first node N1. The error amplifier 210 is coupled to the second bias voltage generating circuit 230 via a second node N2. The error amplifier 210 is configured to: an error voltage is generated based on the reference voltage Vref from the reference voltage terminal and the feedback voltage Vfb from the feedback circuit 240, and is supplied to the control electrode of the output power tube Mout.
The control electrode of the output power tube Mout is coupled to the output terminal of the error amplifier 210. The first pole of the output power tube Mout is coupled to the input voltage end AVCC. The second pole of the output power tube Mout is coupled to the output voltage terminal. The low dropout linear regulator 200 outputs an output voltage Vreg from the output voltage terminal.
Feedback circuit 240 is coupled to the output voltage terminal and error amplifier 210. The feedback circuit 240 is configured to: the output voltage Vreg of the low dropout linear regulator 200 is divided to generate the feedback voltage Vfb.
A first terminal of a first capacitor Cc (which may also be referred to as a miller capacitor or a compensation capacitor) is coupled to the output voltage terminal. A second terminal of the first capacitor Cc is coupled to the second node N2 (i.e., an output terminal of the second bias voltage generating circuit 230).
The low dropout linear regulator 200 according to the embodiment of the present disclosure uses two bias voltage generating circuits (the first bias voltage generating circuit 220 and the second bias voltage generating circuit 230) to supply bias voltages to two load circuits in the error amplifier 210, respectively, and causes the first capacitor Cc to be coupled between the output voltage terminal and the input terminal of the second load circuit (the output terminal of the second bias voltage generating circuit 230), so that the alternating-current variation amount of the output voltage Vreg is transferred to only the second load circuit and not to the first load circuit. The second load circuit can amplify the alternating current variation of the output voltage Vreg, so that the current variation at the control electrode of the output power tube Mout is amplified. The equivalent capacitance value of the first capacitor Cc may be calculated as: c (C) req2 ＝K×gm_out×ro×Cc. Where gm_out represents the transconductance of the output power tube Mout, ro represents the equivalent output resistance value of the output voltage terminal, cc represents the capacitance value of the first capacitor Cc, and K represents the amplification factor of the current variation at the control electrode of the output power tube Mout. K is greater than 1. So that the equivalent compensation capacitance of the first capacitor Cc becomes K times larger. Therefore, in comparison with the example of fig. 1, in the case where the equivalent compensation capacitances are equal, the capacitance value of the first capacitor Cc may be reduced, thereby reducing the area of the low dropout linear regulator 200.
Fig. 3 illustrates an exemplary circuit diagram of a low dropout linear regulator 300 according to an embodiment of the present disclosure. Also shown in the example of fig. 3 are an external load current source Iload and an external load capacitor Cload.
In the low dropout linear regulator 300 shown in fig. 3, the error amplifier 310 includes: a first constant current source I1, a differential input circuit 311, a first load circuit 312, a second load circuit 313, and an error voltage generation circuit 314.
The first constant current source I1 may be coupled to the first voltage terminal V1. The first constant current source I1 is configured to output a first constant current I1.
The differential input circuit 311 is coupled to the first constant current source I1, the reference voltage terminal and the output terminal of the feedback circuit 340. The differential input circuit 311 is coupled to the first load circuit 312 and the error voltage generation circuit 314 via a third node N3. The differential input circuit 311 is coupled to the second load circuit 313 and the error voltage generation circuit 314 via a fourth node N4. The differential input circuit 311 is configured to: the first and second branches Is1 and Is2 are generated from the reference voltage Vref, the feedback voltage Vfb, and the first constant current I1 from the first constant current source I1, the first branch Is1 Is output via the third node N3, and the second branch Is2 Is output via the fourth node N4. Wherein the sum of the first and second branches Is1 and Is2 Is equal to the first constant current I1. The ratio of the first and second branches Is1 and Is2 Is inversely proportional to the voltage difference between the reference voltage Vref and the feedback voltage Vfb. When the voltage difference between the reference voltage Vref and the feedback voltage Vfb increases, the ratio of the first shunt Is1 and the second shunt Is2 decreases, and thus the first shunt Is1 decreases and the second shunt Is2 increases. When the voltage difference between the reference voltage Vref and the feedback voltage Vfb decreases, the ratio of the first shunt Is1 and the second shunt Is2 increases, and thus the first shunt Is1 increases and the second shunt Is2 decreases.
The first load circuit 312 is coupled to the first bias voltage generating circuit 320 via the first node N1. The first load circuit 312 is coupled to the differential input circuit 311 and the error voltage generation circuit 314 via a third node N3. The first load circuit 312 is configured to: the first load current is generated according to the voltage of the first node N1 and is output via the third node N3.
The second load circuit 313 is coupled to the second bias voltage generating circuit 330 via a second node N2. The second load circuit 313 is coupled to the differential input circuit 311 and the error voltage generation circuit 314 via a fourth node N4. The second load circuit 313 is configured to: the second load current is generated according to the voltage of the second node N2 and is output via the fourth node N4.
The error voltage generation circuit 314 is coupled to the differential input circuit 311 and the first load circuit 312 via a third node N3. The error voltage generation circuit 314 is coupled to the differential input circuit 311 and the second load circuit 313 via a fourth node N4. The error voltage generation circuit 314 is configured to: the error voltage is generated according to the voltage of the third node N3 and the voltage of the fourth node N4. The voltage of the third node N3 Is determined from the first shunt Is1 and the first load current. The voltage of the fourth node N3 Is determined from the second shunt Is2 and the second load current.
In some embodiments of the present disclosure, the error voltage corresponds to an amplified value of the voltage difference between the reference voltage Vref and the feedback voltage Vfb.
In the example of fig. 3, the differential input circuit 311 includes: a first transistor M1, and a second transistor M2. The control electrode of the first transistor M1 is coupled to the reference voltage terminal. A first pole of the first transistor M1 is coupled to a first pole of the second transistor M2 and the first constant current source I1. The second pole of the first transistor M1 is coupled to the third node N3. The control electrode of the second transistor M2 is coupled to the feedback circuit 340. The second diode of the second transistor M2 is coupled to the fourth node N4.
The first load circuit 312 includes: and a third transistor M3. The control electrode of the third transistor M3 is coupled to the first node N1. The first pole of the third transistor M3 is coupled to the second voltage terminal V2. The second pole of the third transistor M3 is coupled to the third node N3.
The second load circuit 313 includes: and a fourth transistor M4. The control electrode of the fourth transistor M4 is coupled to the second node N2. The first pole of the fourth transistor M4 is coupled to the second voltage terminal V2. The second pole of the fourth transistor M4 is coupled to the fourth node N4.
The error voltage generation circuit 314 includes: fifth to tenth transistors M5 to M10. The gate of the fifth transistor M5 is coupled to the third bias voltage terminal Vb3. The first pole of the fifth transistor M5 is coupled to the fourth node N4. The second pole of the fifth transistor M5 is coupled to the first pole of the seventh transistor M7. The control electrode of the sixth transistor M6 is coupled to the third bias voltage terminal Vb3. The first pole of the sixth transistor M6 is coupled to the third node N3. The second pole of the sixth transistor M6 is coupled to the first pole of the eighth transistor M8. The control electrode of the seventh transistor M7 is coupled to the first voltage terminal V1. The second pole of the seventh transistor M7 is coupled to the control pole of the ninth transistor M9 and the control pole of the tenth transistor M10. The gate of the eighth transistor M8 is coupled to the first voltage terminal V1. The second pole of the eighth transistor M8 is coupled to the second pole of the tenth transistor M10 and the control pole of the output power transistor Mout. A first pole of the ninth transistor M9 is coupled to the input voltage terminal AVCC and a first pole of the tenth transistor M10.
The first bias voltage generating circuit 320 includes: an eleventh transistor M11, a twelfth transistor M12, and a first resistor R1. Wherein a first end of the first resistor R1 is coupled to the first reference current source Iref1 and the control electrode of the eleventh transistor M11. The second terminal of the first resistor R1 is coupled to the second terminal of the eleventh transistor M11, the control terminal of the twelfth transistor M12, and the first node N1. The first pole of the eleventh transistor M11 is coupled to the second pole of the twelfth transistor M12. The first pole of the twelfth transistor M12 is coupled to the second voltage terminal V2.
The second bias voltage generating circuit 330 includes: a thirteenth transistor M13, a fourteenth transistor M14, and a second resistor R2. The first end of the second resistor R2 is coupled to the second reference current source Iref2 and the control electrode of the thirteenth transistor M13. A second terminal of the second resistor R2 is coupled to the second pole of the thirteenth transistor M13, the control pole of the fourteenth transistor M14 and the second node N2. The first pole of the thirteenth transistor M13 is coupled to the second pole of the fourteenth transistor M14. The first pole of the fourteenth transistor M14 is coupled to the second voltage terminal V2.
The feedback circuit 340 includes: a third resistor R3 and a fourth resistor R4. The first end of the third resistor R3 is coupled to the first end of the fourth resistor R4 and to the output of the feedback circuit 340. The second terminal of the third resistor R3 is coupled to the output voltage terminal. The second terminal of the fourth resistor R4 is coupled to the second voltage terminal V2. In one example, r3:r4=13:4, where R3 represents the resistance value of the third resistor R3 and R4 represents the resistance value of the fourth resistor R4.
In the example of fig. 3, the fourteenth transistor M14 and the fourth transistor M4 may form a current mirror. The twelfth transistor M12 and the third transistor M3 may form a current mirror. The ratio of the width to length ratio of the fourteenth transistor M14 to the fourth transistor M4 may be set to 1: the ratio of the width to length ratio of the twelfth transistor M12 to the third transistor M3 is 1: the ratio of the width to length ratio of the fourteenth transistor M14 to the twelfth transistor M12 is 1:1.k is greater than 1. Thus, the equivalent capacitance value of the first capacitor Cc can be calculated as: c (C) req2 =k×gm_out×ro×cc. Where gm_out represents the transconductance of the output power tube Mout, ro represents the equivalent output resistance value of the output voltage terminal, and Cc represents the capacitance value of the first capacitor Cc. Therefore, in comparison with the example of fig. 1, in the case where the equivalent compensation capacitances are equal, the capacitance value of the first capacitor Cc may be reduced, thereby reducing the area of the low dropout linear regulator 300.
It will be appreciated by those skilled in the art that the internal structures of the error amplifier 310, the first bias voltage generating circuit 320, the second bias voltage generating circuit 330, and the feedback circuit 340 in fig. 3 are exemplary, and the error amplifier 310, the first bias voltage generating circuit 320, the second bias voltage generating circuit 330, and the feedback circuit 340 may be implemented by other circuits. Embodiments of the present disclosure are not limited to a particular implementation of error amplifier 310, first bias voltage generation circuit 320, second bias voltage generation circuit 330, and feedback circuit 340.
Fig. 4 illustrates another exemplary circuit diagram of a low dropout linear regulator 400 according to an embodiment of the present disclosure. On the basis of the low dropout linear regulator 300 shown in fig. 3, the low dropout linear regulator 400 further includes: a protection circuit 450. The protection circuit 450 is coupled to the control pole and the first pole of the output power transistor Mout. The protection circuit 450 is configured to: the voltage difference between the control pole and the first pole of the output power tube Mout is limited.
In some embodiments of the present disclosure, the protection circuit 450 includes: a fifteenth transistor M15 and a sixteenth transistor M16. The control electrode of the fifteenth transistor M15 is coupled to the second electrode of the fifteenth transistor M15 and the first electrode of the sixteenth transistor M16. A first pole of the fifteenth transistor M15 is coupled to the input voltage terminal AVCC. The control electrode of the sixteenth transistor M16 is coupled to the second electrode of the sixteenth transistor M16 and the control electrode of the output power transistor Mout.
In some embodiments of the present disclosure, the protection circuit 450 further includes: a zener diode Z1. The anode of the zener diode Z1 is coupled to the control electrode of the output power tube Mout. The cathode of the zener diode Z1 is coupled to the input voltage terminal AVCC. Fig. 4 shows an exemplary circuit diagram of the protection circuit 450 including the fifteenth transistor M15, the sixteenth transistor M16, and the zener diode Z1.
The protection circuit 450 can prevent the gate oxide of the output power transistor Mout from being broken down in case of transient increase of the input voltage.
In the examples of fig. 3 and 4, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1, the second transistor M2, the ninth transistor M9, and the tenth transistor M10 are PMOS transistors. The third to eighth transistors M3 to M8, the eleventh to sixteenth transistors M11 to M16 are NMOS transistors. The seventh transistor M7, the eighth transistor M8, and the output power transistor Mout are high voltage transistors. It will be appreciated by those skilled in the art that variations of the circuits shown in fig. 3 and 4 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different settings from the examples shown in fig. 3 and 4.
The embodiment of the disclosure also provides a chip. The chip includes a low dropout linear regulator according to an embodiment of the present disclosure. The chip is, for example, a power management type chip.
The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is for example a smart terminal device such as a tablet computer, a smart phone or the like.
In summary, the low dropout linear regulator according to the embodiments of the present disclosure can ensure the stability and the normal operation of the low dropout linear regulator while significantly reducing the internal compensation capacitance. Therefore, the area of a chip including the low dropout linear regulator according to the embodiments of the present disclosure can be significantly reduced.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (10)
1. A low dropout linear regulator comprising: a first bias voltage generating circuit, a second bias voltage generating circuit, an error amplifier, an output power tube, a feedback circuit, and a first capacitor,
wherein the first bias voltage generating circuit is configured to: generating a first bias voltage and providing the first bias voltage to a first load circuit in the error amplifier via a first node;
the second bias voltage generating circuit is configured to: generating a second bias voltage and providing the second bias voltage to a second load circuit in the error amplifier via a second node;
the error amplifier is configured to: generating an error voltage according to a reference voltage from a reference voltage end and a feedback voltage from the feedback circuit, and providing the error voltage to a control electrode of the output power tube;
the first pole of the output power tube is coupled with the input voltage end, and the second pole of the output power tube is coupled with the output voltage end;
the feedback circuit is configured to: dividing an output voltage of the low dropout linear regulator to generate the feedback voltage;
the first end of the first capacitor is coupled to the output voltage end, and the second end of the first capacitor is coupled to the second node.
2. The low dropout linear regulator according to claim 1, wherein said error amplifier comprises: a first constant current source, a differential input circuit, a first load circuit, a second load circuit, and an error voltage generation circuit,
wherein the differential input circuit is configured to: generating a first shunt and a second shunt according to the reference voltage, the feedback voltage and a first constant current from a first constant current source, outputting the first shunt via a third node, and outputting the second shunt via a fourth node, wherein the sum of the first shunt and the second shunt is equal to the first constant current, and the ratio of the first shunt and the second shunt is inversely proportional to the voltage difference between the reference voltage and the feedback voltage;
the first load circuit is configured to: generating a first load current according to the voltage of the first node, and outputting the first load current via the third node;
the second load circuit is configured to: generating a second load current according to the voltage of the second node, and outputting the second load current via the fourth node;
the error voltage generation circuit is configured to: the error voltage is generated from the voltage of the third node and the voltage of the fourth node.
3. The low dropout linear regulator according to claim 2, wherein said differential input circuit comprises: a first transistor, and a second transistor,
the control electrode of the first transistor is coupled to the reference voltage end, the first electrode of the first transistor is coupled to the first electrode of the second transistor and the first constant current source, and the second electrode of the first transistor is coupled to the third node;
the control electrode of the second transistor is coupled to the feedback circuit, and the second electrode of the second transistor is coupled to the fourth node.
4. The low dropout linear regulator according to claim 2, wherein said first load circuit includes: a third transistor is provided which is connected to the first transistor,
the control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the second voltage terminal, and the second electrode of the third transistor is coupled to the third node.
5. The low dropout linear regulator according to claim 4, wherein said second load circuit comprises: a fourth transistor is provided which is connected to the first transistor,
the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the fourth node.
6. The low dropout linear regulator according to any one of claims 2 to 5, wherein the error voltage generating circuit includes: the fifth transistor to the tenth transistor,
the control electrode of the fifth transistor is coupled to the third bias voltage end, the first electrode of the fifth transistor is coupled to the fourth node, and the second electrode of the fifth transistor is coupled to the first electrode of the seventh transistor;
a control electrode of a sixth transistor is coupled to the third bias voltage terminal, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the first electrode of the eighth transistor;
the control electrode of the seventh transistor is coupled to the first voltage end, and the second electrode of the seventh transistor is coupled to the control electrode and the second electrode of the ninth transistor and the control electrode of the tenth transistor;
the control electrode of the eighth transistor is coupled with the first voltage end, and the second electrode of the eighth transistor is coupled with the second electrode of the tenth transistor and the control electrode of the output power tube;
a first pole of the ninth transistor is coupled to the input voltage terminal and a first pole of the tenth transistor.
7. The low dropout linear regulator according to claim 5, wherein said first bias voltage generating circuit comprises: an eleventh transistor, a twelfth transistor, and a first resistor,
wherein a first end of the first resistor is coupled to a first reference current source and a control electrode of the eleventh transistor, and a second end of the first resistor is coupled to a second electrode of the eleventh transistor, a control electrode of the twelfth transistor, and the first node;
a first pole of the eleventh transistor is coupled to a second pole of the twelfth transistor;
the first pole of the twelfth transistor is coupled to the second voltage terminal.
8. The low dropout linear regulator according to claim 7, wherein said second bias voltage generating circuit comprises: a thirteenth transistor, a fourteenth transistor, and a second resistor,
wherein a first end of the second resistor is coupled to a second reference current source and a control electrode of the thirteenth transistor, and a second end of the second resistor is coupled to a second electrode of the thirteenth transistor, a control electrode of the fourteenth transistor, and the second node;
a first pole of the thirteenth transistor is coupled to a second pole of the fourteenth transistor;
the first pole of the fourteenth transistor is coupled with the second voltage terminal;
wherein a ratio of the width to length ratio of the fourteenth transistor to the fourth transistor is 1: k, the ratio of the width-to-length ratio of the twelfth transistor to the third transistor is 1: k, the ratio of the width-to-length ratio of the fourteenth transistor to the twelfth transistor is 1:1, K is greater than 1.
9. The low dropout linear regulator according to any one of claims 1 to 5 and 7 to 8, further comprising: the protection circuit is used for protecting the circuit,
wherein the protection circuit is configured to: the voltage difference between the control pole and the first pole of the output power tube is limited.
10. A low dropout linear regulator comprising: an output power transistor, first to sixteenth transistors, a first capacitor, first to fourth resistors, and a first constant current source,
the control electrode of the first transistor is coupled with the reference voltage end, the first electrode of the first transistor is coupled with the first electrode of the second transistor and the first constant current source, and the second electrode of the first transistor is coupled with the second electrode of the third transistor and the first electrode of the sixth transistor;
a control electrode of the second transistor is coupled to the first end of the third resistor and the first end of the fourth resistor, and a second electrode of the second transistor is coupled to the second electrode of the fourth transistor and the first electrode of the fifth transistor;
the control electrode of the third transistor is coupled with the second electrode of the eleventh transistor and the control electrode of the twelfth transistor, and the first electrode of the third transistor is coupled with the second voltage end;
the control electrode of the fourth transistor is coupled with the second electrode of the thirteenth transistor and the control electrode of the fourteenth transistor, and the first electrode of the fourth transistor is coupled with the second voltage end;
the control electrode of the fifth transistor is coupled with the third bias voltage end, and the second electrode of the fifth transistor is coupled with the first electrode of the seventh transistor;
the control electrode of the sixth transistor is coupled to the third bias voltage terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the eighth transistor;
the control electrode of the seventh transistor is coupled to the first voltage end, and the second electrode of the seventh transistor is coupled to the control electrode of the ninth transistor, the second electrode and the control electrode of the tenth transistor;
the control electrode of the eighth transistor is coupled with the first voltage end, and the second electrode of the eighth transistor is coupled with the second electrode of the tenth transistor and the control electrode of the output power tube;
a first pole of the ninth transistor is coupled to an input voltage terminal and a first pole of the tenth transistor;
a first end of the first resistor is coupled with a first reference current source and a control electrode of the eleventh transistor, and a second end of the first resistor is coupled with a second electrode of the eleventh transistor;
a first pole of the eleventh transistor is coupled to a second pole of the twelfth transistor;
a first pole of the twelfth transistor is coupled to the second voltage terminal;
a first end of the second resistor is coupled with a second reference current source and a control electrode of the thirteenth transistor, and a second end of the second resistor is coupled with a second electrode of the thirteenth transistor;
a first pole of the thirteenth transistor is coupled to a second pole of the fourteenth transistor;
a first pole of the fourteenth transistor is coupled to the second voltage terminal;
the first pole of the output power tube is coupled with the input voltage end, and the second pole of the output power tube is coupled with the output voltage end and the second end of the third resistor;
a second end of the fourth resistor is coupled to the second voltage end;
a control electrode of a fifteenth transistor is coupled to the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor, and the first electrode of the fifteenth transistor is coupled to the input voltage terminal;
a control electrode of the sixteenth transistor is coupled with a second electrode of the sixteenth transistor and a control electrode of the output power tube;
the first end of the first capacitor is coupled with the output voltage end, and the second end of the first capacitor is coupled with the control electrode of the fourth transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310186692.2A CN116501117A (en) | 2023-02-21 | 2023-02-21 | Low-dropout linear voltage regulator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310186692.2A CN116501117A (en) | 2023-02-21 | 2023-02-21 | Low-dropout linear voltage regulator |
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| CN202310186692.2A Pending CN116501117A (en) | 2023-02-21 | 2023-02-21 | Low-dropout linear voltage regulator |
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