CN116520114A - MOS type semiconductor device testing equipment - Google Patents
MOS type semiconductor device testing equipment Download PDFInfo
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- CN116520114A CN116520114A CN202310225572.9A CN202310225572A CN116520114A CN 116520114 A CN116520114 A CN 116520114A CN 202310225572 A CN202310225572 A CN 202310225572A CN 116520114 A CN116520114 A CN 116520114A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000012360 testing method Methods 0.000 title claims abstract description 54
- 239000000523 sample Substances 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000005259 measurement Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 102100030393 G-patch domain and KOW motifs-containing protein Human genes 0.000 description 9
- 101150090280 MOS1 gene Proteins 0.000 description 9
- 101100401568 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MIC10 gene Proteins 0.000 description 9
- 229910052982 molybdenum disulfide Inorganic materials 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000035882 stress Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000032683 aging Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The present disclosure provides a MOS semiconductor device testing apparatus. The method comprises the following steps: the carrier is used for carrying the tested MOS type semiconductor device and is in conductive contact with the drain/collector of the tested MOS type semiconductor device; a substrate including an insulating base, a driving circuit, a switching control circuit, and a threshold value measuring circuit provided on the insulating base; and one or more pairs of probes are fixed on the insulating substrate and are electrically connected with the switching control circuit, the switching control circuit is used for controlling the on-off of any pair of probes and the driving circuit and the on-off of the threshold measurement circuit, wherein any pair of probes are used for respectively conducting contact with the grid electrode and the source/emitter of one MOS type semiconductor device to be tested, and the substrate can move so that the probes are separated from or contact with the MOS type semiconductor device to be tested. The equipment has higher test accuracy.
Description
Technical Field
The disclosure belongs to the technical field of semiconductor device testing, and in particular relates to testing equipment for MOS (metal oxide semiconductor) semiconductor devices.
Background
This section is intended to provide a background or context for the embodiments recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
The MOS semiconductor device is, for example, a metal-oxide semiconductor field effect transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), or the like. The threshold voltage stability of MOS semiconductor devices is relatively poor. It is necessary to test the threshold voltage stability of the MOS type semiconductor device.
Disclosure of Invention
The present disclosure provides a MOS semiconductor device testing apparatus.
The technical scheme adopted by the present disclosure is as follows: a MOS semiconductor device testing apparatus comprising:
the carrier is used for carrying the tested MOS type semiconductor device and is in conductive contact with the drain/collector of the tested MOS type semiconductor device;
a substrate including an insulating base, a driving circuit, a switching control circuit, and a threshold value measuring circuit provided on the insulating base;
the switch control circuit is used for controlling the on-off of any pair of probes and the drive circuit and the threshold measurement circuit, wherein any pair of probes are used for respectively conducting and contacting a grid electrode and a source/emitter electrode of a tested MOS type semiconductor device, the substrate is movable to be separated from or contacted with the tested MOS type semiconductor device, the source/emitter electrode and the grid electrode of the tested MOS type semiconductor device are positioned on a first side surface of the tested MOS type semiconductor device, and the drain/collector electrode of the tested MOS type semiconductor device is positioned on a second side surface of the tested MOS type semiconductor device opposite to the first side surface.
In some embodiments, the MOS-type semiconductor device under test is a MOSFET or an IGBT.
In some embodiments, the number of probes is a plurality of pairs, and the number of driving circuits and the threshold measurement circuits are each a plurality of and correspond to the pairs of probes one to one.
The technical scheme adopted by the present disclosure is as follows: a MOS semiconductor device testing apparatus comprising:
the carrier is used for carrying the tested MOS type semiconductor device and is in conductive contact with the drain/collector of the tested MOS type semiconductor device;
the probe board comprises a first insulating substrate and a wire arranged on the first insulating substrate;
a driving board including a second insulating substrate, a driving circuit disposed on the second insulating substrate, a switching control circuit, and a threshold measurement circuit;
a plurality of connection lines connecting the probe card and the drive board;
the pair or the pairs of probes are fixed on the first insulating substrate and are electrically connected with the switching control circuit through the lead and the connecting wire, and the switching control circuit is used for controlling the on-off of any pair of probes and the driving circuit and the threshold measuring circuit;
wherein any pair of probes is used for respectively conducting and contacting a grid electrode and a source/emitter electrode of a tested MOS type semiconductor device, and the probe board is movable to be separated from or contact with the tested MOS type semiconductor device, the source/emitter electrode and the grid electrode of the tested MOS type semiconductor device are positioned on a first side surface of the tested MOS type semiconductor device, and a drain/collector electrode of the tested MOS type semiconductor device is positioned on a second side surface of the tested MOS type semiconductor device opposite to the first side surface.
In some embodiments, the drive plate is replaceable and fixedly connected to the probe card.
In some embodiments, the MOS-type semiconductor device under test is a MOSFET or an IGBT.
In some embodiments, the number of probes is a plurality of pairs, and the number of driving circuits and the threshold measurement circuits are each a plurality of and correspond to the pairs of probes one to one.
The distance between the driving circuit and the threshold measuring circuit and the tested chip is shorter, the total length of the loop is shorter, the parasitic inductance is smaller, and the accuracy of the test is improved. The parasitic inductance of the loop is reduced, so that the frequency of the signal waveform output by the driving circuit is properly increased, and the voltage overshoot is not caused. The higher the frequency of the signal waveform output by the driving circuit is, the more effectively the chip aging is promoted, so that the test time consumption of each chip is shortened, and the test efficiency is further improved.
Drawings
Fig. 1 is a partial structural view of a related art MOS type semiconductor device testing apparatus.
Fig. 2 is a partial structural view of a MOS type semiconductor device testing apparatus according to an embodiment of the present disclosure.
Fig. 3 is a circuit layout on a substrate of the device shown in fig. 2.
Fig. 4 is a specific circuit diagram of the switching control circuit of the apparatus shown in fig. 2.
Fig. 5 is an equivalent circuit diagram of the apparatus shown in fig. 2 when the MOS device under test is connected to a driving circuit.
Fig. 6 is an equivalent circuit diagram of the apparatus shown in fig. 2 when the MOS device under test is connected to a threshold value measurement circuit.
Fig. 7 is a partial block diagram of a MOS semiconductor device testing apparatus according to other embodiments of the present disclosure.
Fig. 8 is a partial block diagram of a MOS semiconductor device testing apparatus according to other embodiments of the present disclosure.
Fig. 9 is an equivalent circuit diagram of the apparatus shown in fig. 8 when the MOS device under test is connected to a driving circuit.
Fig. 10 is an equivalent circuit diagram of the apparatus shown in fig. 8 when the MOS device under test is connected to the threshold value measurement circuit.
Detailed Description
The disclosure is further described below with reference to the embodiments shown in the drawings.
In the related art, a test is generally performed on a MOS type semiconductor device using a probe station. Fig. 1 shows part of the constituent elements of a probe station: carrier and probe. Electrical signals of the gate and source/emitter of the MOS type semiconductor device under test (i.e., the chip labeled in the drawings) are applied from an external power source (not shown) to the gate and source/emitter of the chip through probe lines (not shown) and probes. An electrical signal of the drain/collector of the chip is applied to the drain/collector of the chip through the submount. The carrier may also apply thermal stress to the chip (i.e., heat the chip).
The probes and probe wires are generally relatively elongated, each typically having a diameter of several tens of micrometers to several millimeters, and each typically having a length of several centimeters to several hundred centimeters. The elongated probe wire has a large parasitic inductance, which may cause distortion of the voltage waveform actually loaded on the chip, such as occurrence of a large overshoot, resulting in a decrease in test accuracy.
When measuring the threshold voltage of a chip, for example, an N-type MOSFET, the source of the chip is usually kept grounded, and positive voltages are applied to the gate and drain simultaneously. In the case of multi-chip synchronous test, the device needs to sequentially detect the threshold voltages of the chips, and the test efficiency is low.
Based on the above analysis, the inventors of the present application proposed a MOS type semiconductor device testing apparatus.
Referring to fig. 2, the apparatus includes a stage, a substrate, and one or more pairs of probes. Other necessary structures for the power supply in the device etc. are not shown in fig. 2. The bottom of the test equipment is a carrying platform, and the diameter of the carrying platform is 150mm to 400mm.
The carrier serves as an electrical interface for the back electrode (i.e., drain/collector) of the chip and provides mechanical support and temperature stress. The chip to be tested is placed above the carrier and is fixed on the carrier.
When the chip is a MOSFET, the source/emitter is in particular the source and the drain/collector is in particular the drain. When the chip is an IGBT, the source/emitter is specifically an emitter, and the drain/collector is specifically a collector.
A substrate is disposed over the chip. The substrate includes an insulating base, and a driving circuit, a switching control circuit, and a threshold measurement circuit provided on the insulating base.
The lower ends of one or more pairs of metal probes are in electrical contact with the metal electrodes of the tested chip, and the metal probes are mutually and electrically insulated. The number of probe pairs is 1 to 5 pairs, but may be more. The metal probe length is typically 20mm to 50mm. The upper ends of the metal probes are fixed on the same insulating substrate, and can transmit electric signals from a driving circuit or a threshold measuring circuit on the insulating substrate.
The substrate may be controllably moved so that the probes contact or disengage the chip.
The vertical distance of the chip from the insulating substrate is typically 5mm to 50mm. The insulating substrate is a ceramic material or polymer and is typically 1mm to 3mm thick. A driving circuit capable of generating a gate driving voltage is arranged on the insulating substrate, and the gate driving voltage generated by the driving circuit is applied between a gate and a source/emitter of the chip to be tested through a probe. The reference level and power supply for the drive circuit is provided by a power supply.
A switching control circuit is disposed on the insulating substrate. The switching control circuit consists of a double-pole double-throw relay and an MOS tube.
The drive circuit is used to apply a drive voltage between the gate and source/emitter of the chip that can cause the chip to age (even if the threshold voltage of the chip shifts). The threshold measurement circuit is used for measuring the threshold voltage of the chip.
The present disclosure does not limit the structure of the driving circuit, and a driving waveform (e.g., a continuous square wave) that promotes chip burn-in can be applied between the gate and the source/emitter of the chip.
The drive loop starts from the output end of the drive circuit, goes through the output end of the drive circuit on the insulating substrate to the copper layer trace (length L1, as shown in FIG. 3) of the grid probe hole G (i.e. the hole through which the probe connecting the grid passes on the insulating substrate), the grid probe (length L2, as shown in FIG. 2), the chip to be tested and the source/emitter probe (length L3, as shown in FIG. 2), and finally goes back to the drive circuit through the copper layer trace (length L4, as shown in FIG. 3) of the source/emitter probe hole S/E on the insulating substrate (i.e. the hole through which the probe connecting the source/emitter passes on the insulating substrate). Total length L of drive circuit total Typically between 20mm and 200mm, L total Mainly consists of L1, L2, L3 and L4. Compared with the related technical scheme, the total length of the driving circuit is greatly shortened.
The switching control circuit switches the operating state of the test equipment by controlling the switch control signal as shown in fig. 4. The switch 1 is a double-pole double-throw switch, and when the control signal of the switch 1 is at a high level, the driving signal is connected into the probe holes S/E and G. When the control signal of the switch 1 is at a low level, the threshold measurement interface is connected with the probe holes S/E and G. The switch 2 is a single-pole double-throw switch, and when the control signal of the switch 2 is at a high level, the threshold measurement interface D/C is connected with the probe hole S/E. When the switch 2 control signal is at a low level, the threshold measurement interface S/E is connected to the probe hole G.
When gate stress is applied, the control signals of the switch 1 and the switch 2 are high level, the probe hole is connected with an output line of a driving circuit, and the driving circuit is connected with a gate and a source/emitter of the chip.
Referring to FIG. 5, the drain/collector and source/emitter shorts of the chip MOS, the gate drive voltage V GS Applied between the gate and the source/emitter. Gate drive voltage V GS Such as a continuous square wave signal.
When the threshold voltage measurement is required, the control signals of the switch 1 and the switch 2 are low level, and the probe holes G and S/E in the figure 3 are connected with a threshold measurement line. Referring to fig. 6, the chip drain/collector and gate are shorted and the carrier is grounded. The probe contacted with the source electrode of the tested chip is connected to the positive terminal of the testing power supply, and the negative terminal of the power supply is grounded or directly connected with the carrier. The test power supply is set in a current source mode, the current range is set between a preset threshold setting current and 0mA, the threshold setting current is negative current, the typical value is between-1 mA and-50 mA, and the voltage setting range is 0V to-10V.
The distance between the driving circuit and the threshold measuring circuit and the tested chip is shorter, the total length of the loop is shorter, the parasitic inductance is smaller, and the accuracy of the test is improved. Although one pair of probes is exemplarily shown in fig. 2, a plurality of pairs of probes may be provided on the substrate. The pairs of probes can be synchronously electrically connected with or disconnected from the chips along with the up-and-down movement of the substrate. Thereby further improving the efficiency of the test.
The parasitic inductance of the loop is reduced, so that the frequency of the signal waveform output by the driving circuit is properly increased, and the voltage overshoot is not caused. The higher the frequency of the signal waveform output by the driving circuit is, the more effectively the chip aging is promoted, so that the test time consumption of each chip is shortened, and the test efficiency is further improved.
Referring to fig. 7, further embodiments provide a test apparatus comprising: a stage, a board for probes, a driving board, and a power source (not shown). The bottom of the test equipment is a carrying platform, and the diameter of the carrying platform is 150mm to 400mm. The carrier serves as an electrical interface for the back electrode (drain/collector) of the chip and provides mechanical support and temperature stress. The chip to be tested is placed above the carrier and is fixed on the carrier. The probe board, the connecting wires and the driving board are arranged above the chip. The probes penetrate the probe card and are electrically connected to traces on the probe card. The lower ends of the metal probes are connected with the metal electrodes of the tested chip, and the metal probes are mutually and electrically insulated. The number of probes is 1 to 5 pairs, or more. The length of the metal probe is 20mm to 50mm. The upper ends of the metal probes are fixed to the same probe card for transmitting electric signals from the driving board. The vertical distance between the chip and the probe card is 5mm to 50mm. The probe card is made of ceramic or polymer and has a thickness of 1mm to 3mm. The probe card has an electric signal transmission function in addition to the function of fixing the probes, and the lower ends of the connecting wires and the upper ends of the probes are connected through copper layers or other modes. The length of the connection line is typically 1mm to 15mm and serves to pass the gate voltage signal. The upper end of the connecting wire is connected with a driving plate, and the size of the driving plate is consistent with that of the probe plate. The driving circuit on the driving board may generate the gate voltage signal. The gate voltage signal is applied to the chip under test through the connection lines, the probe card and the probes. The reference level and power supply for the drive circuit is provided by a power supply.
Similar to the previous embodiments, the switching control circuit is provided on the insulating substrate of the driving board. The switching control circuit consists of a double-pole double-throw relay and an MOS tube. The switching control circuit may be any circuit form capable of switching the circuit connection relationship. The functions of the driving plate of the invention include: providing a grid voltage signal and measuring the threshold voltage of the tested chip.
The total length of the drive circuit is typically 20-200 mm, and the drive circuit is increased by 4 distance connecting lines (L5, L8) and copper layer traces (L6, L7) on the probe card compared with the previous embodiment. The steps of gate stress application and threshold voltage measurement refer to the test device of the previous embodiment.
The substrate of the probe card is a first insulating substrate, and the substrate of the driving board is a second insulating substrate. And a switching control circuit is arranged on the second insulating substrate and consists of a double-pole double-throw relay and an MOS tube. The functions of the drive plate include: providing a gate voltage and measuring a threshold voltage of the chip under test. The power supply of the threshold measurement circuit may be provided outside the drive board.
The distance between the driving circuit and the threshold measuring circuit and the tested chip is shorter, the total length of the loop is shorter, the parasitic inductance is smaller, and the accuracy of the test is improved. Although one pair of probes is exemplarily shown in fig. 7, a plurality of pairs of probes may be provided on the substrate. The pairs of probes can be synchronously electrically connected with or disconnected from the chips along with the up-and-down movement of the substrate. Thereby further improving the efficiency of the test.
Because the drive plate is designed separately from the probe card, in some embodiments the drive plate is replaceable and fixedly attached to the probe card. This enables one probe card to be connected to a plurality of types of drive boards. In other embodiments, the probe card is replaceable and is fixedly coupled to the drive board. Thereby increasing the flexibility of use of the drive board or probe card.
The substrate illustrated in fig. 8 can be tested for 2 chips simultaneously. The chip peripheral circuits are shown in fig. 9 and 10.
Referring to fig. 9, 2 driving circuits (not shown) are provided on a substrate. The gate voltage outputted by a driving circuit is denoted as V GS1 The gate voltage outputted by the other driving circuit is denoted as V GS2 . Since the two drive circuits are independent of each other, the source/emitters of the two chips are not shorted together. The drain/collector electrodes D1/C1, D2/C2 of the chip MOS1 and the chip MOS2 are shorted together with the source/emitter electrodes S1/E1, S2/E2 respectively in the external wiring. The drain/collector electrodes D1/C1, D2/C2 of the two chips MOS1 and MOS2 are shorted in the carrier. The voltage stress V is applied between the gates G1, G2 and the source/emitter S1/E1, S2/E2 of the chips MOS1 and MOS2, respectively GS1 And V GS2 。
Referring to FIG. 10, the gates G1, G2 and the drain/collector electrodes D1/C1, D2/C2 of the chips MOS1 and MOS2 are shorted, and the drain/collector electrodes D1/C1, D2/C2 of the chips MOS1 and MOS2 are in the state ofThe carrier is short-circuited and grounded. Probes contacted with the source electrodes S1/E1 and S2/E2 of the tested chip are respectively connected to the respective and mutually independent test power supply V DC1 、V DC2 Positive terminal of (a), power supply V DC1 、V DC2 The negative terminal is grounded or directly connected to the carrier. Test power supply V DC1 、V DC2 A current source mode is set, the current range is set between a predetermined threshold setting current and 0mA, the threshold setting current is negative current, the typical value is between-1 mA and-50 mA, and the voltage setting range is 0V to-10V. Due to the power supply V of the test chips MOS1 and MOS2 DC1 And V DC2 In order to isolate the power supply, the source/emitter electrodes of the chips MOS1 and MOS2 are not shorted together, and parallel measurement of the threshold voltages of the chips MOS1 and MOS2 can be realized.
In other embodiments, the source/emitter of chips MOS1 and MOS2 are connected simultaneously by the positive terminal of one power supply when making the threshold measurement. A current detection circuit is added in the test equipment to respectively detect the current values of the chips.
It should be noted that, although the example of the drawings shows a test circuit of an N-type silicon carbide MOSFET, the test apparatus of the present disclosure is equally applicable to an N-channel IGBT, a P-type MOSFET, and a P-channel IGBT. And the type of semiconductor material is not limited to silicon carbide, but may be silicon, gallium nitride, or the like, for example.
The scope of the present disclosure is not limited to the above-described embodiments, and it is apparent that various modifications and variations can be made to the present disclosure by those skilled in the art without departing from the scope and spirit of the disclosure. Such modifications and variations are intended to be included herein within the scope of the following claims and their equivalents.
Claims (7)
1. A MOS semiconductor device testing apparatus, characterized by comprising:
the carrier is used for carrying the tested MOS type semiconductor device and is in conductive contact with the drain/collector of the tested MOS type semiconductor device;
a substrate including an insulating base, a driving circuit, a switching control circuit, and a threshold value measuring circuit provided on the insulating base;
and one or more pairs of probes are fixed on the insulating substrate and are electrically connected with the switching control circuit, the switching control circuit is used for controlling the on-off of any pair of probes with the driving circuit and the threshold value measuring circuit, wherein any pair of probes are used for respectively and conductively contacting a grid electrode and a source/emitter electrode of one MOS type semiconductor device to be tested, the substrate is movable to enable the probes to be separated from or contact the MOS type semiconductor device to be tested, the source/emitter electrode and the grid electrode of the MOS type semiconductor device to be tested are positioned on a first side surface of the MOS type semiconductor device to be tested, and a drain/collector electrode of the MOS type semiconductor device to be tested is positioned on a second side surface of the MOS type semiconductor device to be tested, which is opposite to the first side surface.
2. The apparatus of claim 1, wherein the MOS-type semiconductor device under test is a MOSFET or an IGBT.
3. The apparatus of claim 1, wherein the number of probes is a plurality of pairs, and the number of drive circuits and the threshold measurement circuits are each a plurality of and are in one-to-one correspondence with a pair of probes.
4. A MOS semiconductor device testing apparatus, characterized by comprising:
the carrier is used for carrying the tested MOS type semiconductor device and is in conductive contact with the drain/collector of the tested MOS type semiconductor device;
the probe board comprises a first insulating substrate and a wire arranged on the first insulating substrate;
a driving board including a second insulating substrate, a driving circuit disposed on the second insulating substrate, a switching control circuit, and a threshold measurement circuit;
a plurality of connection lines connecting the probe card and the drive board;
the pair or the pairs of probes are fixed on the first insulating substrate and are electrically connected with the switching control circuit through the lead and the connecting wire, and the switching control circuit is used for controlling the on-off of any pair of probes and the driving circuit and the threshold measuring circuit;
wherein any pair of probes is used for respectively conducting and contacting a grid electrode and a source/emitter electrode of a tested MOS type semiconductor device, and the probe board is movable to enable the probes to be separated from or contact with the tested MOS type semiconductor device, the source/emitter electrode and the grid electrode of the tested MOS type semiconductor device are positioned on a first side surface of the tested MOS type semiconductor device, and a drain/collector electrode of the tested MOS type semiconductor device is positioned on a second side surface of the tested MOS type semiconductor device opposite to the first side surface.
5. The apparatus of claim 4, wherein the drive plate is replaceable and fixedly connected to the probe card.
6. The apparatus of claim 4, wherein the MOS-type semiconductor device under test is a MOSFET or an IGBT.
7. The apparatus of claim 4, wherein the number of probes is a plurality of pairs, and the number of drive circuits and the threshold measurement circuits are each a plurality of and are in one-to-one correspondence with pairs of probes.
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| CN202310225572.9A CN116520114A (en) | 2023-03-09 | 2023-03-09 | MOS type semiconductor device testing equipment |
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