CN116506096A - Clock synchronization method, system, component and equipment - Google Patents

Clock synchronization method, system, component and equipment Download PDF

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Publication number
CN116506096A
CN116506096A CN202310752783.8A CN202310752783A CN116506096A CN 116506096 A CN116506096 A CN 116506096A CN 202310752783 A CN202310752783 A CN 202310752783A CN 116506096 A CN116506096 A CN 116506096A
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China
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message
slave
module
clock
master
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CN202310752783.8A
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CN116506096B (en
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董云星
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Beijing Xiangdixian Computing Technology Co Ltd
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Beijing Xiangdixian Computing Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure provides a clock synchronization method, system, component, and apparatus. The clock synchronization method applied to the slave module comprises the steps of responding to the received first message sent by the master module, sending a second message to the master module and starting timing; stopping timing in response to receiving a third message sent by the main module; the third message is sent by the main module at intervals of a first preset time period after the second message is received; dividing the difference between the current timing time length and the first preset time length by 2 to obtain transmission delay between the master module and the slave module; and according to the transmission delay, clock synchronization is carried out on the master module and the slave module. And obtaining the transmission delay between the master module and the slave module in a timing mode, so that clock correction between the master module and the slave module can be performed.

Description

Clock synchronization method, system, component and equipment
Technical Field
The disclosure relates to the technical field of buses, and in particular relates to a clock synchronization method, a clock synchronization system, a clock synchronization component and clock synchronization equipment.
Background
The interconnection protocols of the System On Chip (SOC) internal bus include advanced extensible interface (Advanced eXtensible Interface, AXI) protocol, I2C (Inter Integrated Circuit) bus, I3C (Improved Inter Integrated Circuit), and the like. The master module chip (master die) and each slave module chip (slave die) are connected through a bus. The use of chip (chip) technology in SOC technology is becoming more and more common today, but clocks between the chiplets (master and individual slaves) tend to be unsynchronized, and there is a need for clock synchronization between the chiplets in addition to data communication.
Disclosure of Invention
The invention aims to provide a clock synchronization method, a clock synchronization system, a clock synchronization assembly and clock synchronization equipment, which solve the technical problem that clocks of a master module and each slave module are not synchronous in the prior art.
According to one aspect of the present disclosure, there is provided a clock synchronization method applied to a slave module of a bus system, including:
in response to receiving the first message sent by the main module, sending a second message to the main module and starting timing;
stopping timing in response to receiving a third message sent by the main module; the third message is sent by the main module at intervals of a first preset time period after the second message is received;
dividing the difference value between the current timing time length and the first preset time length by 2 to obtain transmission delay between the master module and the slave module;
and according to the transmission delay, clock synchronization is carried out on the master module and the slave module.
In some embodiments, in the clock synchronization method, clock synchronization is performed on the master module and the slave module according to the transmission delay, including:
according to the transmission delay, a corresponding fourth message is sent to the main module; wherein the fourth message carries a transmission delay;
receiving a fifth message sent by the main module; the fifth message is generated by the main module according to the transmission delay after receiving the fourth message, and the fifth message carries a second preset duration, wherein the sum of the second preset duration and the transmission delay is equal to a specified value;
After receiving the fifth message sent by the master module, the slave clock of the slave module is restarted at intervals of a second preset duration;
wherein the slave clock and the master clock of the master module are restarted simultaneously.
In some embodiments, in the clock synchronization method, the bus system includes at least two slave modules, and each slave module restarts the corresponding slave clock according to the method, so that the slave clocks of each slave module are restarted at the same time.
In some embodiments, in the clock synchronization method, the bus system includes at least two slave modules, the assigned values corresponding to the slave modules are the same, and the fifth message corresponding to the slave modules is sent by the master module at the same time.
In some embodiments, in the clock synchronization method, before sending the corresponding fourth message to the master module according to the transmission delay, the method further includes:
sending a first interrupt message to the main module to trigger the main module to return a sixth message;
and sending a corresponding fourth message to the main module according to the transmission delay, wherein the fourth message comprises:
and in response to receiving the sixth message, sending a corresponding fourth message to the main module according to the transmission delay.
In some embodiments, in the clock synchronization method, the method further includes:
In response to receiving the seventh message sent by the main module, sending an eighth message to the main module; the eighth message carries the time value of the slave clock when the slave module receives the seventh message, and is used for determining whether the master clock and the slave clock are synchronous or not according to the time value of the master clock when the master module sends the seventh message, the time value of the slave clock when the slave module receives the seventh message and the transmission delay; or the eighth message carries the time value of the slave clock when the slave module sends the eighth message, and is used for determining whether the master clock and the slave clock are synchronous or not according to the time value of the master clock when the master module receives the eighth message, the time value of the slave clock when the slave module sends the eighth message and the transmission delay.
In some embodiments, in the clock synchronization method, before the receiving the seventh message sent by the master module and before sending the eighth message to the master module, the method further includes:
and in response to receiving the ninth message sent by the main module, sending a second interrupt message to the main module so as to trigger the main module to return the seventh message.
In some embodiments, in the clock synchronization method, the bus system includes at least two slave modules, and a time interval between any two slave modules sending the second interrupt message is greater than a third preset duration.
In some embodiments, in the clock synchronization method, the method further includes:
receiving a tenth message sent by the master module, and confirming the time value of the slave clock when the slave module receives the tenth message; the tenth message carries the time value of the master clock when the master module sends the tenth message;
and according to the time value of the slave clock when the slave module receives the tenth message, the time value of the master clock when the master module sends out the tenth message and the transmission delay, confirming whether the master clock and the slave clock are synchronous.
According to another aspect of the present disclosure, there is provided a clock synchronization method applied to a master module of a bus system, including:
sending a first message to the slave module to trigger the slave module to start timing and return a second message;
and after receiving the second message, sending a third message to the slave module at intervals of a first preset time length to trigger the slave module to stop timing, so that the slave module divides the difference between the current timing time length and the first preset time length by 2 to obtain the transmission delay between the master module and the slave module, and further clock synchronization is carried out on the master module and the slave module according to the transmission delay.
In some embodiments, in the clock synchronization method, the method further includes:
Receiving a fourth message sent by the slave module, wherein the fourth message is generated by the slave module according to the transmission delay, and the fourth message carries the transmission delay;
generating a fifth message according to the transmission delay carried by the fourth message; the fifth message carries a second preset time length, and the sum of the second preset time length and the transmission delay is equal to a specified value;
sending a fifth message to the slave module, so that the slave module restarts the slave clock of the slave module at intervals of a second preset duration after receiving the fifth message sent by the master module;
wherein the slave clock and the master clock of the master module are restarted simultaneously.
In some embodiments, in the clock synchronization method, the bus system includes at least two slave modules, and the master module enables each slave module to restart the corresponding slave clock according to the method, so that the slave clocks of each slave module are restarted at the same time.
In some embodiments, in the clock synchronization method, the bus system includes at least two slave modules, where the assigned values corresponding to the slave modules are the same;
the fifth message corresponding to each slave module is sent out by the master module at the same time.
In some embodiments, in the clock synchronization method, before receiving the fourth message sent by the slave module, the method further includes:
And in response to receiving the first interrupt message sent by the slave module, sending a sixth message to the slave module to trigger the slave module to return a fourth message.
In some embodiments, in the clock synchronization method, the method further includes:
sending a seventh message to the slave module to trigger the slave module to return an eighth message; the eighth message carries the time value of the slave clock when the slave module receives the seventh message; according to the time value of the master clock when the master module sends the seventh message, the time value of the slave clock when the slave module receives the seventh message and the transmission delay, whether the master clock and the slave clock are synchronous or not is confirmed; or alternatively, the first and second heat exchangers may be,
sending a seventh message to the slave module to trigger the slave module to return an eighth message; wherein the eighth message carries the time value of the slave clock when the slave module sends the eighth message; and according to the time value of the master clock when the master module receives the eighth message, the time value of the slave clock when the slave module sends the eighth message and the transmission delay, determining whether the master clock and the slave clock are synchronous.
In some embodiments, in the clock synchronization method, before sending the seventh message to the slave module, the method further includes:
sending a ninth message to the slave module to trigger the slave module to return a second interrupt message;
Transmitting a seventh message to the slave module, comprising:
and transmitting a seventh message to the slave module in response to receiving the second interrupt message transmitted by the slave module.
In some embodiments, in the clock synchronization method, the bus system includes at least two slave modules, and a time interval between any two slave modules sending the second interrupt message is greater than a third preset duration.
In some embodiments, in the clock synchronization method, the method further includes:
transmitting a tenth message to the slave module to trigger the slave module to acknowledge the time value of the slave clock when the slave module receives the tenth message; the tenth message carries the time value of the master clock when the master module sends the tenth message, so that the slave module confirms whether the master clock and the slave clock are synchronous according to the time value of the slave clock when the slave module receives the tenth message, the time value of the master clock when the master module sends the tenth message and the transmission delay.
According to another aspect of the present disclosure, there is provided a bus system comprising:
a bus;
a slave module configured to implement the clock synchronization method applied to the slave module according to any one of the above embodiments;
the master module is configured to implement the clock synchronization method applied to the master module according to any one of the above embodiments.
According to another aspect of the present disclosure, an electronic assembly is provided comprising a bus system according to any of the embodiments described above.
According to another aspect of the present disclosure, there is provided an electronic device including the electronic assembly according to any one of the above embodiments.
Drawings
FIG. 1 is a flow chart of a clock synchronization method (applied to a slave module) according to an embodiment of the present disclosure;
FIG. 2 is a timing diagram of a clock synchronization method according to one embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a connection structure of a bus system according to an embodiment of the present disclosure;
FIG. 4 is a timing diagram of another clock synchronization method provided by one embodiment of the present disclosure;
FIG. 5 is a timing diagram of another clock synchronization method provided by one embodiment of the present disclosure;
FIG. 6 is a timing diagram of another clock synchronization method provided by one embodiment of the present disclosure;
FIG. 7 is a timing diagram of another clock synchronization method provided by one embodiment of the present disclosure;
fig. 8 is a flowchart of a clock synchronization method (applied to a master module) according to an embodiment of the disclosure.
Detailed Description
Before describing embodiments of the present disclosure, it should be noted that:
Some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.
The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.
The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.
It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.
In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.
The invention aims to provide a clock synchronization method, a system, a component and equipment, wherein the clock synchronization method applied to a slave module comprises the steps of responding to receiving a first message sent by a master module, sending a second message to the master module and starting timing; stopping timing in response to receiving a third message sent by the main module; the third message is sent by the main module at intervals of a first preset time period after the second message is received; dividing the difference value between the current timing time length and the first preset time length by 2 to obtain transmission delay between the master module and the slave module; and according to the transmission delay, clock synchronization is carried out on the master module and the slave module.
In the clock synchronization scheme, the transmission delay between the master module and the slave module is obtained in a timing mode, so that clock correction between the master module and the slave module can be performed, and clock synchronization between the master module and the slave module is realized.
One embodiment of the present disclosure provides a clock synchronization method applied to a slave module of a bus system, as shown in fig. 1, including:
step S110: in response to receiving the first message sent by the main module, sending a second message to the main module and starting timing;
Step S120: stopping timing in response to receiving a third message sent by the main module; the third message is sent by the main module at intervals of a first preset time period after the second message is received;
step S130: dividing the difference value between the current timing time length and the first preset time length by 2 to obtain transmission delay between the master module and the slave module;
step S140: and according to the transmission delay, clock synchronization is carried out on the master module and the slave module.
In the bus system, information transmission is realized between the master module and the slave module through a bus, and the bus can be an AXI bus, an I2C bus or an I3C bus and the like.
The principle of transmission delay test is shown in fig. 2, it can be understood that in the timing chart, T is the time value of the master clock of the master module, T 'is the time value of the slave clock of the slave module, td is the transmission delay between the master module and the slave module, as shown in fig. 2, the master module sends out a first message at the time T0 of the master clock, the slave module sends out a second message at the time T'0 of the slave clock after receiving the first message, and starts to count, the master module receives the second message at the time T1 of the master clock, which is spaced by a first preset time period Δt 1 I.e. at (T1+. DELTA.T of the master clock 1 ) The slave module stops timing after receiving the third message from the time T '1 of the clock, and the time length (T ' 1-T ' 0) is equal to (2 x Td+ [ delta ] T 1 ). Therefore, the slave module compares the current timing duration (T '1-T' 0) with the first preset duration DeltaT 1 Dividing the difference by 2 to obtain the transmission delay Td between the master and slave.
In some embodiments, the first predetermined time period Δt 1 The size of (2) is not limited and may be any value.
In some embodiments, the master module may compare the first predetermined time period ΔT 1 The third message may be carried in the third message and sent to the slave module, or may be carried in other information and sent to the slave module, which is not limited herein.
In some embodiments, the second message is of the ACK message type, so that when the master module receives the second message, the master module has enough time to analyze whether the second message is an ACK message or a NACK message, and after confirming that the second message is an ACK message, the third message is sent out, so that it is preferable that the first predetermined time period Δt 1 Greater than the time required for the master module to analyze the second message. In some embodiments, the first predetermined time period Δt 1 May be 30 time units (clock plus 1, 1 time unit).
In some embodiments, the main module analyzes whether the second message is an ACK message or a NACK message in a manner that the second message carries a corresponding valid identifier, 1 indicates that the second message is an ACK message, 0 indicates that the second message is a NACK message, a correspondence between the valid identifier and the ACK message and the NACK message is recorded in the memory, and when the main module receives the second message, the software program of the main module searches the register for the corresponding information according to the valid identifier carried by the second message, so as to determine whether the second message is an ACK message or a NACK message.
The timing function of the slave module is realized by the slave clock, namely the slave clock is also a timer.
In some embodiments, when performing clock correction, the master module may send a correction message to the slave module (which carries the time value Tr of the master clock when it sent the correction message), and when receiving the correction message, the slave module records the time value T' r of the slave clock when it received the correction message, since the two time values have the following relationship with the transmission delay Td and the clock offset (clock offset between the master clock and the slave clock): t' r=tr+td+offset, so the slave module can calculate the clock offset, so that clock correction between the master module and the slave module can be achieved, and clock synchronization between the master module and the slave module can be achieved.
In other embodiments, the slave module may send a correction message to the master module (carrying the time value T' r of the slave clock and the transmission delay Td when it sent the correction message) when it receives the correction message, and the master module records the time value Tr of the master clock when it receives the correction message, because of the following relationship between the two time values and the transmission delay Td and the clock offset (clock offset between the master clock and the slave clock): tr=t' r+td-offset, so the master module can calculate the clock offset, so that clock correction between the master module and the slave module can be implemented, and clock synchronization between the master module and the slave module can be implemented.
In other embodiments, the clock offset may not need to be calculated when performing clock correction, and the step S140 specifically includes:
step S142: according to the transmission delay, a corresponding fourth message is sent to the main module; wherein the fourth message carries a transmission delay;
step S144: receiving a fifth message sent by the main module; the fifth message is generated by the main module according to the transmission delay after receiving the fourth message, and the fifth message carries a second preset duration, wherein the sum of the second preset duration and the transmission delay is equal to a specified value;
step S146: after receiving the fifth message sent by the master module, the slave clock of the slave module is restarted at intervals of a second preset duration;
wherein the slave clock and the master clock of the master module are restarted simultaneously.
Wherein, restart refers to the clock starting from 0.
It will be appreciated that the slave clock and the master clock are restarted at the same time, and that the clock offset between the slave clock and the master clock is equal to 0, i.e. the clock correction and clock synchronization is achieved upon restart. In the clock synchronization scheme, clock synchronization can be realized without obtaining clock deviation, and time required by clock synchronization can be shortened.
The mode of restarting the master clock and the slave clock simultaneously is as follows: when the master module sends out the fifth message, the master module can determine that the slave clock is restarted at a time interval of a designated value (sum of the second preset duration and the transmission delay) after the master module sends out the fifth message, so that the master module can control the master clock to restart at the time interval of the designated value after the master module sends out the fifth message, and the simultaneous restart of the slave clock and the master clock is realized.
In some embodiments, the fourth message further carries a restart instruction, so that the slave module restarts the slave clock of the slave module at intervals of a second preset duration after receiving the fifth message sent by the master module.
In some embodiments, the bus system includes at least two slave modules. In such a bus system, in order to achieve clock synchronization of the master and slave, the slave clocks of the respective slave modules need to be restarted at the same time. The method for restarting the slave clocks of the slave modules is the same as the method described above, and will not be repeated here.
As shown in fig. 3, the bus system includes 3 slave modules, slave module 0, slave module 1, and slave module 2, respectively.
In some embodiments, in order to implement simultaneous restart of the slave clocks of the slave modules, the assigned values corresponding to the slave modules are the same, and the fifth message corresponding to the slave modules is sent by the master module at the same time, so that the slave clocks of the slave modules are all restarted at the same time after the master module sends the fifth message by the assigned value (sum of the second preset duration and the transmission delay).
It will be understood that, as shown in fig. 2, the master clock has a time value T3 when the master module issues the fifth message, and the specified value is equal to the transmission delay Td plus the second preset time period Δt 2 When clock synchronization is performed, it may be set that when the master module receives the fourth messages sent by all the slave modules, that is, after the transmission delay Td corresponding to each slave module is obtained, the specified value is set according to the transmission delay Td corresponding to each slave module (the specified value needs to be greater than or equal to the transmission delay Td corresponding to each slave module, preferably greater than the transmission delay Td corresponding to each slave module), and then, at the selected sending time T3, the master module sends corresponding fifth messages to each slave module at the same time.
For example, as shown in fig. 3, the transmission delay corresponding to the slave module 0 is 5 time units, the transmission delay corresponding to the slave module 1 is 6 time units, and the transmission delay corresponding to the slave module 2 is 8 time units, then the master module may set the designated value to be 10 time units, that is, restart the slave clock for 5 time units (second preset duration) after the slave module 0 receives the fifth message, restart the slave clock for 4 time units (second preset duration) after the slave module 1 receives the fifth message, and restart the slave clock for 2 time units (second preset duration) after the slave module 2 receives the fifth message, so as to realize that the real start time (restart time) of the slave clocks of all the slave modules is consistent (that is, the same time starts to count from 0).
In some embodiments, as shown in fig. 4, before step S142, the method further includes:
and sending a first interrupt message to the main module to trigger the main module to return a sixth message.
Correspondingly, step S142 includes:
and in response to receiving the sixth message, sending a corresponding fourth message to the main module according to the transmission delay.
It will be appreciated that, after the slave obtains the transmission delay, if the fourth message carrying the transmission delay is directly sent to the master module, at this time, it is possible that the master module is not ready for the receiver to transmit the delay, so it is preferable that, after the slave obtains the transmission delay, the master module is notified by means of an interrupt, which indicates that the slave module has obtained the transmission delay, and if the master module is ready to receive the transmission delay, a sixth message may be sent to the slave module to read the transmission delay obtained by the slave module, where the sixth message corresponds to a read message.
In some embodiments, the slave module may be configured to be spaced apart by a period Δt after receipt of the third message 3 (greater than the time required by the slave to calculate the propagation delay), and then sends a first interrupt message to the master to reserve sufficient time for the slave to calculate the propagation delay. Illustratively, this period of time at intervals may be 30 time units.
In some embodiments, after the clocks are synchronized, the master module and the slave module are disturbed by the outside, and clock deviation occurs again after a period of time, so in order to enable the master module to timely confirm whether the clocks of the master module and the slave module are synchronized, the master module may send a seventh message to the slave module when it is required to confirm whether the clocks are synchronized, so as to read back the time value of the slave clock, thereby confirming whether the time value of the slave clock has an error, and if the time value of the slave clock has an error, indicating that the clock deviation exists. Specifically, the step of confirming whether the clocks are synchronized includes:
in response to receiving the seventh message sent by the main module, sending an eighth message to the main module; the eighth message carries the time value of the slave clock when the slave module receives the seventh message, and is used for determining whether the master clock and the slave clock are synchronous or not according to the time value of the master clock when the master module sends the seventh message, the time value of the slave clock when the slave module receives the seventh message and the transmission delay; or the eighth message carries the time value of the slave clock when the slave module sends the eighth message, and is used for determining whether the master clock and the slave clock are synchronous or not according to the time value of the master clock when the master module receives the eighth message, the time value of the slave clock when the slave module sends the eighth message and the transmission delay.
It can be understood that, as shown in fig. 5, the first clock synchronization confirmation scheme is: when the master module sends out the seventh message, the master module can record the time value T5 of the master clock when the master module sends out the seventh message, the slave module can record the time value T '5 of the slave clock when the slave module receives the seventh message, then the time value T '5 of the slave clock when the slave module receives the seventh message is returned to the master module through the eighth message, when the master module receives the eighth message, the master module confirms whether T '5 is equal to (T5+Td), if so, the master clock and the slave clock are synchronous, otherwise, the master clock and the slave clock are not synchronous (namely, clock deviation exists).
When the slave module has clock deviation, the clock synchronization can be performed again according to the steps S110 to S140, or the clock deviation of the master clock and the slave clock can be obtained according to the difference between T'5 and (t5+td) for the slave module with error, and then the master module can send a broadcast command through the bus to instruct the corresponding slave module to perform clock correction, and the slave module adjusts the slave clock to be consistent with the master clock according to the clock deviation.
The second clock synchronization confirmation scheme is as follows: the master module sends out a seventh message, triggers the slave module to return an eighth message (wherein the seventh message carries a time value T '6 of a slave clock when the slave module sends out the eighth message), records a time value T6 of the master clock when the master module receives the eighth message, confirms whether T6 is equal to (T' 6+Td) or not when the master module receives the eighth message, if so, the master clock and the slave clock are synchronous, and otherwise, the master clock and the slave clock are not synchronous (namely, clock deviation exists).
Similar to the first clock synchronization confirmation scheme, when the slave module has clock deviation, the clock synchronization may be performed again according to the steps S110 to S140, or the clock deviation between the master clock and the slave clock may be obtained according to the difference between T6 and (T' 6+td) for the slave module having error, and then the master module may send a broadcast command through the bus to instruct the corresponding slave module to perform clock correction, where the slave module adjusts the slave clock to be consistent with the master clock according to the clock deviation.
In some embodiments, in response to receiving the seventh message sent by the master module, before sending the eighth message to the master module, further comprising:
and in response to receiving the ninth message sent by the main module, sending a second interrupt message to the main module so as to trigger the main module to return the seventh message.
It will be appreciated that when the master needs to read back the time value of the slave clock to confirm whether there is an error (clock deviation) in the time value of the slave clock, if the master directly transmits the seventh message to the slave, but it is possible that the slave is not ready to be read and returns the corresponding time value at this time, so it is preferable that the master firstly transmits the ninth message to the slave to inform the slave that the master will read data, the slave is ready to notify the master by means of an interrupt (second interrupt message), and the master transmits the seventh message after receiving the seventh message, as shown in fig. 6.
In some embodiments, in a scenario in which the bus system includes at least two slave modules, the time interval between any two slave modules transmitting the second interrupt message is greater than a third preset duration.
It can be understood that the master module may send the ninth message to each slave module at the same time to confirm whether the time value of the slave clock of each slave module has an error, and the time interval between any two slave modules sending the second interrupt message is set to be longer than the third preset duration, so that the master module can be prevented from receiving the second interrupt messages sent by the two slave modules at the same time, and information is not read, so that the master module can receive at most one second interrupt message at a time.
The third preset duration needs to be greater than the transmission delay corresponding to each slave module.
In some embodiments, the third preset duration may be 100 time units.
For example, in the bus system shown in fig. 3, the slave module 0 may send the second interrupt message to the master module 100 time units after receiving the ninth message, then the master module sends the seventh message to read back the time value of the slave clock of the slave module 0 to confirm whether synchronization is performed, and similarly, the slave module 1 sends the second interrupt message to the master module 200 time units after receiving the ninth message, then the master module sends the seventh message to read back the time value of the slave clock of the slave module 1, and the slave module 2 sends the second interrupt message to the master module 300 time units after receiving the ninth message, and then the master module sends the seventh message to read back the time value of the slave clock of the slave module 2.
In some embodiments, a third clock synchronization acknowledgement scheme is also provided as: the master module directly transmits the time value of the master clock to the slave module, and the slave module judges whether the master clock and the slave clock are synchronous or not. Specifically, the step of confirming whether the clocks are synchronized includes:
receiving a tenth message sent by the master module, and confirming the time value of the slave clock when the slave module receives the tenth message; the tenth message carries the time value of the master clock when the master module sends the tenth message;
and according to the time value of the slave clock when the slave module receives the tenth message, the time value of the master clock when the master module sends out the tenth message and the transmission delay, confirming whether the master clock and the slave clock are synchronous.
It will be understood that, as shown in fig. 7, when the master module sends out the tenth message, the tenth message carries the time value T7 of the master clock when the master module sends out the tenth message, and the slave module can record the time value T '7 of the slave clock when it receives the tenth message, and then confirm whether T '7 is equal to (t7+td), if so, it indicates that the master clock and the slave clock are synchronous, otherwise, it indicates that the master clock and the slave clock are not synchronous (i.e. there is a clock deviation, and the clock deviation is equal to | (t7+td) -T ' 7|).
When the slave module has an error (clock deviation), the error (clock deviation) information can be returned to the master module by means of an interrupt message, then clock synchronization can be performed again according to the steps S110 to S140, or the master module can send a broadcast command to the slave module with the error through the bus to instruct the corresponding slave module to perform clock correction, and the slave module adjusts the slave clock to be consistent with the master clock according to the clock deviation.
Based on the same inventive concept, the embodiments of the present disclosure further provide a clock synchronization method applied to a main module of a bus system, as shown in fig. 8, including:
step S210: sending a first message to the slave module to trigger the slave module to start timing and return a second message;
step S220: and after receiving the second message, sending a third message to the slave module at intervals of a first preset time length to trigger the slave module to stop timing, so that the slave module divides the difference between the current timing time length and the first preset time length by 2 to obtain the transmission delay between the master module and the slave module, and further clock synchronization is carried out on the master module and the slave module according to the transmission delay.
In some embodiments, after step S220, the method further includes:
Step S230: receiving a fourth message sent by the slave module, wherein the fourth message is generated by the slave module according to the transmission delay, and the fourth message carries the transmission delay;
step S240: generating a fifth message according to the transmission delay carried by the fourth message; the fifth message carries a second preset time length, and the sum of the second preset time length and the transmission delay is equal to a specified value;
step S250: sending a fifth message to the slave module, so that the slave module restarts the slave clock of the slave module at intervals of a second preset duration after receiving the fifth message sent by the master module;
wherein the slave clock and the master clock are restarted simultaneously.
In some embodiments, the bus system includes at least two slave modules, and the master module causes each slave module to restart its corresponding slave clock according to the method described above, so that the slave clocks of each slave module are restarted simultaneously.
In some embodiments, in the clock synchronization method, the bus system includes at least two slave modules, where the assigned values corresponding to the slave modules are the same;
the fifth message corresponding to each slave module is sent out by the master module at the same time.
In some embodiments, in the clock synchronization method, before receiving the fourth message sent by the slave module, the method further includes:
And in response to receiving the first interrupt message sent by the slave module, sending a sixth message to the slave module to trigger the slave module to return a fourth message.
In some embodiments, in the clock synchronization method, the method further includes:
sending a seventh message to the slave module to trigger the slave module to return an eighth message; the eighth message carries the time value of the slave clock when the slave module receives the seventh message; according to the time value of the master clock when the master module sends the seventh message, the time value of the slave clock when the slave module receives the seventh message and the transmission delay, whether the master clock and the slave clock are synchronous or not is confirmed; or alternatively, the first and second heat exchangers may be,
sending a seventh message to the slave module to trigger the slave module to return an eighth message; wherein the eighth message carries the time value of the slave clock when the slave module sends the eighth message; and according to the time value of the master clock when the master module receives the eighth message, the time value of the slave clock when the slave module sends the eighth message and the transmission delay, determining whether the master clock and the slave clock are synchronous.
In some embodiments, in the clock synchronization method, before sending the seventh message to the slave module, the method further includes:
sending a ninth message to the slave module to trigger the slave module to return a second interrupt message;
Transmitting a seventh message to the slave module, comprising:
and transmitting a seventh message to the slave module in response to receiving the second interrupt message transmitted by the slave module.
In some embodiments, in the clock synchronization method, the bus system includes at least two slave modules, and a time interval between any two slave modules sending the second interrupt message is greater than a third preset duration.
In some embodiments, in the clock synchronization method, the method further includes:
transmitting a tenth message to the slave module to trigger the slave module to acknowledge the time value of the slave clock when the slave module receives the tenth message; the tenth message carries the time value of the master clock when the master module sends the tenth message, so that the slave module confirms whether the master clock and the slave clock are synchronous according to the time value of the slave clock when the slave module receives the tenth message, the time value of the master clock when the master module sends the tenth message and the transmission delay.
The specific implementation process of the clock synchronization method applied to the master module may refer to the clock synchronization method applied to the slave module described in any of the above embodiments, which is not described herein again.
Based on the same inventive concept, the embodiments of the present disclosure also provide a bus system, as shown in fig. 3, including a bus, a slave module, and a master module.
A slave module configured to implement the clock synchronization method applied to the slave module according to any one of the above embodiments;
the master module is configured to implement the clock synchronization method applied to the master module according to any one of the above embodiments.
The bus System is a processing chip or a System-on-a-chip (SOC) chip that needs to implement read-write operations through a bus.
Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic assembly comprising the bus system according to any of the embodiments described above.
In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.
Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic device including the above-described electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (21)

1. A clock synchronization method applied to a slave module of a bus system, comprising:
in response to receiving a first message sent by a main module, sending a second message to the main module and starting timing;
stopping timing in response to receiving a third message sent by the main module; the third message is sent by the main module at intervals of a first preset time period after the second message is received;
dividing the difference between the current timing time length and the first preset time length by 2 to obtain transmission delay between the master module and the slave module;
and according to the transmission delay, clock synchronization is carried out on the master module and the slave module.
2. The method of claim 1, clock synchronizing the master module with the slave module according to the propagation delay, comprising:
according to the transmission delay, a corresponding fourth message is sent to the main module; wherein the fourth message carries the transmission delay;
Receiving a fifth message sent by the main module; the fifth message is generated by the master module according to the transmission delay after receiving the fourth message, and the fifth message carries a second preset duration, wherein the sum of the second preset duration and the transmission delay is equal to a specified value;
after receiving the fifth message sent by the master module, spacing the second preset duration time, and restarting the slave clock of the slave module;
wherein the slave clock and the master clock of the master module are restarted simultaneously.
3. A method according to claim 2, the bus system comprising at least two slave modules, each slave module restarting a corresponding slave clock according to the method of claim 2, such that the slave clocks of each slave module are restarted simultaneously.
4. The method of claim 2, the bus system comprising at least two slave modules, the designated value for each slave module being the same, and the fifth message for each slave module being issued simultaneously by the master module.
5. The method of claim 2, further comprising, prior to sending a corresponding fourth message to the master module in accordance with the propagation delay:
Sending a first interrupt message to the main module to trigger the main module to return a sixth message;
and sending a corresponding fourth message to the main module according to the transmission delay, wherein the fourth message comprises:
and responding to the receiving of the sixth message, and sending a corresponding fourth message to the main module according to the transmission delay.
6. The method of claim 1, the method further comprising:
in response to receiving the seventh message sent by the main module, sending an eighth message to the main module; the eighth message carries a time value of a slave clock when the slave module receives the seventh message, and is used for determining whether the master clock and the slave clock are synchronous according to the time value of the master clock when the master module sends the seventh message, the time value of the slave clock when the slave module receives the seventh message and the transmission delay; or the eighth message carries the time value of the slave clock when the slave module sends the eighth message, and is used for determining whether the master clock and the slave clock are synchronous according to the time value of the master clock when the master module receives the eighth message, the time value of the slave clock when the slave module sends the eighth message and the transmission delay.
7. The method of claim 6, further comprising, in response to receiving a seventh message sent by the master module, before sending an eighth message to the master module:
and in response to receiving the ninth message sent by the main module, sending a second interrupt message to the main module so as to trigger the main module to return the seventh message.
8. The method of claim 7, wherein the bus system comprises at least two slave modules, and wherein any two slave modules transmit the second interrupt message for a time interval greater than a third predetermined period of time.
9. The method of claim 1, the method further comprising:
receiving a tenth message sent by the master module, and confirming a time value of a slave clock when the slave module receives the tenth message; the tenth message carries the time value of the master clock when the master module sends the tenth message;
and according to the time value of the slave clock when the slave module receives the tenth message, the time value of the master clock when the master module sends out the tenth message and the transmission delay, confirming whether the master clock and the slave clock are synchronous.
10. A clock synchronization method applied to a main module of a bus system, comprising:
Sending a first message to a slave module to trigger the slave module to start timing and return a second message;
and after the second message is received, a third message is sent to the slave module at intervals of a first preset time length, so that the slave module stops timing, the difference between the current timing time length and the first preset time length is divided by 2 by the slave module, the transmission delay between the master module and the slave module is obtained, and the clock synchronization is carried out on the master module and the slave module according to the transmission delay.
11. The method of claim 10, the method further comprising:
receiving a fourth message sent by the slave module, wherein the fourth message is generated by the slave module according to the transmission delay, and carries the transmission delay;
generating a fifth message according to the transmission delay carried by the fourth message; the fifth message carries a second preset duration, and the sum of the second preset duration and the transmission delay is equal to a specified value;
sending the fifth message to the slave module, so that the slave module restarts the slave clock of the slave module at intervals of the second preset duration after receiving the fifth message sent by the master module;
Wherein the slave clock and the master clock of the master module are restarted simultaneously.
12. A method according to claim 11, the bus system comprising at least two slave modules, the master module causing each slave module to restart its corresponding slave clock in accordance with the method of claim 11, such that the slave clocks of each slave module are restarted simultaneously.
13. The method of claim 11, the bus system comprising at least two slave modules, the designated values corresponding to each slave module being the same;
the fifth message corresponding to each slave module is sent out by the master module at the same time.
14. The method of claim 11, prior to receiving the fourth message sent by the slave module, the method further comprising:
and in response to receiving the first interrupt message sent by the slave module, sending a sixth message to the slave module so as to trigger the slave module to return the fourth message.
15. The method of claim 10, the method further comprising:
sending a seventh message to the slave module to trigger the slave module to return an eighth message; wherein the eighth message carries a time value of a slave clock when the slave module receives the seventh message; according to the time value of the master clock when the master module sends the seventh message, the time value of the slave clock when the slave module receives the seventh message and the transmission delay, whether the master clock and the slave clock are synchronous or not is confirmed; or alternatively, the first and second heat exchangers may be,
Sending a seventh message to the slave module to trigger the slave module to return an eighth message; wherein the eighth message carries a time value of a slave clock when the slave module sends the eighth message; and according to the time value of the master clock when the master module receives the eighth message, the time value of the slave clock when the slave module sends the eighth message and the transmission delay, determining whether the master clock and the slave clock are synchronous.
16. The method of claim 15, further comprising, prior to sending a seventh message to the slave:
sending a ninth message to the slave module to trigger the slave module to return a second interrupt message;
transmitting a seventh message to the slave module, comprising:
and in response to receiving the second interrupt message sent by the slave module, sending a seventh message to the slave module.
17. The method of claim 16, wherein the bus system comprises at least two slave modules, and wherein any two slave modules transmit the second interrupt message for a time interval greater than a third predetermined period of time.
18. The method of claim 10, the method further comprising:
transmitting a tenth message to the slave module to trigger the slave module to acknowledge the time value of the slave clock when the slave module receives the tenth message; the tenth message carries a time value of a master clock when the master module sends the tenth message, so that the slave module confirms whether the master clock and the slave clock are synchronous according to the time value of the slave clock when the slave module receives the tenth message, the time value of the master clock when the master module sends the tenth message and the transmission delay.
19. A bus system, comprising:
a bus;
a slave module configured to implement the clock synchronization method of any one of claims 1 to 9;
a master module configured to implement the clock synchronization method of any one of claims 10 to 18.
20. An electronic assembly comprising the bus system of claim 19.
21. An electronic device comprising the electronic assembly of claim 20.
CN202310752783.8A 2023-06-26 2023-06-26 Clock synchronization method, system, component and equipment Active CN116506096B (en)

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