CN116505928A - Buffer circuit applied to TX clock - Google Patents

Buffer circuit applied to TX clock Download PDF

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Publication number
CN116505928A
CN116505928A CN202310771621.9A CN202310771621A CN116505928A CN 116505928 A CN116505928 A CN 116505928A CN 202310771621 A CN202310771621 A CN 202310771621A CN 116505928 A CN116505928 A CN 116505928A
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clock signal
phase
conversion circuit
output
drain electrode
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CN202310771621.9A
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CN116505928B (en
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栾昌海
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Niuxin Semiconductor Shenzhen Co ltd
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Niuxin Semiconductor Shenzhen Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)

Abstract

Embodiments of the present application provide a buffer circuit for a TX clock, the circuit comprising: a multiplexer module provided with a plurality of clock signal input ports, a clock signal output port and a selection signal input port for determining a target clock signal from the plurality of input clock signals according to the input selection signal and outputting the target clock signal from the clock signal output port; the single-ended transfer differential module is connected with the clock signal output port and is used for generating two-phase clock signals corresponding to the target clock signals; the multiplexer module comprises an inverter unit and an enabling switch unit; the inverter unit is connected with a plurality of clock signal input ports and an enabling switch unit, and the enabling switch unit is also connected with a selection signal input port and a clock signal output port. According to the technical scheme, parasitic capacitance generated in the operation process can be reduced, and therefore transmission capacity is improved.

Description

Buffer circuit applied to TX clock
Technical Field
The present disclosure relates to the field of data transmission technologies, and in particular, to a buffer circuit applied to a TX clock.
Background
In the process of transmitting data, the sender and the receiver need to keep synchronization to ensure that the data can be correctly transmitted, so that the sender usually selects clocks with corresponding frequencies to synchronize according to a protocol corresponding to the data transmission so as to transmit the data.
In the related art, a transmitter generally employs a multi-terminal multiplexer module to access clock signals of multiple frequencies, so as to provide a guarantee for switching corresponding clock signals based on a data transmission protocol. In a conventional multiplexer module, a plurality of received clock signals are generally selected by using a nand gate, but due to the fact that the number of devices adopted by the nand gate is large, parasitic capacitance generated in the operation process of the conventional multiplexer module is large, edge switching of a TX clock signal is slow, and transmission capability is reduced.
Disclosure of Invention
To solve the above technical problem, embodiments of the present application provide a buffer circuit applied to a TX clock.
According to an aspect of an embodiment of the present application, there is provided a buffer circuit applied to a TX clock, including: a multiplexer module provided with a plurality of clock signal input ports, a clock signal output port and a selection signal input port, for determining a target clock signal from the plurality of input clock signals according to the input selection signal and outputting the target clock signal from the clock signal output port; the single-ended to differential module is connected with the clock signal output port and is used for generating a two-phase clock signal corresponding to the target clock signal; the multiplexer module comprises an inverter unit and an enable switch unit; the inverter unit is connected with the plurality of clock signal input ports and the enabling switch, and the enabling switch unit is also connected with the selection signal input port and the clock signal output port and is used for controlling the inverter unit to output the target clock signal after inversion according to the input selection signal.
Optionally, the inverter unit includes a PMOS transistor and a first NMOS transistor, and the enable switch unit includes an inverting PMOS transistor and a second NMOS transistor, where: the grid electrode of the PMOS tube is connected with the grid electrode of the first NMOS tube in parallel and is connected with the clock signal input port, and the second endpoint of the drain electrode is connected with the first endpoint of the drain electrode of the first NMOS tube in parallel and is connected with the clock signal output port; the grid electrode of the inverted PMOS tube is connected with the selection signal input port, the first end point of the drain electrode is connected with a direct current power supply, and the second end point of the drain electrode is connected with the first end point of the drain electrode of the PMOS tube; the grid electrode of the second NMOS tube is connected with the selection signal input port, the first end point of the drain electrode is connected with the second end point of the drain electrode of the first NMOS tube, and the second end point of the drain electrode is grounded.
Optionally, the inverter unit includes a PMOS transistor and a first NMOS transistor, and the enable switch unit includes an inverting PMOS transistor and a second NMOS transistor, where: the grid electrode of the PMOS tube is connected with the grid electrode of the first NMOS tube in parallel and is connected with the clock signal input port, the first end point of the drain electrode is connected with a direct current power supply, and the second end point of the drain electrode is connected with the first end point of the drain electrode of the first NMOS tube; the second end point of the drain electrode of the first NMOS tube is grounded; the first end point of the inverted PMOS tube drain electrode is connected with the first end point of the second NMOS tube drain electrode in parallel, and is connected with the second end point of the PMOS tube drain electrode and/or the first end point of the first NMOS tube drain electrode; the grid electrode of the inverted PMOS tube and the grid electrode of the second NMOS tube are connected with the selection signal input port, and the second end point of the drain electrode of the inverted PMOS tube and the second end point of the drain electrode of the second NMOS tube are connected with the clock signal output port.
Optionally, the multiplexer module further includes a first shaping inverter, an input end of the first shaping inverter is connected with the clock signal input port, and an output end of the first shaping inverter is connected with the inverter unit, where the number of the first shaping inverters is the same as the number of the clock signal input ports and corresponds to the plurality of clock signal input ports one to one.
Optionally, the single-ended to differential module is provided with a target clock signal input port, a first phase output port and a second phase output port, and includes a first phase conversion circuit and a second phase conversion circuit, wherein: the input end of the first phase conversion circuit is connected with the input port of the target clock signal, and the output end of the first phase conversion circuit is connected with the first phase output port and is used for converting the phase of the target clock signal into a first phase and outputting the first phase; the input end of the second phase conversion circuit is connected with the input port of the target clock signal, and the output end of the second phase conversion circuit is connected with the second phase output port and is used for converting the phase of the target clock signal into a second phase and outputting the second phase; the second phase is 180 degrees out of phase with the first phase.
Optionally, each of the first phase conversion circuit and the second phase conversion circuit includes a plurality of inverters sequentially connected, input ends of a first inverter in the first phase conversion circuit and a first inverter in the second phase conversion circuit are both connected with the target clock signal input port, an output end of a last inverter in the first phase conversion circuit is connected with the first phase output port, and an output end of a last inverter in the second phase conversion circuit is connected with the second phase output port; wherein the difference between the number of inverters in the second phase conversion circuit and the number of inverters in the first phase conversion circuit is an odd number.
Optionally, the second phase conversion circuit further comprises a delay device; the input end of the delay device is connected with the output end of the last inverter in the second phase conversion circuit, and the output end of the delay device is connected with the second phase output port and is used for delaying the target clock signal output by the last inverter for a first preset time period and then outputting the delayed target clock signal.
Optionally, the single-ended differential module further comprises a duty cycle calibration circuit; the first input end and the second input end of the duty ratio calibration circuit are respectively connected with the output end of the first phase conversion circuit and the output end of the second phase conversion circuit, the first output end of the duty ratio calibration circuit is connected with the first phase output port, and the second output end of the duty ratio calibration circuit is connected with the second phase output port.
Optionally, the single-ended differential-rotation module further includes a second shaping inverter and a third shaping inverter; the input end of the second shaping inverter is connected with the output end of the first phase conversion circuit, and the output end of the second shaping inverter is connected with the first phase output port; the input end of the third shaping inverter is connected with the output end of the second phase conversion circuit, and the output end of the third shaping inverter is connected with the second phase output port.
Optionally, when the number of the input clock signals is greater than the number of the clock signal input ports of the multiplexer modules, the input clock signals are distributed and connected to the clock signal input ports of at least two multiplexer modules, and the clock signal output ports of the at least two multiplexer modules are connected to the clock signal input port of another multiplexer module, so that the target clock signal is output from the clock signal output port of the other multiplexer module.
In the technical scheme of the embodiment of the application, the multiplexer module receives and processes a plurality of clock signals through the inverter unit, then the enabling switch unit receives the selection signal input by the selection signal input port, and selects the target clock signal from the plurality of clock signals according to the selection signal, so that the target clock signal is transmitted to the single-ended-to-differential module for converting the clock signal into two-phase clock signals, and the differential data transmission technology is convenient to implement.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a circuit schematic diagram of a buffer circuit applied to a TX clock according to an exemplary embodiment of the present application.
Fig. 2 is a circuit schematic diagram of a multiplexer module in a buffer circuit according to an exemplary embodiment of the present application.
Fig. 3 is a circuit schematic of an inverter unit and an enable switch unit in a multiplexer module according to an exemplary embodiment of the present application.
Fig. 4 is a circuit schematic diagram of an inverter unit and an enable switch unit in a multiplexer module according to another exemplary embodiment of the present application.
Fig. 5 is a circuit schematic of a multiplexer module in the buffer circuit shown on the basis of fig. 1.
Fig. 6 is a schematic circuit diagram of a first phase conversion circuit and a second phase conversion circuit in a single-ended to differential module according to an exemplary embodiment of the present application.
Fig. 7 is a circuit schematic diagram of a second phase conversion circuit in the single-ended to differential module shown in fig. 6.
Fig. 8 is a circuit schematic of a single-ended to differential module of the buffer circuit shown in fig. 6.
Fig. 9 is a circuit schematic of a single-ended to differential module of the buffer circuit shown in fig. 1.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present application. One skilled in the relevant art will recognize, however, that the aspects of the application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
It should be noted that: references herein to "a plurality" means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., a and/or B may represent: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
Fig. 1 is a schematic circuit diagram of a buffer circuit applied to a TX clock according to an embodiment of the present application. As shown in fig. 1, the buffer circuit 100 includes a multiplexer module 110 and a single-to-differential module 120, and each of the parts will be described one by one.
The multiplexer module 110 is provided with a plurality of clock signal input ports, a clock signal output port, and a selection signal input port, and is configured to determine a target clock signal from the plurality of input clock signals according to the input selection signal, and output the target clock signal from the clock signal output port.
It should be noted that, the TX clock is used to control the frequency at which the transmitter transmits data, and is synchronized with the frequency at which the receiver receives data. Meanwhile, according to the speed requirements of different transmission protocols, the frequency of the TX clocks is also different, and correspondingly, the mode of generating the TX clocks is also different. For example, when the required clock frequency of the transmission protocol is low, the TX clock corresponding frequency may be generated by Ring Oscillator PLL (Ring Oscillator Phase Locked Loop, loop oscillation phase locked loop), and when the required clock frequency of the transmission protocol is high, the TX clock corresponding frequency may be generated by LC Oscillation PLL (LC Oscillation Phase Locked Loop ).
In the embodiment of the present application, in order to facilitate switching of the output frequency of the TX clock, a plurality of clock signals may be accessed through a multiplexer provided with a plurality of clock signal input ports, and at the same time, the selection signal input port of the multiplexer receives an input selection signal, so as to determine, according to the selection signal, a target clock signal output by the clock signal output port from the input plurality of clock signals, where the target clock signal is a clock signal corresponding to the TX clock frequency required by the current transmission protocol.
Consider that there may be a number of clock signals that is greater than the number of clock signal input ports provided by the multiplexer. Accordingly, a circuit schematic of the multiplexer module 110 as shown in fig. 2 is presented in this application.
Referring to fig. 2, when the number of input clock signals is greater than the number of clock signal input ports of the multiplexer module 110, the input clock signals are distributed to be connected to the clock signal input ports of at least two multiplexer modules 110, and the clock signal output ports of at least two multiplexer modules 110 are connected to the clock signal input ports of another multiplexer module, so that a target clock signal is output from the clock signal output ports of another multiplexer module, thereby completing a function of selecting the target clock signal when the number of clock signals is greater than the number of clock signal input ports of the multiplexer module 110.
Referring to fig. 1, the multiplexer module 110 includes an inverter unit 130 and an enable switch unit 140.
It should be noted that, in the conventional multiplexer module 110, the nand gate is generally used to select the received clock signals, but due to the number of devices adopted by the nand gate, parasitic capacitance generated in the operation process of the conventional multiplexer module 110 is large, so that edge switching of the clock signals is slower, and transmission capability is reduced.
In the embodiment of the present application, the inverter unit 130 in the multiplexer module 110 is connected to a plurality of clock signal input ports and the enable switch unit 140, and the enable switch unit 140 is also connected to a selection signal input port and a clock signal output port for controlling the inverter unit 130 to output the inverted target clock signal according to the input selection signal.
Through the above embodiment, the multiplexer module 110 receives and processes the plurality of clock signals via the inverter unit 130, and then the enable switch unit 140 receives the selection signal input from the selection signal input port, and selects the target clock signal from the plurality of clock signals according to the selection signal, that is, selects the clock signal corresponding to the output frequency required by the current transmission protocol from the plurality of clock signals, and the number of devices used in the manner of enabling the switch to select the target clock signal is smaller than that of the manner of selecting the target clock signal by the nand gate, so that the problem that the multiplexer module 110 generates larger parasitic capacitance in the operation process, and the edge switching of the clock signal is slow is avoided, thereby improving the transmission capability.
The inverter unit 130 and the enable switch unit 140 may be flexibly arranged according to need, and in one example, reference may be made to fig. 3. The inverter unit 130 includes a PMOS transistor P1 and a first NMOS transistor N1, and the enable switch unit 140 includes an inverting PMOS transistor P2 and a second NMOS transistor N2.
The grid electrode of the PMOS tube P1 is connected with the grid electrode of the first NMOS tube N1 in parallel and is connected with the clock signal input port, and the second endpoint of the drain electrode is connected with the first endpoint of the drain electrode of the first NMOS tube N1 in parallel and is connected with the clock signal output port;
the grid electrode of the inverted PMOS tube P2 is connected with the selection signal input port, the first end point of the drain electrode is connected with the direct current power supply, and the second end point of the drain electrode is connected with the first end point of the drain electrode of the PMOS tube P1;
the grid electrode of the second NMOS tube N2 is connected with the selection signal input port, the first end point of the drain electrode is connected with the second end point of the drain electrode of the first NMOS tube N1, and the second end point of the drain electrode is grounded.
In the embodiment of the present application, each clock signal input port is respectively connected to the corresponding inverter unit 130 and the enable switch unit 140, where the enable switch units 140 of each clock signal input port are connected to each other, so that when any one enable switch unit 140 among the plurality of enable switch units 140 is in an on state, the rest enable switch units 140 are adjusted to be in an off state.
Based on the inverter unit 130 and the enable switch unit 140 shown in fig. 3, if the current multiplexer module 110 has the first clock signal and the second clock signal connected thereto, and the frequencies corresponding to the first clock signal and the second clock signal are respectively 50MHz and 100MHz, when the clock signal corresponding to the TX clock frequency required by the transmission protocol is the clock signal of 50MHz, the selection signal corresponding to the first clock signal may be manually input by the user or automatically input after the processor recognizes the transmission protocol, even if the selection signal corresponding to the clock signal of 50MHz is a high level signal.
Therefore, when the first clock signal is input to the inverter unit 130 and the enable switch unit 140, firstly, since the gate of the inverted PMOS transistor P2 and the gate of the second NMOS transistor N2 in the enable switch unit 140 corresponding to the first clock signal both receive the selection signal that is the high level signal, the inverted PMOS transistor P2 and the second NMOS transistor N2 are both in the on state.
Then, each time the gate of the PMOS transistor P1 and the gate of the first NMOS transistor N1 in the inverter unit 130 receive the high level signal of the first clock signal, the PMOS transistor P1 is in an off state, and the first NMOS transistor N1 is in an on state, so that the electrical signal output by the dc power supply connected to the first end of the drain of the inverted PMOS transistor P2 cannot pass through the PMOS transistor P1; meanwhile, the clock signal output port is grounded via the second endpoint of the drain electrode of the second NMOS transistor N2, so that the clock signal output port is output in a low level state.
When the gate of the PMOS transistor P1 and the gate of the first NMOS transistor N1 in the inverter unit 130 receive the low-level signal of the first clock signal, the PMOS transistor P1 is in a turned-on state, and the first NMOS transistor N1 is in an off state, so that an electrical signal output by the dc power supply connected to the first end of the drain of the inverted PMOS transistor P2 is delivered to the clock signal output port, and is turned off by the first NMOS transistor N1, so that the electrical signal output by the dc power supply is output by the clock signal output port, that is, the clock signal output port is changed into a high-level state corresponding to the electrical signal output by the dc voltage.
In addition, when the second clock signal accessed by the front multiplexer module 110 is input to the corresponding inverter unit 130 and the enable switch unit 140, since the enable switch unit 140 corresponding to the first clock signal is already in the on state, the enable switch unit 140 corresponding to the second clock signal is in the off state, that is, the gate of the inverted PMOS transistor P2 and the gate of the second NMOS transistor N2 of the second clock signal corresponding to the enable switch unit 140 both receive the selection signal that is the low level signal, so that the inverted PMOS transistor P2 and the second NMOS transistor N2 both remain in the cut-off state, and thus the electric signal output by the dc power supply connected to the first end of the drain of the inverted PMOS transistor P2 cannot be transmitted to the clock signal output port, and meanwhile, the clock signal output port cannot be grounded through the second end of the drain of the second NMOS transistor N2 that is grounded, so that the clock signal output port remains unchanged regardless of whether the second clock signal is the high level signal or the low level signal.
In another example, the inverter unit 130 includes a PMOS transistor P1 and a first NMOS transistor N1, and the enable switch unit 140 includes an inverted PMOS transistor P2 and a second NMOS transistor N2, which may be further configured as shown in fig. 4.
The grid electrode of the PMOS tube P1 is connected with the grid electrode of the first NMOS tube N1 in parallel and is connected with the clock signal input port, the first end point of the drain electrode is connected with the direct current power supply, and the second end point of the drain electrode is connected with the first end point of the drain electrode of the first NMOS tube N1;
the second end point of the drain electrode of the first NMOS tube N1 is grounded;
the first end point of the drain electrode of the inverted PMOS tube P2 is connected in parallel with the first end point of the drain electrode of the second NMOS tube N2, and is connected with the second end point of the drain electrode of the PMOS tube P1 and/or the first end point of the drain electrode of the first NMOS tube N1;
the grid electrode of the inverted PMOS tube P2 and the grid electrode of the second NMOS tube N2 are connected with the selection signal input port, and the second endpoint of the drain electrode of the inverted PMOS tube P2 and the second endpoint of the drain electrode of the second NMOS tube N2 are connected with the clock signal output port.
Based on the inverter unit 130 and the enable switch unit 140 shown in fig. 4, the current multiplexer module 110 is also connected to the first clock signal and the second clock signal, and if the target clock signal corresponding to the TX clock frequency required by the current transmission protocol is still the first clock signal, the selection signal corresponding to the first clock signal is the high level signal.
When the gate of the PMOS transistor P1 and the gate of the first NMOS transistor N1 in the inverter unit 130 receive the high-level signal of the first clock signal, the PMOS transistor P1 is in the cut-off state, and the first NMOS transistor N1 is in the on state, and meanwhile, the gate of the inverted PMOS transistor P2 and the gate of the second NMOS transistor N2 in the enable switch unit 140 corresponding to the first clock signal both receive the selection signal of the high-level signal, so that the inverted PMOS transistor P2 and the second NMOS transistor N2 are in the on state, and the clock signal output port is grounded via the first NMOS transistor N1 and the second NMOS transistor N2, so that the clock signal output port is output in the low-level state.
When the gate of the PMOS transistor P1 and the gate of the first NMOS transistor N1 in the inverter unit 130 receive the low-level signal of the first clock signal, the PMOS transistor P1 is in a conductive state, the first NMOS transistor N1 is in an off state, and the inverted PMOS transistor P2 and the second NMOS transistor N2 are both in a conductive state, so that an electrical signal output by the dc power supply connected to the first end of the drain of the PMOS transistor P1 is transmitted to the clock signal output port via the inverted PMOS transistor P2 and/or the second NMOS transistor N2, and the first NMOS transistor N1 blocks the dc power supply from being grounded, so that the clock signal output port outputs a high-level state corresponding to the electrical signal output by the dc voltage.
In addition, when the second clock signal accessed by the front multiplexer module 110 is input to the inverter unit 130 and the enable switch unit 140 shown in fig. 4, since the enable switch unit 140 corresponding to the first clock signal is already in the on state, the enable switch unit 140 corresponding to the second clock signal is in the off state, that is, the gate of the inverted PMOS transistor P2 and the gate of the second NMOS transistor N2 of the second clock signal corresponding to the enable switch unit 140 both receive the selection signal being the low level signal, so that the inverted PMOS transistor P2 and the second NMOS transistor N2 both remain in the off state, so that no matter whether the second clock signal is the high level signal or the low level signal, the electrical signal cannot be transmitted to the clock signal output port through the inverted PMOS transistor P2 and/or the second NMOS transistor N2, and the clock signal output port remains unchanged all the time.
Fig. 5 is a circuit schematic of the multiplexer module 110 in the buffer circuit 100 shown on the basis of fig. 1. As shown in fig. 5, the multiplexer module 110 further includes a first shaping inverter 170, an input terminal of the first shaping inverter 170 is connected to the clock signal input port, and an output terminal of the first shaping inverter 170 is connected to the inverter unit 130, where the number of the first shaping inverters 170 is the same as the number of the clock signal input ports and corresponds to the plurality of clock signal input ports one by one.
In the embodiment of the application, the waveform of the received clock signal is considered to change to a certain extent under the condition of interference, so that the subsequent processing of the clock signal is deviated. Therefore, after the waveform shaping is performed on the clock signal input from the clock signal input port by the first shaping inverter 170, the clock signal is transmitted to the inverter unit 130 for further processing, so that the influence of interference on the clock signal is weakened, and the possibility of deviation generated during further processing of the clock signal is reduced.
In addition, in the present application, the multiplexer module 110 is provided with a plurality of clock signal input ports, so that in order to improve the anti-interference capability of the clock signal input by each clock signal input port, a plurality of first shaping inverters 170 are provided and are in one-to-one correspondence with the clock signal input ports, so that each clock signal can be shaped by the corresponding first shaping inverter 170, and the purpose of improving the anti-interference capability is achieved.
Referring to fig. 1, a single-ended to differential module 120 included in the buffer circuit 100 is connected to a clock signal output port, and is configured to generate two-phase clock signals corresponding to a target clock signal.
In the embodiment of the present application, the single-ended-to-differential module 120 may convert a single-phase target clock signal into two-phase clock signals, that is, convert the target clock signal into a differential signal, and output the differential signal through two paths, so that the transmitter may implement a differential data transmission technology based on the target clock signal converted into two phases, thereby improving the anti-interference capability and the capability of suppressing electromagnetic interference during data transmission.
The single-to-differential module 120 may be configured in a manner as shown in fig. 1, where the single-to-differential module 120 is provided with a target clock signal input port, a first phase output port, and a second phase output port, and includes a first phase conversion circuit 150 and a second phase conversion circuit 160.
The input end of the first phase conversion circuit 150 is connected to the input port of the target clock signal, and the output end is connected to the first phase output port, so as to convert the phase of the target clock signal into the first phase and output the first phase.
The input end of the second phase conversion circuit 160 is connected with the input port of the target clock signal, and the output end is connected with the second phase output port, and is used for converting the phase of the target clock signal into the second phase and outputting the second phase; the second phase is 180 degrees out of phase with the first phase.
Fig. 6 is a schematic circuit diagram of the first phase conversion circuit 150 and the second phase conversion circuit 160 in the single-ended to differential module 120 according to the embodiment of the present application. As shown in fig. 6, the first phase conversion circuit 150 and the second phase conversion circuit 160 respectively include a plurality of inverters sequentially connected, wherein the input end of a first inverter of the first phase conversion circuit 150 and the input end of a second inverter of the second phase conversion circuit 160 are connected to the input port of the target clock signal, the output end of a last inverter of the first phase conversion circuit 150 is connected to the first phase output port, and the output end of a last inverter of the second phase conversion circuit 160 is connected to the second phase output port.
Since the two-phase clock signals required by the differential data transmission technology are 180 ° different, the difference between the number of inverters in the second phase conversion circuit 160 and the number of inverters in the first phase conversion circuit 150 in the present application is always an odd number, so that no matter how many inverters are arranged in the first phase conversion circuit 150 and the second phase conversion circuit 160, the output of the first phase conversion circuit 150 and the second phase conversion circuit 160 are always 180 ° different, and the transmission requirement of the differential data transmission technology is satisfied.
Fig. 7 is a circuit schematic diagram of the second phase conversion circuit 160 in the single-ended to differential module 120 shown in fig. 6. As shown in fig. 7, the second phase conversion circuit 160 further includes a delay; the input end of the delay device is connected with the output end of the last inverter in the second phase conversion circuit 160, and the output end of the delay device is connected with the second phase output port and is used for delaying the target clock signal output by the last inverter by a first preset time period and then outputting the delayed target clock signal.
In the process of inverting the received clock signal, the inverter does not output the clock signal after inversion in real time, but needs a certain processing time to output the inverted clock signal corresponding to the clock signal.
In the embodiment of the present application, the number of inverters of the second phase conversion circuit 160 is always smaller than that of the first phase conversion circuit 150, and therefore, the time consumption of the second phase target clock signal output by the second phase conversion circuit 160 is smaller than that of the first phase target clock signal output by the first phase conversion circuit 150. It is possible to ensure that the second phase conversion circuit 160 is output in synchronization with the first phase conversion circuit 150 by providing a delay in the second phase conversion circuit 160 to delay the target clock signal output from the last inverter in the second phase conversion circuit 160 by a first preset period of time and then output it.
The first preset duration may be flexibly adjusted according to needs, that is, according to a difference between the number of inverters in the first phase conversion circuit 150 and the number of inverters in the second phase conversion circuit 160 and a time consumption of outputting the inverted clock signal by a single inverter.
Fig. 8 is a circuit schematic of the single-to-differential module 120 of the buffer circuit 100 shown in fig. 6. As shown in fig. 8, the single-ended to differential module 120 further includes a duty cycle calibration circuit, where a first input terminal and a second input terminal of the duty cycle calibration circuit are respectively connected to the output terminal of the first phase conversion circuit 150 and the output terminal of the second phase conversion circuit 160, and a first output terminal of the duty cycle calibration circuit is connected to the first phase output port, and a second output terminal of the duty cycle calibration circuit is connected to the second phase output port.
It should be noted that, in the transmission process of the clock signal, due to devices and process deviations existing in the transmission link, the duty ratio of the clock signal is easily offset, and if the frequency of the clock signal is too high, the clock signal can not be turned normally even due to the offset of the duty ratio, so that serious timing errors are caused.
In the embodiment of the present application, in order to make the duty ratio of the two-phase clock signal difficult to be misaligned, the duty ratio calibration circuit may calibrate the clock signal of the first phase and the clock signal of the second phase before the first phase output port of the first phase conversion circuit 150 and the second phase output port of the second phase conversion circuit 160 output the clock signals, so as to avoid occurrence of a fault of a timing error due to the duty ratio misalignment of the two-phase clock signals.
Fig. 9 is a circuit schematic of the single-to-differential module 120 of the buffer circuit 100 shown in fig. 1. As shown in fig. 9, the single-ended to differential module 120 further includes a second shaping inverter 180 and a third shaping inverter 190;
an input end of the second shaping inverter 180 is connected with an output end of the first phase conversion circuit 150, and an output end of the second shaping inverter 180 is connected with a first phase output port;
an input terminal of the third shaping inverter 190 is connected to an output terminal of the second phase conversion circuit 160, and an output terminal of the third shaping inverter 190 is connected to the second phase output port.
In this embodiment of the present application, the multiplexer module 110 determines, from a plurality of clock signals, a target clock signal corresponding to an output frequency required by a current transmission protocol and outputs the target clock signal, and then the single-ended-to-differential module 120 converts the generated two-phase target clock signal with a phase difference of 180 ° based on the target clock signal, so as to implement a differential data transmission technology, and the second shaping inverter 180 and the third shaping inverter 190 serve as a final stage processing circuit, so that, on one hand, the two-phase clock signal can be further shaped before being output, and interference suffered by the two-phase clock signal in a transmission process is reduced, on the other hand, the two-phase clock signal can play a role of isolating a front stage and a rear stage, and mutual interference between the front stage and the rear stage in an operation process is avoided.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A buffer circuit for use with a TX clock, the circuit comprising:
a multiplexer module provided with a plurality of clock signal input ports, a clock signal output port and a selection signal input port, for determining a target clock signal from the plurality of input clock signals according to the input selection signal and outputting the target clock signal from the clock signal output port;
the single-ended to differential module is connected with the clock signal output port and is used for generating a two-phase clock signal corresponding to the target clock signal;
wherein the multiplexer module comprises an inverter unit and an enable switch unit;
the inverter unit is connected with the plurality of clock signal input ports and the enabling switch unit, and the enabling switch unit is also connected with the selection signal input port and the clock signal output port and is used for controlling the inverter unit to output the target clock signal after inversion according to the input selection signal.
2. The buffer circuit of claim 1, wherein the inverter unit comprises a PMOS transistor and a first NMOS transistor, and the enable switch unit comprises an inverting PMOS transistor and a second NMOS transistor, wherein:
the grid electrode of the PMOS tube is connected with the grid electrode of the first NMOS tube in parallel and is connected with the clock signal input port, and the second endpoint of the drain electrode is connected with the first endpoint of the drain electrode of the first NMOS tube in parallel and is connected with the clock signal output port;
the grid electrode of the inverted PMOS tube is connected with the selection signal input port, the first end point of the drain electrode is connected with a direct current power supply, and the second end point of the drain electrode is connected with the first end point of the drain electrode of the PMOS tube;
the grid electrode of the second NMOS tube is connected with the selection signal input port, the first end point of the drain electrode is connected with the second end point of the drain electrode of the first NMOS tube, and the second end point of the drain electrode is grounded.
3. The buffer circuit of claim 1, wherein the inverter unit comprises a PMOS transistor and a first NMOS transistor, and the enable switch unit comprises an inverting PMOS transistor and a second NMOS transistor, wherein:
the grid electrode of the PMOS tube is connected with the grid electrode of the first NMOS tube in parallel and is connected with the clock signal input port, the first end point of the drain electrode is connected with a direct current power supply, and the second end point of the drain electrode is connected with the first end point of the drain electrode of the first NMOS tube;
the second end point of the drain electrode of the first NMOS tube is grounded;
the first end point of the inverted PMOS tube drain electrode is connected with the first end point of the second NMOS tube drain electrode in parallel, and is connected with the second end point of the PMOS tube drain electrode and/or the first end point of the first NMOS tube drain electrode;
the grid electrode of the inverted PMOS tube and the grid electrode of the second NMOS tube are connected with the selection signal input port, and the second end point of the drain electrode of the inverted PMOS tube and the second end point of the drain electrode of the second NMOS tube are connected with the clock signal output port.
4. The buffer circuit of claim 1, wherein the multiplexer module further comprises a first shaping inverter, an input of the first shaping inverter being connected to the clock signal input port, an output of the first shaping inverter being connected to the inverter unit, wherein the number of first shaping inverters is the same as the number of clock signal input ports and corresponds one-to-one to the plurality of clock signal input ports.
5. The buffer circuit of claim 1, wherein the single-ended to differential module is provided with a target clock signal input port, a first phase output port, and a second phase output port, comprising a first phase conversion circuit and a second phase conversion circuit, wherein:
the input end of the first phase conversion circuit is connected with the input port of the target clock signal, and the output end of the first phase conversion circuit is connected with the first phase output port and is used for converting the phase of the target clock signal into a first phase and outputting the first phase;
the input end of the second phase conversion circuit is connected with the input port of the target clock signal, and the output end of the second phase conversion circuit is connected with the second phase output port and is used for converting the phase of the target clock signal into a second phase and outputting the second phase; the second phase is 180 degrees out of phase with the first phase.
6. The buffer circuit according to claim 5, wherein each of the first phase conversion circuit and the second phase conversion circuit includes a plurality of inverters connected in sequence, an input terminal of a first inverter of the first phase conversion circuit and the second phase conversion circuit is connected to the target clock signal input port, an output terminal of a last inverter of the first phase conversion circuit is connected to the first phase output port, and an output terminal of a last inverter of the second phase conversion circuit is connected to the second phase output port;
wherein the difference between the number of inverters in the second phase conversion circuit and the number of inverters in the first phase conversion circuit is an odd number.
7. The buffer circuit of claim 6, wherein the second phase conversion circuit further comprises a delay;
the input end of the delay device is connected with the output end of the last inverter in the second phase conversion circuit, and the output end of the delay device is connected with the second phase output port and is used for delaying the target clock signal output by the last inverter for a first preset time period and then outputting the delayed target clock signal.
8. The buffer circuit of claim 5, wherein the single-ended-to-differential module further comprises a duty cycle calibration circuit;
the first input end and the second input end of the duty ratio calibration circuit are respectively connected with the output end of the first phase conversion circuit and the output end of the second phase conversion circuit, the first output end of the duty ratio calibration circuit is connected with the first phase output port, and the second output end of the duty ratio calibration circuit is connected with the second phase output port.
9. The buffer circuit of claim 5, wherein the single-ended to differential module further comprises a second shaping inverter and a third shaping inverter;
the input end of the second shaping inverter is connected with the output end of the first phase conversion circuit, and the output end of the second shaping inverter is connected with the first phase output port;
the input end of the third shaping inverter is connected with the output end of the second phase conversion circuit, and the output end of the third shaping inverter is connected with the second phase output port.
10. The buffer circuit according to claim 1, wherein when the number of clock signals input is greater than the number of clock signal input ports of the multiplexer modules, the input plurality of clock signals are distributed to the clock signal input ports of at least two multiplexer modules, and the clock signal output ports of the at least two multiplexer modules are connected to the clock signal input port of another multiplexer module, so that the target clock signal is output from the clock signal output port of the other multiplexer module.
CN202310771621.9A 2023-06-28 2023-06-28 Buffer circuit applied to TX clock Active CN116505928B (en)

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