CN114448420A - Single-pulse high-level signal synchronization circuit - Google Patents
Single-pulse high-level signal synchronization circuit Download PDFInfo
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- CN114448420A CN114448420A CN202210077045.3A CN202210077045A CN114448420A CN 114448420 A CN114448420 A CN 114448420A CN 202210077045 A CN202210077045 A CN 202210077045A CN 114448420 A CN114448420 A CN 114448420A
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Abstract
The invention discloses a single-pulse high-level signal synchronization circuit, which specifically comprises: the single-pulse high-level signal synchronization module is used for synchronously converting the input single-pulse high-level synchronization signal from a first clock domain to a second clock domain and transmitting the single-pulse high-level synchronization signal to the first AND gate; the single-pulse high-level signal compensation module is used for providing a compensation correction signal for the abnormal single-pulse high-level synchronous signal; and the first AND gate is used for performing AND logic selection on the single-pulse high-level synchronous signal output by the single-pulse high-level signal synchronization module by adopting the compensation correction signal provided by the single-pulse high-level signal compensation module and outputting a normal single-pulse high-level synchronous signal of the second clock domain. The invention not only meets the requirement that the synchronous signal is transmitted from the fast clock domain to the slow clock domain, but also meets the requirement that the signal is transmitted from the slow clock domain to the fast clock domain, and simultaneously solves the problem of abnormal signals in the process of cross-clock domain transmission through compensating and correcting the signal, thereby realizing the final cross-clock domain output of single-pulse high-level synchronous signals.
Description
Technical Field
The invention relates to the field of signal circuit design, in particular to a single-pulse high-level signal synchronization circuit.
Background
There are often multiple clock domain signals present during chip design. When a plurality of clock domain signals exist, chip design needs to relate to the transmission of signals among different clock domains, the most common method for processing the signals by crossing the clock domains in the prior art is to use a register for beating, although the method is simple, the method has obvious limitation, particularly, aiming at a single-pulse high-level signal synchronizing circuit, the single-pulse high-level signal synchronizing circuit is mainly used for realizing the high-level synchronization of the signals of a first time domain of an input single clock cycle to a second time domain, but the current single-pulse high-level signal synchronizing circuit has the problem that the signals cannot be synchronously transmitted from a fast clock domain to a slow clock domain, and the problem that abnormal signals are generated in the synchronous transmission due to the abnormal level state of a reset signal in the signal crossing clock domain transmission process easily exists.
Disclosure of Invention
In order to solve the above problems, the present invention provides a single-pulse high-level signal synchronization circuit, which implements transmission of a signal of a single clock cycle from a first clock domain to a second clock domain, and satisfies both transmission of a synchronization signal from a fast clock domain to a slow clock domain and transmission of a signal from the slow clock domain to the fast clock domain, and at the same time, solves a problem of an abnormal signal occurring in a cross-clock domain transmission process by setting a compensation correction signal, and implements final output of a single-pulse high-level signal across clock domains. The specific technical scheme of the invention is as follows:
a single-pulse high-level signal synchronization circuit specifically comprises: the single-pulse high-level signal synchronization module is connected with the first AND gate and is used for synchronously converting the signal from the first clock domain to the second clock domain; the single-pulse high-level signal compensation module is connected with the first AND gate and is used for providing a compensation correction signal for the abnormal high-level signal output by the signal synchronization circuit module; and the first AND gate is used for outputting a signal which is compensated and corrected by the single-pulse high-level signal compensation module and synchronously converted from the first clock domain to the second clock domain by the signal synchronization circuit module.
Further, the single-pulse high-level signal synchronization module specifically includes: the first and second and third and gates are connected with the first and second registers; the output end of the first phase inverter is connected with the first input end of the second AND gate, the output end of the second AND gate is connected with the reset signal input end of the first register, the output end of the third register is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the first input end of the third AND gate.
Further, an input end of the first inverter in the single-pulse high-level signal synchronization module is used as an input end of the single-pulse high-level signal synchronization module, and is configured to receive a signal that needs to be converted from a first clock domain to a second clock domain.
Further, the first register, the second register and the third register in the single-pulse high-level signal synchronization module are connected in series; the output end of the first register is connected with the first input end of the second register, and the output end of the second register is connected with the first input end of the third register.
Further, the output end of the second register in the single-pulse high-level signal synchronization module is further connected with the second input end of the third and gate.
Further, the single-pulse high-level signal compensation module specifically includes: the fourth AND gate, the fourth register, the fifth register, the sixth register, the third inverter and the fourth inverter; the output end of the fourth register is connected with the first input end of the fifth register, the output end of the fifth register is connected with the first input end of the sixth register, the output end of the sixth register is connected with the input end of the third inverter, the output end of the third inverter is connected with the first input end of the fourth AND gate, and the output end of the fourth AND gate is connected with the input end of the fourth inverter.
Further, an output end of the fifth register in the single-pulse high-level signal compensation module is further connected with a second input end of the fourth and gate.
Furthermore, the output end of a third and gate in the single-pulse high-level signal synchronization module is used as the output end of the single-pulse high-level signal synchronization module and is connected with the first input end of the first and gate; the output end of a fourth inverter in the single-pulse high-level signal compensation module is used as the output end of the single-pulse high-level signal compensation module and is connected with the second input end of the first AND gate; and the output end of the first AND gate is used as the output end of the single-pulse high-level signal synchronization circuit and is used for outputting a signal converted from a first clock domain to a second clock domain.
Further, the reset signal input end of the second register, the reset signal input end of the third register, the reset signal input end of the fourth register, the reset signal input end of the fifth register, the reset signal input end of the sixth register, and the second input end of the second and gate are respectively configured to receive an inverted reset signal.
Further, a clock signal input terminal of the first register, a clock signal input terminal of the second register, a clock signal input terminal of the third register, a clock signal input terminal of the fourth register, a clock signal input terminal of the fifth register, and a clock signal input terminal of the sixth register are respectively configured to receive a clock signal of a second clock domain.
The single-pulse high-level signal synchronization module synchronously transmits the synchronization signal of a single clock period from a first clock domain to a second clock domain, and the compensation and correction of the abnormal single-pulse low-level signal output by the single-pulse high-level signal synchronization module are realized on the basis of the single-pulse high-level signal compensation module, so that the single-pulse high-level signal synchronization circuit is ensured to output the normal single-pulse high-level synchronization signal transmitted from the first clock domain to the second clock domain.
Drawings
Fig. 1 is a block diagram of a single-pulse high-level signal synchronization circuit according to a first embodiment of the present invention.
Fig. 2 is a circuit diagram of a single-pulse high-level signal synchronization module according to a second embodiment of the invention.
Fig. 3 is a circuit diagram of a single-pulse high-level signal compensation module according to a third embodiment of the invention.
FIG. 4 is a circuit diagram of a single-pulse high-level signal synchronization circuit according to a fourth embodiment of the present invention.
Fig. 5 is a waveform diagram of each output terminal of the single-pulse high-level signal synchronization circuit according to an embodiment of the invention.
Fig. 6 is a schematic diagram illustrating a compensated waveform in a single-pulse high-level signal synchronization circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clear, the present invention will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the following specific examples are illustrative only and are not intended to limit the invention. Moreover, it should be understood that the technical disclosure of the present invention may be modified by those skilled in the art by a conventional method, and it should not be understood that the technical disclosure of the present invention is not limited thereto.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. Reference to the words "a," "an," "the," and "the" in this application are not to be construed as limiting in number, and may mean singular or plural. The use of the terms "including," "comprising," "having," and any variations thereof herein, is intended to cover non-exclusive inclusions, such as: a process, method, system product or apparatus that comprises a list of steps or modules is not limited to the listed steps or elements but may include additional steps or elements not listed or inherent to such process, method, product or apparatus. Reference throughout this application to the terms "first," "second," "third," and the like are only used for distinguishing between similar references and not intended to imply a particular ordering for the objects.
As a preferred embodiment of the present invention, a first embodiment of the present invention provides a single-pulse high-level signal synchronization circuit, as shown in fig. 1, the single-pulse high-level signal synchronization circuit specifically includes: the single-pulse high-level signal compensation module comprises a single-pulse high-level signal synchronization module, a single-pulse high-level signal compensation module and a first AND gate; the single-pulse high-level signal synchronization module is used for receiving a signal which needs to be synchronously converted from a first clock domain to a second clock domain, synchronously converting the signal from the first clock domain to the second clock domain and then transmitting the signal to the first AND gate, and the single-pulse high-level signal compensation circuit is used for providing a compensation correction signal for compensation correction when outputting an abnormal high-level signal to the single-pulse high-level signal synchronization module; and the first AND gate is respectively connected with the single-pulse high-level signal synchronization module and the single-pulse high-level signal compensation module, and is used for performing AND logic selection on a signal which is output by the single-pulse high-level signal synchronization module and is converted from a first clock domain to a second clock domain according to a compensation correction signal provided by the single-pulse high-level signal compensation circuit, and outputting a signal which realizes synchronous conversion from the first clock domain to the second clock domain.
It should be noted that, in the prior art, only a part of the single-pulse high-level synchronization module is usually adopted as the single-pulse high-level signal synchronization circuit, which has a problem of outputting an abnormal high-level signal, and the reason for generating the abnormal high-level signal may be that when the synchronization signal in the first time domain received by the single-pulse high-level signal synchronization module is at a low level, the single-pulse high-level signal synchronization module erroneously determines that the received synchronization signal in the first time domain is at a high level due to an abnormal low level of the inverted reset signal input to the single-pulse high-level signal synchronization module, and thus the single-pulse high-level synchronization circuit outputs an abnormal high-level signal, whereas in this embodiment, the single-pulse high-level signal compensation module is arranged in the single-pulse high-level signal synchronization circuit to implement that when the single-pulse high-level signal synchronization module outputs an abnormal high-level signal, the abnormal high level signal is compensated and corrected through AND logic selection of the first AND gate, so that the single-pulse high level signal synchronization circuit can output a normal signal which is synchronously converted from the first clock domain to the second clock domain, and output of a conversion abnormal signal is avoided.
Based on the first embodiment, as a preferred embodiment of the present invention, as shown in fig. 2, the single-pulse high-level signal synchronization module in the second embodiment of the present invention specifically includes: the first and second and third and gates are connected with the first and second registers; the output end of the first phase inverter is connected with the first input end of the second AND gate, the output end of the second AND gate is connected with the reset signal input end of the first register, the output end of the third register is connected with the input end of the second phase inverter, and the input end of the second phase inverter is connected with the first input end of the third AND gate.
Preferably, an input end of the first inverter in the single-pulse high-level signal synchronization module is used as an input end of the single-pulse high-level signal synchronization module, and is configured to receive a signal that needs to be converted from a first clock domain to a second clock domain.
Preferably, the first register, the second register and the third register in the single-pulse high-level signal synchronization module are connected in series; the output end of the first register is connected with the first input end of the second register, and the output end of the second register is connected with the first input end of the third register.
Preferably, the output end of the second register in the single-pulse high-level signal synchronization module is further connected to the second input end of the third and gate.
Based on the foregoing embodiment, as a preferred embodiment of the present invention, as shown in fig. 3, the single-pulse high-level signal compensation module in the third embodiment of the present invention specifically includes: the fourth AND gate, the fourth register, the fifth register, the sixth register, the third inverter and the fourth inverter; the output end of the fourth register is connected with the first input end of the fifth register, the output end of the fifth register is connected with the first input end of the sixth register, the output end of the sixth register is connected with the input end of the third inverter, the output end of the third inverter is connected with the first input end of the fourth AND gate, and the output end of the fourth AND gate is connected with the input end of the fourth inverter.
Preferably, the output end of the fifth register in the single-pulse high-level signal compensation module is further connected to the second input end of the fourth and gate.
Preferably, an output end of a third and gate in the single-pulse high-level signal synchronization module is used as an output end of the single-pulse high-level signal synchronization module and connected to the first input end of the first and gate; the output end of a fourth inverter in the single-pulse high-level signal compensation module is used as the output end of the single-pulse high-level signal compensation module and is connected with the second input end of the first AND gate; and the output end of the first AND gate is used as the output end of the single-pulse high-level signal synchronization circuit and is used for outputting a signal converted from a first clock domain to a second clock domain.
Based on the above embodiments, as a preferred embodiment of the present invention, as shown in fig. 4, in a fourth embodiment of the present invention, a reset signal input terminal of the second register, a reset signal input terminal of the third register, a reset signal input terminal of the fourth register, a reset signal input terminal of the fifth register, a reset signal input terminal of the sixth register, and a second input terminal of the second and gate in the single-pulse high-level synchronous circuit are respectively configured to receive an inverted reset signal. Meanwhile, the clock signal input end of the first register, the clock signal input end of the second register, the clock signal input end of the third register, the clock signal input end of the fourth register, the clock signal input end of the fifth register and the clock signal input end of the sixth register are respectively used for receiving a clock signal of a second clock domain.
It should be noted that reset values of the first register and the fourth register are high level signals, and reset values of the second register, the third register, the fifth register and the sixth register are low level signals.
As shown in fig. 5, fig. 5 is a waveform diagram of each output signal of the single-pulse high-level synchronization circuit in which the compensation module does not generate compensation, where signal _ in refers to a synchronization signal in a first time domain input to the single-pulse high-level synchronization module, and signal _ out refers to a synchronization signal in a second time domain output by the single-pulse high-level synchronization circuit. As can be seen, the first time domain is a slow clock domain compared to the second time domain, and the signal is synchronously transferred from the slow clock domain to the fast clock domain.
As shown in fig. 6, fig. 6 is a waveform diagram of output signals of each output terminal for compensation by the compensation module in the single-pulse high-level signal synchronization circuit, in which signal _ in refers to a synchronization signal of a first time domain input to the single-pulse high-level synchronization module, and signal _ out refers to a synchronization signal of a second time domain output by the single-pulse high-level synchronization circuit, when the single-pulse high-level signal synchronization module outputs an abnormal synchronization signal, the compensation correction module output by the single-pulse high-level signal compensation module performs compensation correction for the abnormal synchronization signal, so as to ensure that a finally output synchronization signal of the second time domain is normal. As shown in fig. 6, the inverted reset signal outputs an abnormal low level signal, which causes the second and gate output signal to be influenced by the abnormal low level signal output by the inverted reset signal and output an abnormal low level signal, the beats of the first register, the second register and the third register are not influenced, the third and gate output signal is influenced by the abnormal low level signal output by the second and gate and output an abnormal high level signal, and the single-pulse high level synchronization circuit is not influenced by the abnormal low level signal under the compensation of the output signal of the fourth inverter in the single-pulse high level signal compensation module, so as to ensure the accuracy of the synchronization signal output by the single-pulse high level signal synchronization circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A single-pulse high-level signal synchronization circuit is characterized by comprising:
the single-pulse high-level signal synchronization module is connected with the first AND gate and is used for synchronously converting the input single-pulse high-level synchronization signal from a first clock domain to a second clock domain;
the single-pulse high-level signal compensation module is connected with the first AND gate and is used for providing a compensation correction signal for the abnormal single-pulse high-level synchronous signal output by the single-pulse high-level signal synchronization module;
and the first AND gate is used for performing AND logic selection on the single-pulse high-level synchronous signal output by the single-pulse high-level signal synchronization module by adopting the compensation correction signal provided by the single-pulse high-level signal compensation module and outputting a normal single-pulse high-level synchronous signal of the second clock domain.
2. The single-pulse high-level signal synchronization circuit according to claim 1, wherein the single-pulse high-level signal synchronization module specifically comprises: the first and second and third and gates are connected with the first and second registers; the output end of the first phase inverter is connected with the first input end of the second AND gate, the output end of the second AND gate is connected with the reset signal input end of the first register, the output end of the third register is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the first input end of the third AND gate.
3. The single-pulse high-level signal synchronizing circuit according to claim 2, wherein an input terminal of the first inverter in the single-pulse high-level signal synchronizing module is used as an input terminal of the single-pulse high-level signal synchronizing module, and is configured to receive a single-pulse high-level synchronizing signal that needs to be converted from a first clock domain to a second clock domain.
4. The single-pulse high-level signal synchronization circuit according to claim 2, wherein the first register, the second register, and the third register in the single-pulse high-level signal synchronization module are connected in series; the output end of the first register is connected with the first input end of the second register, and the output end of the second register is connected with the first input end of the third register.
5. The single-pulse high-level signal synchronization circuit according to claim 4, wherein the output terminal of the second register in the single-pulse high-level signal synchronization module is further connected to the second input terminal of the third AND gate.
6. The single-pulse high-level signal synchronization circuit according to claim 1, wherein the single-pulse high-level signal compensation module specifically comprises: the fourth AND gate, the fourth register, the fifth register, the sixth register, the third inverter and the fourth inverter; the output end of the fourth register is connected with the first input end of the fifth register, the output end of the fifth register is connected with the first input end of the sixth register, the output end of the sixth register is connected with the input end of the third inverter, the output end of the third inverter is connected with the first input end of the fourth AND gate, and the output end of the fourth AND gate is connected with the input end of the fourth inverter.
7. The single-pulse high-level signal synchronization circuit according to claim 6, wherein the output terminal of the fifth register in the single-pulse high-level signal compensation module is further connected to the second input terminal of the fourth and gate.
8. The single-pulse high-level signal synchronization circuit according to claims 2 and 6, wherein an output terminal of a third AND gate in the single-pulse high-level signal synchronization module is connected to the first input terminal of the first AND gate as an output terminal of the single-pulse high-level signal synchronization module; the output end of a fourth inverter in the single-pulse high-level signal compensation module is used as the output end of the single-pulse high-level signal compensation module and is connected with the second input end of the first AND gate; and the output end of the first AND gate is used as the output end of the single-pulse high-level signal synchronization circuit and is used for outputting the single-pulse high-level synchronization signal converted from the first clock domain to the second clock domain.
9. The single-pulse high-level signal synchronizing circuit according to claim 8, wherein the reset signal input terminal of the second register, the reset signal input terminal of the third register, the reset signal input terminal of the fourth register, the reset signal input terminal of the fifth register, the reset signal input terminal of the sixth register, and the second input terminal of the second and gate are configured to receive an inverted reset signal, respectively.
10. The single-pulse high-level signal synchronizing circuit according to claim 9, wherein the clock signal input terminal of the first register, the clock signal input terminal of the second register, the clock signal input terminal of the third register, the clock signal input terminal of the fourth register, the clock signal input terminal of the fifth register, and the clock signal input terminal of the sixth register are respectively configured to receive a clock signal of a second clock domain.
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| CN202210077045.3A CN114448420A (en) | 2022-01-24 | 2022-01-24 | Single-pulse high-level signal synchronization circuit |
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| CN202210077045.3A CN114448420A (en) | 2022-01-24 | 2022-01-24 | Single-pulse high-level signal synchronization circuit |
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