CN116504166A - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
CN116504166A
CN116504166A CN202310484540.0A CN202310484540A CN116504166A CN 116504166 A CN116504166 A CN 116504166A CN 202310484540 A CN202310484540 A CN 202310484540A CN 116504166 A CN116504166 A CN 116504166A
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CN
China
Prior art keywords
gate driving
driving circuit
circuit
pixel
display area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310484540.0A
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Chinese (zh)
Inventor
张金方
吴忠厚
张露
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
Hefei Visionox Technology Co Ltd
Original Assignee
Kunshan Govisionox Optoelectronics Co Ltd
Hefei Visionox Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunshan Govisionox Optoelectronics Co Ltd, Hefei Visionox Technology Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Priority to CN202310484540.0A priority Critical patent/CN116504166A/en
Publication of CN116504166A publication Critical patent/CN116504166A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a first display area, a second display area and a non-display area; the second display area at least partially surrounds the first display area; the second display area is provided with at least one row of first pixel circuits, the first pixel circuits comprise a first side pixel circuit and a second side pixel circuit, and the first side pixel circuit and the second side pixel circuit are distributed on two sides of the first display area; the non-display area is provided with a grid driving circuit; the grid driving circuit comprises a first grid driving circuit and a second grid driving circuit, the first grid driving circuit is arranged on one side of the first side pixel circuit far away from the first display area, and the second grid driving circuit is arranged on one side of the second side pixel circuit far away from the first display area; the at least one first grid driving circuit and the at least one second grid driving circuit are respectively used for driving the first side pixel circuits and the second side pixel circuits of the first pixel circuits in the same row, and the narrow frame design of the hole area is facilitated.

Description

Array substrate and display panel
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
The display panel comprises a display area and a non-display area, wherein the display area is provided with a plurality of rows of pixel units, the non-display area is provided with a plurality of cascaded gate driving circuits, and each stage of gate driving circuit is connected with one row of pixel units through gate signal lines and used for driving the pixel units to display. Display panels are evolving towards full-screen displays. In the full screen, a transparent display area with relatively high light transmittance is required to be arranged in the display area for placing a camera and other structures, and a conventional display area at other positions of the display area at least partially surrounds the transparent display area. The transparent display area cuts off part of the row pixel units of the conventional display area, and when the grid driving circuit drives one row of pixel units, the grid signal lines need to be wound around the transparent display area, so that the frame of the transparent display area is relatively large, and the display effect of the display panel is not facilitated.
Disclosure of Invention
The invention provides an array substrate and a display panel, which are used for realizing the design of a narrow frame of a hole area of the array substrate and improving the display effect of the display panel.
In a first aspect, an embodiment of the present invention provides an array substrate, including a first display area, a second display area, and a non-display area; the second display region at least partially surrounds the first display region, and the non-display region at least partially surrounds the second display region;
The second display area is provided with at least one row of first pixel circuits, the first pixel circuits comprise a first side pixel circuit and a second side pixel circuit, and the first side pixel circuit and the second side pixel circuit are distributed on two sides of the first display area;
the non-display area is provided with a grid driving circuit; the grid driving circuit comprises a first grid driving circuit and a second grid driving circuit, the first grid driving circuit is arranged on one side of the first side pixel circuit, which is far away from the first display area, and the second grid driving circuit is arranged on one side of the second side pixel circuit, which is far away from the first display area; at least one of the first gate driving circuit and the second gate driving circuit is used for driving a first side pixel circuit and a second side pixel circuit of the first pixel circuit in the same row, respectively.
Optionally, the gate driving circuit further includes a third gate driving circuit and a fourth gate driving circuit; the second display area is also provided with a second pixel circuit; the third gate driving circuit and the fourth gate driving circuit drive the second pixel circuit;
along a first direction, at least part of the gate driving circuit has a length smaller than that of the first pixel circuit; wherein the first direction is a column direction of the first pixel circuit.
Optionally, the first gate driving circuit and the third gate driving circuit are disposed on the same side of the second display area, and the second gate driving circuit and the fourth gate driving circuit are disposed on the same side of the second display area; along the first direction, at least one first gate driving circuit is arranged between the third gate driving circuits, and/or at least one second gate driving circuit is arranged between the fourth gate driving circuits.
Optionally, the array substrate further includes an impedance compensation unit;
the first grid driving circuit is connected with the first side pixel circuit through the impedance compensation unit, and/or the second grid driving circuit is connected with the second side pixel circuit through the impedance compensation unit; the impedance compensation unit is used for compensating the impedance of the first pixel circuit.
Optionally, when the first pixel circuit includes transistors of different types, the gate driving circuit further includes a fifth gate driving circuit and a sixth gate driving circuit; the fifth gate driving circuit and the first gate driving circuit are arranged on the same side of the second display area, the sixth gate driving circuit and the second gate driving circuit are arranged on the same side of the second display area, the level of a gate driving signal provided by the fifth gate driving circuit is opposite to the level of a gate driving signal provided by the first gate driving circuit, and the level of a gate driving signal provided by the sixth gate driving circuit is opposite to the level of a gate driving signal provided by the second gate driving circuit; the fifth gate driving circuit and the sixth gate driving circuit are used for driving the first pixel circuit;
Along a first direction, at least part of the length of the fifth gate driving circuit is smaller than the length of the first pixel circuit, and the impedance compensation unit and the fifth gate driving circuit are arranged in the same column; and/or at least part of the length of the sixth gate driving circuit is smaller than the length of the first pixel circuit, and the impedance compensation unit and the sixth gate driving circuit are arranged in the same column; wherein the first direction is a column direction of the first pixel circuit.
Optionally, the impedance compensation unit includes a resistance-capacitance compensation circuit.
Optionally, the circuit topologies of the first gate driving circuit and the second gate driving circuit are the same.
Optionally, the first gate driving circuit includes at least one of a scan circuit and a light emission control circuit.
Optionally, when the gate driving circuit further includes a fifth gate driving circuit and a sixth gate driving circuit, the first gate driving circuit and the second gate driving circuit include a first scanning circuit, the fifth gate driving circuit and the sixth gate driving circuit include a second scanning circuit, and an effective level of a first scanning signal provided by the first scanning circuit is opposite to an effective level of a second scanning signal provided by the second scanning circuit.
In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate in the first aspect.
According to the technical scheme, the first side pixel circuits in the first pixel circuits in the at least one row are driven by the first gate driving circuit, and the second side pixel circuits are driven by the second gate driving circuit, so that the at least one first gate driving circuit is prevented from winding around the first display area to drive the second side pixel circuits, the at least one second gate driving circuit is prevented from winding around the first display area to drive the first side pixel circuits, driving of the first pixel circuits can be achieved, winding around the first display area is reduced, narrow frame design of the first display area is facilitated, and display effect of the display panel can be improved.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate provided in the prior art;
FIG. 2 is a schematic diagram of a pixel circuit according to the prior art;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic structural diagram of an array substrate provided in the prior art. As shown in fig. 1, the array substrate includes a transparent display area 101, a normal display area 102, and a non-display area 103, the normal display area 102 at least partially surrounding the transparent display area 101 (the normal display area 102 is exemplarily shown in fig. 1 to completely surround the transparent display area 101), and the non-display area 103 is disposed around the normal display area 102. The conventional display area 102 is provided with a plurality of rows of pixel circuits 1021 for driving the light emitting elements to emit light. Fig. 2 is a schematic diagram illustrating a pixel circuit according to the prior art. As shown in fig. 2, the pixel circuit is an 8T1C circuit, that is, the pixel circuit includes 8 transistors and 1 capacitor. The gate initializing transistor T1 and the threshold compensating transistor T2 are N-type transistors, and the driving transistor T3 and the other switching transistors are P-type transistors. The non-display region 103 is provided with a gate driving circuit connected to the pixel circuit 1021 through a gate signal line 1022 for supplying a driving signal to the pixel circuit 1021. Exemplarily, referring to fig. 1 and 2, when the pixel circuit is an 8T1C circuit, the gate driving circuit includes a first P-type scan circuit SCANP1, a second P-type scan circuit SCANP2, a first N-type scan circuit SCANN1, a second N-type scan circuit SCANN2, and a light emission control circuit EM1. The two first P-type scan circuits SCANP1 provide scan signals for the P-type transistors in the partial row of pixel circuits 1021, and the scan signals of the P-type transistors in the partial row of pixel circuits 1021 are bilateral driving. The second P-type scan circuit SCANP2 provides scan signals for the P-type transistors in the other part of the row pixel circuits 1021, and the scan signals for the P-type transistors in the other part of the row pixel circuits 1021 are driven in a single side. The first N-type scan circuit scan 1 and the second N-type scan circuit scan 2 provide scan signals for N-type transistors in the pixel circuits 1021 in different rows, and the scan signals of the N-type transistors in the pixel circuits 1021 are driven in a single side. The light emission control circuit EM1 provides the pixel circuit 1021 with a light emission control signal, and at this time, the light emission control signal of the pixel circuit 1021 is driven in one side. When the gate driving circuit unilaterally drives the pixel circuit 1021, the gate signal line 1022 needs to be wound at the transparent display area 101, so that the frame area around the transparent display area 101 is relatively large, which is not beneficial to realizing the narrow frame design of the panel hole area of the display panel, and reduces the display effect of the display panel.
Aiming at the technical problems, the embodiment of the invention provides an array substrate. Fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. As shown in fig. 3, the array substrate includes a first display area 110, a second display area 120, and a non-display area 130; the second display area 120 at least partially surrounds the first display area 110, and the non-display area 130 at least partially surrounds the second display area 120; the second display area 120 is provided with at least one row of first pixel circuits P1, the first pixel circuits P1 include a first side pixel circuit P11 and a second side pixel circuit P12, and the first side pixel circuit P11 and the second side pixel circuit P12 are distributed on two sides of the first display area 110; the non-display region 130 is provided with a gate driving circuit; the gate driving circuit includes a first gate driving circuit 131 and a second gate driving circuit 132, the first gate driving circuit 131 is disposed at a side of the first side pixel circuit P11 far from the first display region 110, and the second gate driving circuit 132 is disposed at a side of the second side pixel circuit P12 far from the first display region 110; the first gate driving circuit 131 is used for driving the first side pixel circuit P11, and the second gate driving circuit is used for driving the second side pixel circuit P12; the at least one first gate driving circuit 131 and second gate driving circuit 132 are used to drive the first side pixel circuit P11 and second side pixel circuit P12 of the same row of first pixel circuits P1, respectively.
Specifically, the display panel may be a full screen display panel. The first display area 110 may be a transparent display area of a display panel, and may also be referred to as a sub-screen of the display panel. The shape of the first display area 110 is not limited. Illustratively, the first display area 110 may be circular, drop-shaped, U-shaped, etc., and the first display area 110 is illustratively shown in FIG. 3 as circular. The second display area 120 may be a conventional display area of a display panel, or a main screen called a display panel. In addition, it is exemplarily shown in fig. 3 that the second display area 120 completely surrounds the first display area 110, such that the display panel forms an offshore type full screen display panel. The first display area 110 may only be provided with a light emitting element to ensure light transmittance of the first display area 110, so that a photosensitive element may be disposed at a position opposite to the first display area 110, so as to realize under-screen sensitization of the display panel, and further realize full-screen display of the display panel. The light emitting element may be an organic light emitting diode (organic light emitting diode, OLED), for example. The photosensitive element can be a camera, and can realize the under-screen shooting of the display panel. A transition region (not shown in fig. 3) may be further provided between the first display region 110 and the second display region 120, and the transition region may be provided with a pixel circuit connected to the light emitting element of the first display region 110 for driving the light emitting element within the first display region 110 to emit light. In addition, the non-display area 130 may be a bezel area of the display panel, and the non-display area 130 is exemplarily shown in fig. 3 to completely surround the second display area 120.
The second display area 120 is provided with at least one row of first pixel circuits P1. When the second display area 120 at least partially surrounds the first display area 110, the first display area 110 blocks at least one row of pixel circuits of the second display area 120, that is, along a row direction in which the first pixel circuits P1 are arranged, the at least one row of first pixel circuits P1 includes a first side pixel circuit P11 and a second side pixel circuit P12 on both sides of the first display area 110. When the non-display area 130 at least partially surrounds the second display area 120, the non-display area 130 may be disposed at both sides of the second display area 120 along the row direction in which the first pixel circuits P1 are arranged. The non-display area 130 is provided with a first gate driving circuit 131 and a second gate driving circuit 132, the first gate driving circuit 131 is disposed on a side of the first side pixel circuit P11 away from the first display area 110, and the second gate driving circuit 132 is disposed on a side of the second side pixel circuit P12 away from the first display area 110 for driving the first pixel circuit P1. For example, when the array substrate includes a plurality of rows of the first pixel circuits P1, the first gate driving circuit 131 may drive a part of the rows of the first pixel circuits P1, the second gate driving circuit 132 may drive another part of the rows of the first pixel circuits P1, and the first pixel circuits P1 may be driven by the first gate driving circuit 131 and the second gate driving circuit 132 at the same time, so that a single-side driving of the first pixel circuits P1 may be realized, which reduces the number of the first gate driving circuit 131 and the second gate driving circuit 132, and is beneficial to realizing a narrow frame of the display panel. For example, the first gate driving circuit 131 drives the odd-numbered row first pixel circuits P1, and the second gate driving circuit 132 drives the even-numbered row first pixel circuits P1. At this time, the first gate driving circuit 131 is wound around the first display area 110 to drive the second side pixel circuits P12 of the odd-numbered row first pixel circuits P1, and the second gate driving circuit 132 is wound around the first display area 110 to drive the first side pixel circuits P11 of the even-numbered row first pixel circuits P1.
When the at least one first gate driving circuit 131 and the second gate driving circuit 132 are used for driving the first side pixel circuit P11 and the second side pixel circuit P12 of the same row of the first pixel circuit P1 respectively, the first side pixel circuit P11 in the at least one row of the first pixel circuit P1 is driven by the first gate driving circuit 131, and the second side pixel circuit P12 is driven by the second gate driving circuit 132, at this time, the sum of the numbers of the first gate driving circuit 131 and the second gate driving circuit 132 is greater than the number of rows of the first pixel circuit P1, so that the at least one first gate driving circuit 131 can be prevented from winding around the first display area 110 to drive the second side pixel circuit P12, and the at least one second gate driving circuit 132 is wound around the first display area 110 to drive the first side pixel circuit P11, so that the driving of the first pixel circuit P1 can be realized, the winding around the first display area 110 is reduced, the narrow frame of the first display area 110 is facilitated, and the display effect of the display panel can be improved.
Illustratively, as shown in fig. 3, the first gate driving circuit 131 drives the first side pixel circuits P11 of the first row first pixel circuits P1, the first second gate driving circuit 132 drives the second side pixel circuits P12 of the first row first pixel circuits P1, the other first gate driving circuits 131 drive the other odd row first pixel circuits P1, and the other second gate driving circuits 132 drive the even row first pixel circuits P1. At this time, when the first gate driving circuit 131 drives the first row of the first pixel circuits P1, the first display area 110 can be prevented from being wound to connect with the second side of the pixel circuits P12, so that the winding around the first display area 110 can be reduced, which is beneficial to realizing the narrow frame design of the first display area 110.
According to the technical scheme, at least one first grid driving circuit and at least one second grid driving circuit are arranged and used for driving a first side pixel circuit and a second side pixel circuit of the same row of first pixel circuits respectively, so that the first side pixel circuits in the at least one row of first pixel circuits are driven by the first grid driving circuits, and meanwhile, the second side pixel circuits are driven by the second grid driving circuits, and therefore the fact that the at least one first grid driving circuits are wound around a first display area to drive the second side pixel circuits can be avoided, the at least one second grid driving circuits are wound around the first display area to drive the first side pixel circuits can be achieved, winding around the first display area is reduced, narrow frame design of the first display area is facilitated, and display effect of a display panel can be improved.
Fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 4, the gate driving circuit further includes a third gate driving circuit 133 and a fourth gate driving circuit 134; the second display area 120 is further provided with a second pixel circuit P2; the third gate driving circuit 133 and the fourth gate driving circuit 134 drive the second pixel circuit P2; along the first direction Y, at least a portion of the gate driving circuit has a length smaller than that of the first pixel circuit P1; the first direction Y is a column direction of the first pixel circuit P1.
Specifically, the third gate driving circuit 133 and the fourth gate driving circuit 134 may be disposed on both sides of the second display region 120 along the row direction of the first pixel circuit P1, respectively, and the third gate driving circuit 133 and the fourth gate driving circuit 134 may drive the second pixel circuits P2 of different rows to realize single-side driving of the second pixel circuits P2. The second pixel circuit P2 is disposed on one side of the first display region 110 along the first direction Y, and no winding around the first display region 110 is required when the third gate driving circuit 133 and the fourth gate driving circuit 134 drive the second pixel circuit P2. Illustratively, the third gate driving circuit 133 may drive the odd-numbered row second pixel circuits P2, and the fourth gate driving circuit 134 may drive the even-numbered row second pixel circuits P2. The sum of the numbers of the third gate driving circuit 133 and the fourth gate driving circuit 134 is equal to the number of rows of the second pixel circuit P2.
In the first direction Y, the length of the second pixel circuit P2 may be equal to the length of the first pixel circuit P1. Illustratively, the first pixel circuit P1 and the second pixel circuit P1 have the same circuit topology, i.e., the first pixel circuit P1 and the second pixel circuit P2 have the same elements and the connection relationship between the elements is the same. When at least one first gate driving circuit 131 and second gate driving circuit 132 are used to drive the first side pixel circuits P11 and second side pixel circuits P12 of the same row of first pixel circuits P1, respectively, the sum of the number of first gate driving circuits 131 and the number of second gate driving circuits 132 is greater than the number of rows of first pixel circuits P1, and at this time, the length of at least a part of the gate driving circuits is smaller than the length of the first pixel circuits P1, so that the length of the first direction Y occupied by the gate driving circuits required when the first pixel circuits P1 and the second pixel circuits P2 are driven by the single-side gate driving circuit can be reduced, and thus, there can be a free space in the first direction Y for setting more first gate driving circuits 131 and/or second gate driving circuits 132 to increase the number of first gate driving circuits 131 and/or second gate driving circuits 132, so that the at least one first gate driving circuit 131 and second gate driving circuits 132 can drive the first side pixel circuits P11 and the second side pixel circuits P12 of the same row of first pixel circuits P1, respectively.
Illustratively, as shown in fig. 4, in the first direction Y, the lengths of the second gate driving circuit 132 and the fourth gate driving circuit 134 are smaller than the length of the first pixel circuit P1, and then the positions of the columns where the second gate driving circuit 132 and the fourth gate driving circuit 134 are located leave more space for setting more second gate driving circuits 132 so that the number of the second gate driving circuits 132 is greater than the number of even rows of the first pixel circuit P1. In fig. 4, the number of the second gate driving circuits 132 is four more than the number of the even-numbered rows of the first pixel circuits P1, when the first gate driving circuits 131 drive the odd-numbered row first pixel circuits P1 and the second gate driving circuits 132 equal to the number of the even-numbered row first pixel circuits P1 drive the even-numbered row first pixel circuits P1, the redundant second gate driving circuits 132 can simultaneously drive the second side pixel circuits P12 of the odd-numbered row first pixel circuits P1, and the first gate driving circuits 131 correspondingly connected with the odd-numbered rows drive the first side pixel circuits P11 of the odd-numbered row first pixel circuits P1, thereby avoiding the first gate driving circuits 131 to wire-drive the second side pixel circuits P12 of the odd-numbered row first pixel circuits P1 around the first display area 110, reducing the wire-wound around the first display area 110, being beneficial to realizing the narrow frame design of the first display area 110, and further improving the display effect of the display panel. While the other first gate driving circuits 131 wind around the first display area 110 to drive the first pixel circuits P1 of the other odd rows.
It should be noted that, in fig. 4, it is exemplarily shown that the lengths of the second gate driving circuit 132 and the fourth gate driving circuit 134 are both smaller than the length of the first pixel circuit P1, so as to realize that there is more space for setting more second gate driving circuits 132. In other embodiments, the lengths of the first gate driving circuit 131 and the third gate driving circuit 133 may also be set smaller than the length of the first pixel circuit P1 to realize that there is more space for setting more first gate driving circuits 131. Fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 5, along the first direction Y, the lengths of the first gate driving circuit 131 and the third gate driving circuit 133 are smaller than the length of the first pixel circuit P1, so that the positions of the columns where the first gate driving circuit 131 and the third gate driving circuit 133 are located leave more apertures for setting more first gate driving circuits 131, so that the number of the first gate driving circuits 131 is greater than the number of odd rows of the first pixel circuit P1. The number of the first gate driving circuits 131 is exemplarily shown in fig. 5 to be four more than the number of even lines of the first pixel circuit P1. When the second gate driving circuit 132 drives the even-line first pixel circuits P1 and the first gate driving circuits 131 equal in number to the odd-line first pixel circuits P1 drive the odd-line first pixel circuits P1, the redundant first gate driving circuits 131 can simultaneously drive the first side pixel circuits P11 of the even-line first pixel circuits P1, and the second gate driving circuit 132 correspondingly connected with the even-line first pixel circuits P1 drives the second side pixel circuits P12 of the even-line first pixel circuits P1, thereby avoiding the second gate driving circuit 132 from winding around the first display area 110 to drive the first side pixel circuits P11 of the even-line first pixel circuits P1, reducing the winding around the first display area 110, being beneficial to realizing the narrow frame design of the first display area 110, and further improving the display effect of the display panel. While the other second gate driving circuits 132 wind around the first display area 110 to drive the other even rows of the first pixel circuits P1.
In addition, with continued reference to fig. 5, the lengths of the second gate driving circuit 132 and the fourth gate driving circuit 134 along the first direction Y may be set to be smaller than the length of the first pixel circuit P1, and the lengths of the first gate driving circuit 131 and the third gate driving circuit 133 may be set to be smaller than the length of the first pixel circuit P1, so that more space may be provided for setting more first gate driving circuits 131 and second gate driving circuits 132 at the same time, so that the windings of the first gate driving circuit 131 and the second gate driving circuit 132 around the first display area 110 may be reduced at the same time, the windings around the first display area 110 may be further reduced, and the narrow frame design of the first display area 110 may be facilitated.
The gate driving circuit includes an output transistor, which may include a plurality of gates. When the length of at least part of the gate driving circuits is smaller than the length of the first pixel circuits P1 along the first direction Y, the number of columns of gates of the output transistors arranged along the first direction Y is greater than one column, so that the number of gates arranged per column is smaller, thereby reducing the length of the output transistors along the first direction Y, and further reducing the length of the gate driving circuits along the first direction Y, and further arranging more first gate driving circuits 131 and/or second gate driving circuits 132 along the first direction Y. Illustratively, the output transistor of the gate driving circuit includes 4 gates, by arranging 3 gates arranged along the first direction Y, and 1 gate and 3 gates arranged along the row direction of the first pixel circuit P1, so that the 4 gates of the output transistor are arranged in two columns, and the length required to be occupied by 1 gate is reduced relative to the 4 gates of the output transistor arranged along the first direction Y, thereby the length of the gate driving circuit along the first direction Y can be reduced.
With continued reference to fig. 4 and 5, the first gate driving circuit 131 and the third gate driving circuit 133 are disposed on the same side of the second display area 120, and the second gate driving circuit 132 and the fourth gate driving circuit 134 are disposed on the same side of the second display area 120; along the first direction Y, at least one first gate driving circuit 131 is disposed between the third gate driving circuits 133 and/or at least one second gate driving circuit 132 is disposed between the fourth gate driving circuits 134.
Specifically, the first gate driving circuit 131 and the third gate driving circuit 133 may be disposed in the same column and may be cascaded to provide the same driving signal to the first pixel circuit P1 and the second pixel circuit P2. The second gate driving circuit 132 and the fourth gate driving circuit 134 may be arranged in the same column and may be cascaded to provide the same driving signal to the first pixel circuit P1 and the second pixel circuit P2. In the first direction Y, the lengths of the first and third gate driving circuits 131 and 133 are smaller than the length of the first pixel circuit P1, and when an empty space is used to set more first gate driving circuits 131, the first gate driving circuits 131 may be divided into a normal first gate driving circuit and an unnecessary first gate driving circuit. The conventional first gate driving circuits are disposed corresponding to the first pixel circuits P1 along the row direction of the first pixel circuits P1, and the number of the conventional first gate driving circuits is equal to the odd-numbered rows of the first pixel circuits P1 for providing driving signals for the odd-numbered rows of the first pixel circuits P1. While the conventional first gate driving circuit and the third gate driving circuit 133 are divided into a plurality of cells by a certain number, each cell being used for setting an unnecessary first gate driving circuit therebetween. Illustratively, a plurality of gate driving units may be divided for 2 in the sum of the numbers of the conventional first and third gate driving circuits 133 along the first direction Y, and the space left by each gate driving unit may be provided with an excess first gate driving circuit and connected to the first side pixel circuit P11 of the first pixel circuit P1 to reduce the wiring of the second gate driving circuit 132 around the first display region 110. For example, along the row direction of the first pixel circuits P1, 2 rows of pixel circuits (including the first pixel circuits P1 and the second pixel circuits P2) may be provided corresponding to 3 gate driving circuits (including the first gate driving circuit 131 and the third gate driving circuit 133), and an unnecessary one gate driving circuit is provided as an unnecessary first gate driving circuit for driving the first side pixel circuits P11 of one row of the first pixel circuits P1 while one second gate driving circuit 132 drives the second side pixel circuits P12 of the same row of the first pixel circuits P1.
Similarly, in the first direction Y, the lengths of the second gate driving circuit 132 and the fourth gate driving circuit 134 are smaller than the length of the first pixel circuit P1, and when the spare space is used for setting more second gate driving circuits 132, the second gate driving circuits 132 may be divided into a conventional second gate driving circuit and a spare second gate driving circuit. The conventional second gate driving circuits are disposed corresponding to the first pixel circuits P1 along the row direction of the first pixel circuits P1, and the number of the conventional second gate driving circuits is equal to the even number of the first pixel circuits P1 for providing driving signals for the even number of the first pixel circuits P1. While the conventional second gate driving circuit and the fourth gate driving circuit 134 are divided into a plurality of cells by a certain number, each cell being used for providing an unnecessary second gate driving circuit therebetween. Illustratively, a plurality of gate driving units may be divided for 2 in the sum of the numbers of the conventional second and fourth gate driving circuits 134 along the first direction Y, and the space left by each gate driving unit may be provided with an unnecessary second gate driving circuit and connected to the second side pixel circuit P12 of the first pixel circuit P1 to reduce the wiring of the first gate driving circuit 131 around the first display region 110. For example, along the row direction of the first pixel circuits P1, 2 rows of pixel circuits (including the first pixel circuits P1 and the second pixel circuits P2) may be provided corresponding to 3 gate driving circuits (including the second gate driving circuit 132 and the fourth gate driving circuit 134), and an unnecessary one gate driving circuit is provided as an unnecessary second gate driving circuit for driving the second side pixel circuits P12 of the first pixel circuits P1 of one row while one first gate driving circuit 131 drives the first side pixel circuits P11 of the first pixel circuits P1 of the same row. When the same first pixel circuit P1 is driven, the conventional first gate driving circuit and the redundant second gate driving circuit respectively drive the first side pixel circuit P11 and the second side pixel circuit P12 of the same row of the first pixel circuit P1. The conventional second gate driving circuit and the unnecessary first gate driving circuit drive the second side pixel circuit P12 and the first side pixel circuit P11 of the same row of the first pixel circuit P1, respectively.
It should be noted that, in other embodiments, the redundant first gate driving circuit and/or the redundant second gate driving circuit may be disposed in a centralized manner. Fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 6, in the first direction Y, the redundant first gate driving circuit is disposed on a side of the third gate driving circuit 133 away from the conventional first gate driving circuit, and the redundant second gate driving circuit is disposed on a side of the fourth gate driving circuit 134 away from the conventional second gate driving circuit.
Based on the above technical solutions, fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 7, the array substrate further includes an impedance compensation unit 140; the first gate driving circuit 131 is connected to the first side pixel circuit P11 through the impedance compensation unit 140, and/or the second gate driving circuit 132 is connected to the second side pixel circuit P12 through the impedance compensation unit 140; the impedance compensation unit 140 is used for compensating the impedance of the first pixel circuit P1.
Specifically, when at least one first gate driving circuit 131 and one second gate driving circuit 132 are used to drive the first side pixel circuit P11 and the second side pixel circuit P12 of the same row of the first pixel circuits P1, respectively, the load corresponding to the first gate driving circuit 131 is the first side pixel circuit P11, and the load corresponding to the second gate driving circuit 132 is the second side pixel circuit P12. At this time, the loads corresponding to the first gate driving circuit 131 and the second gate driving circuit 132 are smaller than the loads corresponding to the other gate driving circuits driving one row of the first pixel circuits P1 or one row of the second pixel circuits P2. By arranging the first gate driving circuit 131 to be connected with the first side pixel circuit P11 through the impedance compensation unit 140, the load corresponding to the first gate driving circuit 131 can be compensated, so that the difference between the driving signals provided by the first gate driving circuit 131 and the driving signals provided by other gate driving circuits can be reduced, the difference between the driving currents provided by the first side pixel circuit P11 and the second pixel circuit P2 for the light emitting element is reduced, and the mura risk of the display panel is reduced. Similarly, by setting the second gate driving circuit 132 to be connected to the second side pixel circuit P12 through the impedance compensation unit 140, the load corresponding to the second gate driving circuit 132 can be compensated, so that the difference between the driving signals provided by the second gate driving circuit 132 and the driving signals provided by other gate driving circuits can be reduced, the difference between the driving currents provided by the second side pixel circuit P12 and the second pixel circuit P2 for the light emitting element is reduced, and the mura risk of the display panel is reduced.
With continued reference to fig. 7, when the first pixel circuit P1 includes transistors of different types, the gate driving circuit further includes a fifth gate driving circuit 135 and a sixth gate driving circuit 136; the fifth gate driving circuit 135 and the first gate driving circuit 131 are disposed on the same side of the second display area 120, the sixth gate driving circuit 136 and the second gate driving circuit 132 are disposed on the same side of the second display area 120, the level of the gate driving signal provided by the fifth gate driving circuit 135 is opposite to the level of the gate driving signal provided by the first gate driving circuit 131, and the level of the gate driving signal provided by the sixth gate driving circuit 136 is opposite to the level of the gate driving signal provided by the second gate driving circuit 132; the fifth gate driving circuit 135 and the sixth gate driving circuit 136 are for driving the first pixel circuit P1; along the first direction Y, at least a portion of the length of the fifth gate driving circuit 135 is smaller than the length of the first pixel circuit P1, and the impedance compensation unit 140 is arranged in the same column as the fifth gate driving circuit 135; and/or, at least part of the length of the sixth gate driving circuit 136 is smaller than the length of the first pixel circuit P1, and the impedance compensation unit 140 is arranged in the same column as the sixth gate driving circuit 136; the first direction Y is a column direction of the first pixel circuit P1.
Specifically, the first pixel circuit P1 may include both a P-type transistor and an N-type transistor, and the pixel circuit provided in fig. 2 is an 8T1C circuit, where the gate initializing transistor T1 and the threshold compensating transistor T2 are N-type transistors, and the other transistors are P-type transistors. The driving signal required for the first pixel circuit P1 at this time includes two kinds of scanning signals and light emission control signals for opposite levels.
When the fifth gate driving circuit 135 and the sixth gate driving circuit 136 are used for driving the first pixel circuit P1, the fifth gate driving circuit 135 and the sixth gate driving circuit 136 may both drive each row of the first pixel circuit P1, so that the first pixel circuit P1 realizes bilateral driving. Illustratively, the fifth gate driving circuit 135 and the sixth gate driving circuit 136 may provide a scan signal to the P-type transistor in the first pixel circuit P1. At this time, the first and second gate driving circuits 131 and 132 may provide a scan signal to the N-type transistor in the first pixel circuit P1 and/or provide a light emission control signal to the first pixel circuit P1. By setting the length of at least part of the fifth gate driving circuit 135 along the first direction Y to be smaller than the length of the first pixel circuit P1, a space can be left in the column where the fifth gate driving circuit 135 is located, and by setting the impedance compensation unit 140 in the space, the impedance compensation unit 140 can be prevented from additionally occupying a non-display area on the array substrate, which is beneficial to realizing narrow frame design. At the same time, the impedance compensation unit 140 can be prevented from setting the display area (including the first display area 110 and the second display area 120) to affect the display effect of the display panel.
On the basis of the technical schemes, the impedance compensation unit comprises a resistance-capacitance compensation circuit.
In particular, the impedance compensation unit may include a resistance-capacitance compensation circuit for implementing RC compensation when the at least one first gate driving circuit drives the first side pixel circuit, and/or implementing RC compensation when the at least one second gate driving circuit drives the second side pixel circuit, so as to reduce the difference of driving currents provided by the first pixel circuit and the second pixel circuit to the light emitting element, and reduce mura risk of the display panel.
Based on the technical schemes, the circuit topologies of the first grid driving circuit and the second grid driving circuit are the same.
Specifically, the circuit topologies of the first gate driving circuit and the second gate driving circuit are the same, that is, the first gate driving circuit and the second gate driving circuit have the same circuit element, and the connection relationship between the circuit elements is the same, and the driving signals output by the first gate driving circuit and the second gate driving circuit are the same, so that the same driving signal can be provided for the first pixel circuits in the same row. The first gate driving circuit and the second gate driving circuit may be, for example, a scanning circuit, and may also be a light emission control circuit.
On the basis of the above technical solutions, the first gate driving circuit includes at least one of a scanning circuit and a light emission control circuit.
Specifically, when the first gate driving circuit includes a scanning circuit, the second gate driving circuit includes a scanning circuit. The first gate driving circuit and the second gate driving circuit provide scanning signals for the first pixel circuit. At this time, the third gate driving circuit and the fourth gate driving circuit may also be scanning circuits, and may provide scanning signals for the second pixel circuits. When the first gate driving circuit includes a light emission control circuit, the second gate driving circuit includes a light emission control circuit, and the first gate driving circuit and the second gate driving circuit supply light emission control signals to the first pixel circuit. At this time, the third gate driving circuit and the fourth gate driving circuit may also be light emission control circuits for providing light emission control signals for the second pixel circuits. When the first gate driving circuit includes both a scanning circuit and a light emission control circuit, the second gate driving circuit includes both a scanning circuit and a light emission control circuit, the scanning circuit provides a scanning signal for the first pixel circuit, and the light emission control circuit provides a light emission control signal for the first pixel circuit. At this time, the third gate driving circuit and the fourth gate driving circuit may also include a scanning circuit and a light emission control circuit, where the scanning circuit provides a scanning signal for the second pixel circuit and the light emission control circuit provides a light emission control signal for the second pixel circuit. In addition, the circuit topologies of the first gate driving circuit and the second gate driving circuit are the same, and when the first gate driving circuit includes both the scanning circuit and the light emission control circuit, the second gate driving circuit includes both the scanning circuit and the light emission control circuit.
On the basis of the technical scheme, when the gate driving circuit further comprises a fifth gate driving circuit and a sixth gate driving circuit, the first gate driving circuit and the second gate driving circuit comprise a first scanning circuit, the fifth gate driving circuit and the sixth gate driving circuit comprise a second scanning circuit, and the effective level of a first scanning signal provided by the first scanning circuit is opposite to the effective level of a second scanning signal provided by the second scanning circuit.
Specifically, when the first pixel circuit includes transistors of different types, the scanning signal required for the first pixel circuit includes two kinds of scanning signals of high and low levels. At this time, the effective level of the first scanning signal provided by the first scanning circuit is set to be opposite to the effective level of the second scanning signal provided by the second scanning circuit, so that different scanning signals can be provided for the first pixel circuit. The fifth gate driving circuit and the sixth gate driving circuit can be bilateral driving, and the second scanning circuit is arranged to provide scanning signals for the P-type transistors in the first pixel circuit, so that load variation of the scanning signals corresponding to the P-type transistors in the first pixel circuit can be reduced, and display uniformity of the display panel can be improved. At this time, the first scanning circuit may provide a scanning signal for the N-type transistor in the first pixel circuit.
The embodiment of the invention also provides a display panel. Fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 8, the display panel 10 includes an array substrate 11 according to any embodiment of the present invention.
Specifically, the display panel 10 includes the array substrate 11 provided in any embodiment of the present invention, so that the array substrate provided in any embodiment of the present invention has the same beneficial effects, and will not be described herein again. The display panel can be any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame and the like.
The embodiment of the invention also provides a display device. Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 9, the display device 20 includes a display panel 21 provided in any embodiment of the present invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (10)

1. The array substrate is characterized by comprising a first display area, a second display area and a non-display area; the second display region at least partially surrounds the first display region, and the non-display region at least partially surrounds the second display region;
the second display area is provided with at least one row of first pixel circuits, the first pixel circuits comprise a first side pixel circuit and a second side pixel circuit, and the first side pixel circuit and the second side pixel circuit are distributed on two sides of the first display area;
the non-display area is provided with a grid driving circuit; the grid driving circuit comprises a first grid driving circuit and a second grid driving circuit, the first grid driving circuit is arranged on one side of the first side pixel circuit, which is far away from the first display area, and the second grid driving circuit is arranged on one side of the second side pixel circuit, which is far away from the first display area; at least one of the first gate driving circuit and the second gate driving circuit is used for driving a first side pixel circuit and a second side pixel circuit of the first pixel circuit in the same row, respectively.
2. The array substrate of claim 1, wherein the gate driving circuit further comprises a third gate driving circuit and a fourth gate driving circuit; the second display area is also provided with a second pixel circuit; the third gate driving circuit and the fourth gate driving circuit drive the second pixel circuit;
Along a first direction, at least part of the gate driving circuit has a length smaller than that of the first pixel circuit; wherein the first direction is a column direction of the first pixel circuit.
3. The array substrate of claim 2, wherein the first gate driving circuit and the third gate driving circuit are disposed on the same side of the second display region, and the second gate driving circuit and the fourth gate driving circuit are disposed on the same side of the second display region; along the first direction, at least one first gate driving circuit is arranged between the third gate driving circuits, and/or at least one second gate driving circuit is arranged between the fourth gate driving circuits.
4. The array substrate of claim 1, further comprising an impedance compensation unit;
the first grid driving circuit is connected with the first side pixel circuit through the impedance compensation unit, and/or the second grid driving circuit is connected with the second side pixel circuit through the impedance compensation unit; the impedance compensation unit is used for compensating the impedance of the first pixel circuit.
5. The array substrate according to claim 4, wherein when the first pixel circuit includes transistors of different types, the gate driving circuit further includes a fifth gate driving circuit and a sixth gate driving circuit; the fifth gate driving circuit and the first gate driving circuit are arranged on the same side of the second display area, the sixth gate driving circuit and the second gate driving circuit are arranged on the same side of the second display area, the level of a gate driving signal provided by the fifth gate driving circuit is opposite to the level of a gate driving signal provided by the first gate driving circuit, and the level of a gate driving signal provided by the sixth gate driving circuit is opposite to the level of a gate driving signal provided by the second gate driving circuit; the fifth gate driving circuit and the sixth gate driving circuit are used for driving the first pixel circuit;
along a first direction, at least part of the length of the fifth gate driving circuit is smaller than the length of the first pixel circuit, and the impedance compensation unit and the fifth gate driving circuit are arranged in the same column; and/or at least part of the length of the sixth gate driving circuit is smaller than the length of the first pixel circuit, and the impedance compensation unit and the sixth gate driving circuit are arranged in the same column; wherein the first direction is a column direction of the first pixel circuit.
6. The array substrate of claim 4 or 5, wherein the impedance compensation unit comprises a resistance-capacitance compensation circuit.
7. The array substrate of any one of claims 1-5, wherein the circuit topologies of the first gate driving circuit and the second gate driving circuit are identical.
8. The array substrate of claim 7, wherein the first gate driving circuit comprises at least one of a scan circuit and a light emission control circuit.
9. The array substrate of claim 8, wherein when the gate driving circuit further includes a fifth gate driving circuit and a sixth gate driving circuit, the first gate driving circuit and the second gate driving circuit include a first scanning circuit, the fifth gate driving circuit and the sixth gate driving circuit include a second scanning circuit, and an effective level of a first scanning signal provided by the first scanning circuit is opposite to an effective level of a second scanning signal provided by the second scanning circuit.
10. A display panel comprising the array substrate of any one of claims 1-9.
CN202310484540.0A 2023-04-27 2023-04-27 Array substrate and display panel Pending CN116504166A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310484540.0A CN116504166A (en) 2023-04-27 2023-04-27 Array substrate and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310484540.0A CN116504166A (en) 2023-04-27 2023-04-27 Array substrate and display panel

Publications (1)

Publication Number Publication Date
CN116504166A true CN116504166A (en) 2023-07-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310484540.0A Pending CN116504166A (en) 2023-04-27 2023-04-27 Array substrate and display panel

Country Status (1)

Country Link
CN (1) CN116504166A (en)

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