CN116490004A - Lanthanum titanate ferroelectric memristor array with novel structure and preparation method thereof - Google Patents
Lanthanum titanate ferroelectric memristor array with novel structure and preparation method thereof Download PDFInfo
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- CN116490004A CN116490004A CN202310395009.6A CN202310395009A CN116490004A CN 116490004 A CN116490004 A CN 116490004A CN 202310395009 A CN202310395009 A CN 202310395009A CN 116490004 A CN116490004 A CN 116490004A
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 229910052746 lanthanum Inorganic materials 0.000 title claims abstract description 48
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052709 silver Inorganic materials 0.000 claims abstract description 10
- 239000004332 silver Substances 0.000 claims abstract description 10
- 238000004544 sputter deposition Methods 0.000 claims description 45
- 239000010408 film Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008859 change Effects 0.000 abstract description 13
- 238000004364 calculation method Methods 0.000 abstract description 4
- 210000005036 nerve Anatomy 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 10
- 239000000956 alloy Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000001351 cycling effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000946 synaptic effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000003592 biomimetic effect Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 210000002569 neuron Anatomy 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a lanthanum titanate ferroelectric memristor with a novel structure and a preparation method thereof, and the lanthanum titanate ferroelectric memristor is characterized by comprising a plurality of Pt bottom electrode layers which are parallel to each other and provided with gaps, wherein a resistance change layer is arranged on the second electrode layer, the resistance change layer is a dielectric layer positioned on the second electrode layer, the dielectric layer is a lanthanum titanate film with the thickness of 40nm and a silver film with the total thickness of 1.37nm, a plurality of Ag top electrode layers which are parallel to each other and provided with gaps are arranged on the dielectric layer, and the top electrode layers and the bottom electrode layers are distributed in a crossing way. According to the invention, the on-off ratio of the lanthanum titanate ferroelectric memristor is improved through the increase of the thickness of the dielectric layer and the doping of Ag atoms, so that the power consumption of the device is greatly reduced, and the device meets the power consumption requirement of nerve morphology calculation.
Description
Technical Field
The invention relates to a lanthanum titanate ferroelectric memristor with a novel structure and a preparation method thereof, belonging to the technical field of ferroelectric storage.
Background
As moore's law approaches tail sounds, it is desirable to find new microelectronic devices based on new materials or structures to replace traditional logic devices and use the devices to build brain-like computing systems, thereby breaking von neumann bottlenecks. In this case, memristors have become one of the powerful candidates due to their low power consumption, high integration density, great application potential in data storage, and excellent synaptic biomimetic properties. However, the conventional oxide memristor has the defects of low switch ratio, large turn-on voltage, poor stability and the like, and the development of the conventional oxide memristor still faces a plurality of difficulties. The resistance change characteristics of the ferroelectric memristor are derived from the change of the ferroelectric material potential barrier, and the ferroelectric memristor has higher reliability compared with the conventional oxidation memristor by virtue of the unique resistance change characteristics.
According to the invention, the ferroelectric memristor based on lanthanum titanate is improved in structure, so that the switching ratio of the lanthanum titanate ferroelectric memristor is increased, the switching voltage of the device is reduced, the device has better non-easy storage characteristic, and the power consumption requirement of nerve morphology calculation is met.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a lanthanum titanate ferroelectric memristor with a novel structure and a preparation method thereof.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
the invention provides a lanthanum titanate ferroelectric memristor array with a novel structure, which is characterized by comprising a plurality of bottom electrode layers which are parallel to each other and provided with gaps, wherein a dielectric layer is arranged on the second electrode layer, the dielectric layer is a lanthanum titanate film with the thickness of 40nm and a silver film with the total thickness of 1.37nm, a plurality of top electrode layers which are parallel to each other and provided with gaps are arranged on the dielectric layer, and the top electrode layers and the bottom electrode layers are distributed in a crossing way.
As a preferred embodiment, a plurality of the top electrode layers and the bottom electrode layers are vertically arranged.
As a preferred embodiment, the dielectric layer and the second electrode layer are uniform in shape and size.
As a preferred embodiment, the dielectric layer has a thickness of 40nm of lanthanum titanate film and 1.37nm of silver film.
As a preferred embodiment, the first electrode layer is an Ag thin film having a thickness of 100nm, and the bottom electrode is a Pt thin film having a thickness of 100nm.
In a second aspect, the invention provides a preparation method of a lanthanum titanate ferroelectric memristor array with a novel structure, which is characterized by comprising the following steps:
step S1, arranging a first mask on a dried substrate, and sputtering and depositing a bottom electrode layer material Pt serving as a first sputtering source on the upper surface of the substrate in a vacuum environment to prepare a Pt bottom electrode layer;
s2, taking down the first mask, covering a second mask through an alignment mark, taking lanthanum titanate as a second sputtering source, taking a top electrode layer material Ag as a third sputtering source, firstly opening the second sputtering source to sputter a lanthanum titanate film, opening the third sputtering source when the lanthanum titanate film is sputtered to half, simultaneously sputtering the second sputtering source and the third sputtering source for 10 seconds, closing the third sputtering source, and continuing to sputter by the second sputtering source until the second sputtering source is finished, so as to obtain a medium layer of the lanthanum titanate film with the thickness of 40nm and the silver film with the total thickness of 1.37 nm.
And S3, setting a third mask above the dielectric layer, selecting an Ag material as a third sputtering source, and sputtering a first electrode layer material to the dielectric layer to obtain a top electrode Ag layer, thereby obtaining the lanthanum titanate ferroelectric memristor array with the novel structure.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention provides a lanthanum titanate ferroelectric memristor array with a novel structure, which is characterized by comprising a plurality of Pt bottom electrode layers which are parallel to each other and provided with gaps, wherein a resistive layer is arranged on the second electrode layer, the resistive layer is a dielectric layer positioned on the second electrode layer, the dielectric layer is a lanthanum titanate film with the thickness of 40nm and a silver film with the total thickness of 1.37nm, a plurality of Ag top electrode layers which are parallel to each other and provided with gaps are arranged on the dielectric layer, and the top electrode layers and the bottom electrode layers are distributed in a crossing way. According to the invention, the on-off ratio of the lanthanum titanate ferroelectric memristor is improved through the increase of the thickness of the dielectric layer and the doping of Ag atoms, so that the power consumption of the device is greatly reduced, and the device meets the power consumption requirement of nerve morphology calculation.
2. The preparation method of the lanthanum titanate ferroelectric memristor array with the novel structure provided by the invention can be used for preparing the lanthanum titanate ferroelectric memristor array with the novel structure, is simple and efficient, has low cost, and is suitable for industrial popularization and use.
Drawings
FIG. 1 shows a Ag/La-based alloy according to an embodiment of the present invention 2 Ti 2 O 7 -structural schematic of a novel ferroelectric memristor array of Ag/Pt.
FIG. 2 shows a Ag/La-based alloy according to a second embodiment of the present invention 2 Ti 2 O 7 -a preparation flow chart of a novel ferroelectric memristor array of Ag/Pt.
FIG. 3 shows a Ag/La-based alloy according to a second embodiment of the present invention 2 Ti 2 O 7 -I-V cycling characteristics of a novel ferroelectric memristor array of Ag/Pt at 100nA limit.
FIG. 4 shows a Ag/La-based alloy according to a second embodiment of the present invention 2 Ti 2 O 7 Novel ferroelectric memristor array of-Ag/Pt at 5×10 -3 I-V characteristic curve under A limit.
FIG. 5 shows a Ag/La-based alloy according to a second embodiment of the present invention 2 Ti 2 O 7 -a characteristic curve of a transition of a new ferroelectric memristor array of Ag/Pt from a threshold switching characteristic to a resistive switching characteristic.
FIG. 6 shows a Ag/La-based alloy according to a second embodiment of the present invention 2 Ti 2 O 7 -a long graph of resistance retention characteristics of a novel ferroelectric memristor array of Ag/Pt at a voltage of 0.01V.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
Embodiment one:
the invention provides a lanthanum titanate ferroelectric memristor array with a novel structure, referring to fig. 1, the lanthanum titanate ferroelectric memristor array comprises a plurality of bottom electrode Pt layers which are parallel to each other and provided with gaps, a dielectric layer is arranged on the bottom electrode layers, the dielectric layer comprises a lanthanum titanate film with the thickness of 40nm and a silver film with the total thickness of 1.37nm, a plurality of top electrode Ag layers which are parallel to each other and provided with gaps are arranged on the dielectric layer, and the top electrode layers and the bottom electrode layers are distributed in a crossed manner. Through arranging the first electrode layer and the second electrode layer in a multi-group crossing way, compared with a single device, the device has smaller characteristic size, the switching characteristic and the stability of the device can be obviously improved, the lanthanum titanate ferroelectric memristor with the novel structure can be better applied to non-easy storage, the synaptic weight of a neural network can be replaced, and the storage density and the application range of the ferroelectric memory are greatly increased.
The person skilled in the art can set a plurality of top electrode layers and bottom electrode layers in a vertical state, or set the top electrode layers and the bottom electrode layers in an angle of 45 degrees, and the specific setting angle can be set according to actual needs.
Preferably, the shapes and the sizes of the dielectric layer and the bottom electrode layer are matched one by one, for example, the shape of the bottom electrode layer of the dielectric layer is rectangular. The thickness of the dielectric layer is 41.37nm, that is, the total thickness of lanthanum titanate and Ag is 41.37nm, but is not limited thereto. The dielectric layer is a ferroelectric material dielectric layer and is prepared by a PVD method.
The thickness of the Ag layer of the top electrode is 100nm, and the thickness of the Pt layer of the bottom electrode is 100nm.
The top electrode Ag and the bottom electrode Pt are used for being electrically connected with an external power supply, and the top electrode Ag and the bottom electrode Pt are prepared through a PVD (physical vapor deposition) method.
Embodiment two:
for easy understanding, the implementation provides a method based on Ag/La 2 Ti 2 O 7 A method for preparing a novel ferroelectric memristor array of Ag/Pt, please refer to fig. 2, specifically comprising the steps of:
step S1, arranging a first mask on a dried silicon substrate, fixing the silicon substrate on a target gun of a sputtering system in a vacuum environment, selecting a Pt material as a first sputtering source, and sputtering and depositing the first sputtering source on the upper surface of the silicon substrate through a magnetron sputtering instrument so as to uniformly and completely cover the first sputtering source on the upper surface of the silicon substrate to prepare a Pt electrode;
s2, taking down the first mask, covering a second mask through an alignment mark, taking lanthanum titanate as a second sputtering source, taking a top electrode layer material Ag as a third sputtering source, firstly opening the second sputtering source to sputter a lanthanum titanate film, opening the third sputtering source when the lanthanum titanate film is sputtered to half, simultaneously sputtering the second sputtering source and the third sputtering source for 10 seconds, closing the third sputtering source, and continuing to sputter by the second sputtering source until the second sputtering source is finished to obtain a medium layer of the lanthanum titanate film with the thickness of 40nm and the silver film with the total thickness of 1.37 nm;
and S3, setting a third mask above the dielectric layer, selecting an Ag material as a third sputtering source, and sputtering a first electrode layer material to the dielectric layer to obtain a top electrode Ag layer, thereby obtaining the lanthanum titanate ferroelectric memristor array with the novel structure.
FIG. 3 is a diagram showing a Ag/La-based structure according to a second embodiment 2 Ti 2 O 7 Typical I-V cycling profile of a new ferroelectric memristor array unipolar resistive properties of Ag/Pt, with voltage on the abscissa and current on the ordinate, current limiting at 100nA. The voltage is scanned from 0V to 0.3V, and when the voltage is not yet 0.3V, the voltage is about 0.15V based on Ag/La 2 Ti 2 O 7 The new ferroelectric memristor of Ag/Pt undergoes the SET process, the device changes from high resistance state to low resistance state and remains until the positive voltage scan ends, but when the negative voltage scans from 0V to 0.3V, the device has initially returned to the high resistance state, exhibiting unipolar resistive characteristics, and subsequently, for verifying stability, 100 cycles of this test are performed, and it can be seen that the turn-on voltage in fig. 3 is about 0.15V each time, and the I-V curves are substantially identical each time. It can be seen that based on Ag/La 2 Ti 2 O 7 The novel ferroelectric memristor array of Ag/Pt shows ultra-low power consumption and stable unipolar resistance change characteristics under the condition of small current limit, and marks the hardware requirement of the lanthanum titanate memristor with a novel structure on nerve state calculation.
FIG. 4 is a diagram showing a Ag/La-based structure according to a second embodiment 2 Ti 2 O 7 Typical of the bipolar resistance characteristics of a novel ferroelectric memristor array of Ag/PtType I-V graph, wherein the abscissa is voltage, the ordinate is current, and the current limit is 5×10 -3 A. The voltage is scanned from 0V to 1V, and when the voltage is scanned to be less than 1V, the voltage is approximately 0.5V, based on Ag/La 2 Ti 2 O 7 The novel ferroelectric memristor of Ag/Pt generates a SET process, the device changes from a high resistance state to a low resistance state, the stable resistance value is kept all the time, a RSET process is generated in the process of scanning the voltage from 0V to-1V, the high resistance state is returned, the stable resistance value can be kept, and the switching voltage of the device is as low as 0.5V and-0.6V.
FIG. 5 shows the Ag/La based current limiting of the present invention 2 Ti 2 O 7 -SET process graph of novel ferroelectric memristor array of Ag/Pt, with increasing current limit, starting voltage of SET process gradually becomes smaller, resistance change characteristic of device is changed from initial threshold switching to resistance change switching, indicating that based on Ag/La 2 Ti 2 O 7 The novel ferroelectric memristor of Ag/Pt can change the resistance change characteristic under continuous regulation and control of continuous current, so that more application requirements are met.
FIG. 6 is based on Ag/La 2 Ti 2 O 7 Novel ferroelectric memristor array of Ag/Pt is maintained for a period of time in a high-resistance state and a low-resistance state, and when the ferroelectric memristor is under the action of a smaller voltage, the novel ferroelectric memristor array is based on Ag/La 2 Ti 2 O 7 Low resistance state resistance of novel ferroelectric memristors of Ag/Pt (about 10 2 Ω) may last more than 1000 seconds, a high resistance state resistance value (about 10 10 Ω) may also last more than 1000 seconds and the duration may be further extended. Wherein, the abscissa is time, and the ordinate is resistance. As can be seen from FIGS. 3 to 6, the present invention is based on Ag/La 2 Ti 2 O 7 The novel ferroelectric memristor of Ag/Pt has both unipolar resistance change characteristics and bipolar resistance change characteristics, can be regulated and controlled through current limiting, has very low power consumption under both characteristics, and has good resistance state retention characteristics under the bipolar resistance change characteristics. The high resistance state shown in FIG. 7 is about 10 10 Omega, low resistance state resistance value of about 10 2 Omega, on-off ratio of 10 8 That is, the invention is based on Ag/La 2 Ti 2 O 7 Novel ferroelectric memory of Ag/PtThe resistor has good switching characteristics.
In summary, the invention is based on Ag/La 2 Ti 2 O 7 The novel ferroelectric memristor of Ag/Pt has ultralow power consumption, good stability and huge on-off ratio, can be used for non-easy storage, simulates neurons of human brain, and has broad prospect. In addition, the preparation method of the invention is simple, efficient and low in cost, and is suitable for industrial popularization and application.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (6)
1. The utility model provides a novel lanthanum titanate ferroelectric memristor array of structure, its characterized in that includes a plurality of bottom electrode layers that are parallel to each other and are equipped with the clearance, be equipped with the dielectric layer on the second electrode layer, the dielectric layer is 40nm thick lanthanum titanate film and 1.37nm total thickness's silver film, be equipped with a plurality of top electrode layers that are parallel to each other and are equipped with the clearance on the dielectric layer, alternately lay between top electrode layer and the bottom electrode layer.
2. The novel structured lanthanum titanate ferroelectric memristor array of claim 1, wherein a plurality of the top electrode layers and the bottom electrode layers are vertically arranged.
3. The novel structured lanthanum ferroelectric titanate memristor array of claim 1, wherein the dielectric layer and bottom electrode layer are uniform in shape and size.
4. The novel structured lanthanum titanate ferroelectric memristor array according to claim 1, wherein the dielectric layer is a 40nm thick lanthanum titanate film and a 1.37nm total thickness silver film.
5. The novel structure of lanthanum titanate ferroelectric memristor according to claim 1, wherein the top electrode layer is an Ag thin film with a thickness of 100nm, and the bottom electrode layer is a Pt thin film with a thickness of 100nm.
6. The preparation method of the lanthanum titanate ferroelectric memristor array with the novel structure is characterized by comprising the following steps of:
step S1, arranging a first mask on a dried silicon substrate, and sputtering and depositing a bottom electrode layer material Pt serving as a first sputtering source on the upper surface of the substrate in a vacuum environment to prepare a Pt bottom electrode layer;
s2, taking down the first mask, covering a second mask through an alignment mark, taking lanthanum titanate as a second sputtering source, taking a top electrode layer material Ag as a third sputtering source, firstly opening the second sputtering source to sputter a lanthanum titanate film, opening the third sputtering source when the lanthanum titanate film is sputtered to half, simultaneously sputtering the second sputtering source and the third sputtering source for 10 seconds, closing the third sputtering source, and continuing to sputter by the second sputtering source until the second sputtering source is finished, so as to obtain a medium layer of the lanthanum titanate film with the thickness of 40nm and the silver film with the total thickness of 1.37 nm.
And S3, setting a third mask above the dielectric layer, selecting an Ag material as a third sputtering source, and sputtering a first electrode layer material to the dielectric layer to obtain a top electrode Ag layer, thereby obtaining the lanthanum titanate ferroelectric memristor array with the novel structure.
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