CN116487340A - Heterogeneous integrated gallium oxide field effect transistor with micro-channel and preparation method thereof - Google Patents
Heterogeneous integrated gallium oxide field effect transistor with micro-channel and preparation method thereof Download PDFInfo
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- CN116487340A CN116487340A CN202310474680.XA CN202310474680A CN116487340A CN 116487340 A CN116487340 A CN 116487340A CN 202310474680 A CN202310474680 A CN 202310474680A CN 116487340 A CN116487340 A CN 116487340A
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- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 157
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 156
- 230000005669 field effect Effects 0.000 title claims abstract description 35
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000002826 coolant Substances 0.000 claims abstract description 24
- 238000012546 transfer Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 118
- 238000000034 method Methods 0.000 claims description 54
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000009623 Bosch process Methods 0.000 claims description 7
- 238000000227 grinding Methods 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 238000000608 laser ablation Methods 0.000 claims description 4
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 238000009616 inductively coupled plasma Methods 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 10
- 238000001816 cooling Methods 0.000 abstract description 4
- 238000005265 energy consumption Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 10
- 238000005498 polishing Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241001354791 Baliga Species 0.000 description 1
- 241000252506 Characiformes Species 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention provides a heterogeneous integrated gallium oxide field effect transistor with a micro-channel and a preparation method thereof, wherein an embedded micro-channel is directly prepared in a gallium oxide heterogeneous integrated structure, so that a cooling medium directly flows close to a heat source, thereby realizing efficient heat dissipation, reducing the channel temperature of the field effect transistor and optimizing the thermal performance of a device. The gallium oxide field effect transistor based on embedded micro-channels and heterogeneous integration has the advantages of compact structure, high heat transfer efficiency, low energy consumption of a cooling system and the like.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a heterogeneous integrated gallium oxide field effect transistor with a micro-channel and a preparation method thereof.
Background
Gallium oxide, which is a fourth generation semiconductor material, has a wider band gap, higher critical breakdown field strength, larger Baliga figure of merit, and lower manufacturing cost than silicon carbide and gallium nitride, and is a preferred material for manufacturing power devices. However, because the thermal conductivity of gallium oxide is low, the gallium oxide-based power device can generate reliability problem due to the excessively high temperature, so that the output power of the device is reduced, and the development of the gallium oxide-based power device is limited by the heat dissipation problem, so that the industry puts higher demands on the thermal management of the gallium oxide-based power device.
In the prior art, when preparing a gallium oxide-based power device, gallium oxide is generally combined with a high heat conduction substrate by utilizing a heterogeneous integration method, and a gallium oxide layer is thinned as much as possible on the basis, so that the heat transfer distance from a heat source to the substrate is shortened, and meanwhile, the interface thermal resistance of the gallium oxide and the substrate material is reduced by optimizing a process, however, the heat dissipation efficiency by means of a heat conduction mode is still limited, and the heat dissipation requirement of the device under a higher power density is difficult to meet.
Therefore, it is necessary to provide a hetero-integrated gallium oxide field effect transistor with a micro-channel and a preparation method thereof.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a hetero-integrated gallium oxide field effect transistor with a micro-channel and a manufacturing method thereof, which are used for solving the heat dissipation problem of the gallium oxide field effect transistor in the prior art.
In order to achieve the above object, the present invention provides a method for manufacturing a hetero-integrated gallium oxide field effect transistor having a micro flow channel, comprising the steps of:
providing a gallium oxide substrate and a support substrate, and bonding the gallium oxide substrate and the support substrate to prepare a gallium oxide heterogeneous integrated structure comprising a gallium oxide layer and the support substrate;
patterning the gallium oxide heterogeneous integrated structure to form a slit which penetrates through the gallium oxide layer and the bottom of which is positioned in the support substrate;
etching the support substrate based on the slit to form a first groove with a first width penetrating through the gallium oxide layer and a second groove with a second width, wherein the second groove is positioned in the support substrate and is larger than the first width;
etching the support substrate to form a third groove with a cooling medium inlet and outlet in the support substrate, wherein the third groove is communicated with the second groove;
forming metal electrodes which are arranged at intervals on the gallium oxide layer, wherein the metal electrodes seal the first grooves;
and forming a gate structure positioned on the gallium oxide layer between the metal electrodes.
Optionally, the method for preparing the gallium oxide hetero-integrated structure comprises a bonding grinding method or a smart-cut transfer method.
Optionally, the support substrate includes a Si substrate, a SiC substrate, an AlN substrate, or a diamond substrate.
Optionally, before bonding, the gallium oxide substrate and/or the surface of the support substrate has an insulating layer, and the insulating layer includes a silicon oxide layer.
Optionally, the method for preparing the slit comprises an etching method or a laser ablation method, wherein the step of preparing the slit by the etching method comprises the following steps:
forming a hard mask on the surface of the gallium oxide layer;
forming patterned photoresist on the hard mask, and etching the hard mask by adopting inductively coupled plasma so as to pattern the hard mask;
removing the photoresist, and etching the gallium oxide layer to expose the support substrate;
and etching the supporting substrate by adopting a Bosch process to form the slit.
Optionally, the method further comprises the step of forming ohmic contact between the gallium oxide layer and the metal electrode; the method of forming the metal electrode includes an electroplating method.
Optionally, the cooling medium comprises a liquid cooling medium or a gaseous cooling medium.
Optionally, the method of etching the support substrate based on the slit includes an isotropic etching method; the method of forming the third trench in the support substrate includes a Bosch process.
The invention also provides a heterogeneous integrated gallium oxide field effect transistor with a micro-channel, comprising:
the gallium oxide heterogeneous integrated structure comprises a support substrate and a gallium oxide layer positioned on the support substrate, wherein a first groove with a first width penetrating through the gallium oxide layer is formed in the gallium oxide layer, a second groove with a second width and a third groove with a cooling medium inlet and outlet are formed in the support substrate, the second width is larger than the first width, and the second groove is connected with the first groove and the third groove;
the metal electrodes are arranged at intervals and positioned on the gallium oxide layer, and seal the first grooves;
and the grid structure is positioned on the gallium oxide layer and between the metal electrodes.
Optionally, the second grooves include crisscrossed mesh grooves or stripe grooves.
As described above, according to the heterogeneous integrated gallium oxide field effect transistor with the micro-channel and the preparation method thereof, the embedded micro-channel is directly prepared in the gallium oxide heterogeneous integrated structure, so that a cooling medium directly flows close to a heat source, high-efficiency heat dissipation is realized, the channel temperature of the field effect transistor is reduced, and the thermal performance of a device is optimized. The gallium oxide field effect transistor based on embedded micro-channels and heterogeneous integration has the advantages of compact structure, high heat transfer efficiency, low energy consumption of a cooling system and the like.
Drawings
Fig. 1 is a schematic process flow diagram of a hetero-integrated gallium oxide field effect transistor with a micro-channel according to an embodiment.
Fig. 2 is a schematic diagram of a structure obtained after bonding a gallium oxide substrate and a support substrate when a gallium oxide hetero-integrated structure is manufactured by using a bonding grinding method in the embodiment.
Fig. 3 is a schematic structural diagram of a gallium oxide hetero-integrated structure obtained after polishing when the gallium oxide hetero-integrated structure is prepared by a bonding polishing method in the embodiment.
Fig. 4 is a schematic structural diagram of a gallium oxide substrate after forming a defect layer in the gallium oxide substrate when the gallium oxide hetero-integrated structure is prepared by using the smart cut transfer method in the embodiment.
Fig. 5 is a schematic diagram of a structure obtained after bonding a gallium oxide substrate and a support substrate when a gallium oxide hetero-integrated structure is prepared by using an intelligent lift-off transfer method in the embodiment.
Fig. 6 is a schematic structural diagram of a gallium oxide hetero-integrated structure obtained after lift-off and grinding when the gallium oxide hetero-integrated structure is prepared by an intelligent lift-off transfer method in the embodiment.
FIG. 7 is a schematic diagram showing a structure after forming a hard mask in an embodiment
FIG. 8 is a schematic diagram of a structure after forming a patterned hard mask in an embodiment.
Fig. 9 is a schematic view showing a structure after forming the slit in the embodiment.
Fig. 10 is a schematic structural diagram of the first trench and the second trench formed in the embodiment.
Fig. 11 is a schematic diagram of a structure after removing the hard mask in the embodiment.
Fig. 12 is a schematic view showing a structure after ohmic contact is formed in the embodiment.
Fig. 13 is a schematic structural view of the third trench formed in the embodiment.
Fig. 14 is a schematic diagram of a structure after forming a seed layer in an embodiment.
Fig. 15 is a schematic diagram of a structure after patterning photoresist in an embodiment.
Fig. 16 is a schematic view showing a structure after forming a metal electrode in the embodiment.
Fig. 17 is a schematic diagram of the structure after photoresist removal in the embodiment.
Fig. 18 is a schematic diagram of a structure after patterning a seed layer according to an embodiment.
Fig. 19 is a schematic diagram of a structure after forming a gate structure in an embodiment.
Fig. 20 is a schematic view showing a partial perspective structure of a hetero-integrated gallium oxide field effect transistor having a micro flow channel formed in the embodiment.
Description of element reference numerals
100-supporting a substrate; a 200-gallium oxide substrate; 200 a-injection plane; 201-a defect layer; 210-a gallium oxide layer; 300-hard mask; 400-slit; 510-a first trench; 520-a second trench; 530-a third trench; 600-ohm contact; 700-seed layer; 800-photoresist; 900-metal electrode; 110-gate structure; 111-gate dielectric layer; 112-gate.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures, including embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact, and further, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a method for preparing a hetero-integrated gallium oxide field effect transistor with a micro-channel, which includes the following steps:
s1: providing a gallium oxide substrate and a support substrate, and bonding the gallium oxide substrate and the support substrate to prepare a gallium oxide heterogeneous integrated structure comprising a gallium oxide layer and the support substrate;
s2: patterning the gallium oxide heterogeneous integrated structure to form a slit which penetrates through the gallium oxide layer and the bottom of which is positioned in the support substrate;
s3: etching the support substrate based on the slit to form a first groove with a first width penetrating through the gallium oxide layer and a second groove with a second width, wherein the second groove is positioned in the support substrate and is larger than the first width;
s4: etching the support substrate to form a third groove with a cooling medium inlet and outlet in the support substrate, wherein the third groove is communicated with the second groove;
s5: forming metal electrodes which are arranged at intervals on the gallium oxide layer, wherein the metal electrodes seal the first grooves;
s6: and forming a gate structure positioned on the gallium oxide layer between the metal electrodes.
According to the embodiment, the embedded micro-channel is directly prepared in the gallium oxide heterogeneous integrated structure, so that a cooling medium directly flows close to a heat source, efficient heat dissipation is achieved, the channel temperature of the heterogeneous integrated gallium oxide field effect transistor is reduced, the thermal performance of a device is optimized, and the heterogeneous integrated gallium oxide field effect transistor has the advantages of being compact in structure, high in heat transfer efficiency, low in energy consumption of a cooling system and the like.
The following description is presented with reference to fig. 2 to 20, which specifically includes:
first, referring to fig. 2 to 6, step S1 is performed to provide a gallium oxide substrate 200 and a support substrate 100, and the gallium oxide substrate 200 and the support substrate 100 are bonded to prepare a gallium oxide hetero-integrated structure including a gallium oxide layer 210 and the support substrate 100.
As an example, the method of preparing the gallium oxide hetero-integrated structure may include a bond grinding method or a smart-cut transfer method.
Specifically, referring to fig. 2 to 3, when the bonding grinding method is used to prepare the gallium oxide hetero-integrated structure, the method may include the following steps:
as shown in fig. 2, the gallium oxide substrate 200 and the support substrate 100 are provided, and the gallium oxide substrate 200 is bonded to the support substrate 100;
as shown in fig. 3, the gallium oxide substrate 200 is polished to form the gallium oxide layer 210 on the support substrate 100, thereby obtaining the gallium oxide hetero-integrated structure.
Referring to fig. 4 to 6, when the intelligent lift-off transfer method is used to prepare the gallium oxide hetero-integrated structure, the method may include the following steps:
as shown in fig. 4, the gallium oxide substrate 200 and the support substrate 100 are provided, and a defect ion implantation, such as implantation H, he plasma, is performed in the gallium oxide substrate 200 to form a defect layer 201 in the gallium oxide substrate 200;
as shown in fig. 5, the implantation surface 200a of the gallium oxide substrate 200 is bonded to the support substrate 100;
as shown in fig. 6, annealing and stripping are performed, a part of the gallium oxide substrate 200 is stripped and removed from the defect layer 201, and grinding is performed, so as to form the gallium oxide layer 210 on the support substrate 100, thereby obtaining the gallium oxide hetero-integrated structure.
The polishing method may include one or a combination of mechanical polishing and CMP polishing, and the thickness of the gallium oxide layer 210 is preferably 0.01 to 10 μm, such as 0.01 μm, 0.1 μm, 1 μm, 5 μm, 10 μm, etc., after polishing, and may be specifically selected according to the need.
As an example, the support substrate 100 may include a Si substrate, a SiC substrate, an AlN substrate, or a diamond substrate to provide a support substrate having high heat conductive properties for improving the overall heat dissipation capability of the device. The supporting substrate 100 may have a wafer-level size, such as 6 inches, 8 inches, 12 inches, etc., and the material and size of the supporting substrate 100 are not limited herein.
As an example, the gallium oxide substrate 200 and/or the surface of the support substrate 100 may further have an insulating layer (not shown) before bonding, wherein the insulating layer may include a silicon oxide layer.
Specifically, the insulating layer may be formed on one or a combination of the surface of the support substrate 100 and the surface of the gallium oxide substrate 200 before bonding, so that the insulating layer having a good insulating effect, such as a silicon oxide layer, may be formed between the gallium oxide layer 210 and the support substrate 100 after bonding to achieve electrical isolation between subsequent devices through the insulating layer. The material of the insulating layer is not limited to silicon oxide, and dielectric layers of other materials may be used, which is not limited herein.
Next, referring to fig. 7 to 9, step S2 is performed to pattern the gallium oxide hetero-integrated structure to form a slit 400 penetrating the gallium oxide layer 210 and having a bottom located in the support substrate 100.
As an example, the method of preparing the slit 400 may include an etching method or a laser ablation method.
Referring to fig. 7 to 9, in this embodiment, the slit 400 is prepared by etching, and the steps may include:
referring to fig. 7, a hard mask 300 is formed on the surface of the gallium oxide layer 210;
referring to fig. 8, a patterned photoresist (not shown) is formed on the hard mask 300, and the hard mask 300 is etched using inductively coupled plasma to pattern the hard mask 300;
removing the photoresist, and etching the gallium oxide layer 210 to expose the support substrate 100;
as shown in fig. 9, the support substrate 100 is etched using a Bosch process to form the slit 400.
In the present embodiment, a silicon oxide hard mask is formed on the surface of the gallium oxide layer 210 by plasma enhanced chemical vapor deposition as the hard mask 300, but the kind and preparation method of the hard mask 300 are not limited thereto. The formed slit 400 may include criss-cross mesh slits or strip slits, and the specific shape may be selected according to the need, so as to prepare the slit 400 having a certain length and being arranged at intervals, so as to facilitate the preparation of the subsequent micro-channels. After stripping the photoresist, the gallium oxide layer 210 may be etched using a chemical method, such as dry etching, until the support substrate 100 is exposed, which may be tested by endpoint detection. After etching the support substrate 100 using the Bosch process, the slit 400 may be further deepened, thereby preparing the slit 400 having a high aspect ratio.
Of course, in another embodiment, the slit 400 may also be prepared by laser ablation, and the steps may include:
cutting the gallium oxide heterogeneous integrated structure by using a laser to generate high-energy laser, and repeating the above processes to obtain the slit 400 with the required shape;
and cleaning the gallium oxide hetero-integrated structure by acid to remove residues in the slit 400, thereby completing the preparation of the slit 400.
Regarding the specific method and steps for forming the slit 400, the adaptation may be performed as needed, and is not excessively limited herein.
Referring to fig. 10 and 11, step S3 is performed to etch the support substrate 100 based on the slit 400, forming a first trench 510 having a first width penetrating the gallium oxide layer 210, and a second trench 520 having a second width in the support substrate 100, wherein the second width is greater than the first width.
As an example, the method of etching the support substrate 100 based on the slit 400 may include an isotropic etching method.
As shown in fig. 10, in the present embodiment, the slit 400 in the support substrate 100 is widened by using isotropic gas etching, and after repeating the etching process for several cycles, the first trench 510 having the first width penetrating the gallium oxide layer 210 and the second trench 520 having the second width in the support substrate 100 are obtained. Wherein a camera mounted directly on the etch chamber can be used to accurately obtain the desired trench width by in-situ photolithography tracking of the gallium oxide layer 210.
After the etching is completed, referring to fig. 11, the silicon oxide hard mask may be stripped using, for example, HF treatment, and may be treated using, for example, a piranha solution to further remove organic residues on the surface, so as to facilitate the subsequent process.
As an example, after removing the hard mask 300, a step of forming an ohmic contact 600 may be further included.
Specifically, referring to fig. 12, the ohmic contact 600 may be formed after the process steps of forming a patterned metal layer and annealing above the gallium oxide layer 210 in order to improve the electrical performance of the hetero-integrated gallium oxide field effect transistor. The material of the ohmic contact 600 is not excessively limited here.
Next, referring to fig. 13, step S4 is performed to etch the support substrate 100, a third trench 530 having a cooling medium inlet and outlet is formed in the support substrate 100, and the third trench 530 is in communication with the second trench 520.
Specifically, a Bosch process may be used to etch a manifold channel including a cooling medium inlet and outlet (not shown) in the support substrate 100 until the manifold channel merges with the second groove 520 to form a micro flow channel system. The etching method of the support substrate 100, the morphology, the size, etc. of the third trench 530 formed are not excessively limited herein.
Next, referring to fig. 14 to 18, step S5 is performed to form metal electrodes 900 disposed at intervals on the gallium oxide layer 210, and the metal electrodes 900 seal the first trenches 510.
As an example, the method of forming the metal electrode 900 may include an electroplating method.
Specifically, referring to fig. 14 to 18, in the present embodiment, the opening of the first trench 510 in the gallium oxide layer 210 is sealed by the metal electrode 900 while the metal electrode 900 is formed on top of the ohmic contact 600 to be applied as a source-drain electrode. The metal electrode 900 is made of copper, but not limited thereto.
The specific steps of forming the metal electrode 900 may include:
referring to fig. 14, a uniform seed layer 700 is deposited, wherein an adhesion layer (not shown) may be deposited prior to depositing the seed layer 700, and for copper materials, a layer of chromium may be deposited as the adhesion layer prior to depositing copper as the seed layer 700.
Referring to fig. 15, a photoresist 800 is coated and the photoresist 800 is patterned to define a region to be plated.
Referring to fig. 16, electroplating is performed to form the metal electrode 900, which includes applying a conductive adhesive to the edge of the structure of fig. 15 to make electrical contact as a cathode, and immersing the prepared structure in, for example, H 2 SO 4 For a certain time to remove surface oxidation products. During electroplating, as the metal electrode 900 grows conformally and isotropically, the opening of the first trench 510 in the gallium oxide layer 210 will seal as metal bridges and coalesces over the opening.
After electroplating, as in fig. 17, the photoresist 800 is stripped, and as in fig. 18, the seed layer 700 is removed by selective etching to reveal the gallium oxide layer 210.
Next, referring to fig. 19, step S5 is performed to form a gate structure 110 on the gallium oxide layer 210 between the metal electrodes 900.
Specifically, the gate structure 110 includes a gate dielectric layer 111 in contact with the gallium oxide layer 210 and a gate 112 on the gate dielectric layer 111, where the gate dielectric layer 111 may include a silicon oxide gate dielectric layer, and the gate 112 may include a polysilicon gate, etc., but the material of the gate structure 110 is not limited thereto, so far, the hetero-integrated gallium oxide field effect transistor based on embedded micro-channels and hetero-integration is formed.
The step of forming the source/drain region by ion implantation in the gallium oxide layer 210 may be further included, and may be specifically selected according to the type of the device to be fabricated, which is not limited herein.
As an example, the cooling medium may include a liquid cooling medium or a gas cooling medium, which may be specifically selected according to needs, and the cooling medium may be led into the embedded micro-channel to flow through the micro-channel, so that the cooling medium is directly close to the heat source, thereby realizing efficient heat dissipation, and reducing the channel temperature of the hetero-integrated gallium oxide field effect transistor, so as to optimize the thermal performance of the device.
Referring to fig. 20, a schematic partial perspective view of the hetero-integrated gallium oxide field-effect transistor with a micro flow channel formed in the present embodiment is illustrated. Wherein the arrow direction indicates the flow direction of the cooling medium.
Referring to fig. 19 and 20, the present embodiment further provides a hetero-integrated gallium oxide field effect transistor having a micro-channel, the hetero-integrated gallium oxide field effect transistor including: gallium oxide hetero-integrated structure, metal electrodes 900 arranged at intervals and a gate structure 110. The gallium oxide hetero-integrated structure comprises a support substrate 100 and a gallium oxide layer 210 positioned on the support substrate 100, wherein a first groove 510 with a first width penetrating through the gallium oxide layer 210 is formed in the gallium oxide layer 210, a second groove 520 with a second width and a third groove 530 with a cooling medium inlet and outlet are formed in the support substrate 100, the second width is larger than the first width, and the second groove 520 is connected with the first groove 510 and the third groove 530; the metal electrode 900 is located on the gallium oxide layer 210, and the metal electrode 900 seals the first trench 510; the gate structure 110 is located on the gallium oxide layer 210 and between the metal electrodes 900, and includes a gate dielectric layer 111 and a gate 112.
The preparation method may be used for the preparation of the hetero-integrated gallium oxide field effect transistor, but is not limited thereto, and in this embodiment, the hetero-integrated gallium oxide field effect transistor is directly prepared by using the preparation process, so that details about the preparation process, structure, material, etc. of the hetero-integrated gallium oxide field effect transistor are not described herein.
As an example, the gallium oxide layer 210 and the metal electrode 900 may also have an ohmic contact 600 therebetween.
As an example, the second trenches 520 may include crisscrossed mesh trenches or stripe trenches, and the shapes of the first trenches 510, the second trenches 520, and the third trenches 530 are not excessively limited herein.
In summary, according to the hetero-integrated gallium oxide field effect transistor with the micro-channel and the preparation method thereof, the embedded micro-channel is directly prepared in the gallium oxide hetero-integrated structure, so that a cooling medium directly flows close to a heat source, efficient heat dissipation is realized, the channel temperature of the field effect transistor is reduced, and the thermal performance of a device is optimized. The gallium oxide field effect transistor based on embedded micro-channels and heterogeneous integration has the advantages of compact structure, high heat transfer efficiency, low energy consumption of a cooling system and the like.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The preparation method of the heterogeneous integrated gallium oxide field effect transistor with the micro-channel is characterized by comprising the following steps of:
providing a gallium oxide substrate and a support substrate, and bonding the gallium oxide substrate and the support substrate to prepare a gallium oxide heterogeneous integrated structure comprising a gallium oxide layer and the support substrate;
patterning the gallium oxide heterogeneous integrated structure to form a slit which penetrates through the gallium oxide layer and the bottom of which is positioned in the support substrate;
etching the support substrate based on the slit to form a first groove with a first width penetrating through the gallium oxide layer and a second groove with a second width, wherein the second groove is positioned in the support substrate and is larger than the first width;
etching the support substrate to form a third groove with a cooling medium inlet and outlet in the support substrate, wherein the third groove is communicated with the second groove;
forming metal electrodes which are arranged at intervals on the gallium oxide layer, wherein the metal electrodes seal the first grooves;
and forming a gate structure positioned on the gallium oxide layer between the metal electrodes.
2. The method of manufacturing according to claim 1, characterized in that: the method for preparing the gallium oxide heterogeneous integrated structure comprises a bonding grinding method or an intelligent stripping transfer method.
3. The method of manufacturing according to claim 1, characterized in that: the support substrate includes a Si substrate, a SiC substrate, an AlN substrate, or a diamond substrate.
4. The method of manufacturing according to claim 1, characterized in that: before bonding, the gallium oxide substrate and/or the surface of the support substrate are provided with an insulating layer, and the insulating layer comprises a silicon oxide layer.
5. The method of manufacturing according to claim 1, characterized in that: the method for preparing the slit comprises an etching method or a laser ablation method, wherein the step of preparing the slit by the etching method comprises the following steps:
forming a hard mask on the surface of the gallium oxide layer;
forming patterned photoresist on the hard mask, and etching the hard mask by adopting inductively coupled plasma so as to pattern the hard mask;
removing the photoresist, and etching the gallium oxide layer to expose the support substrate;
and etching the supporting substrate by adopting a Bosch process to form the slit.
6. The method of manufacturing according to claim 1, characterized in that: further comprising the step of forming an ohmic contact between the gallium oxide layer and the metal electrode; the method of forming the metal electrode includes an electroplating method.
7. The method of manufacturing according to claim 1, characterized in that: the cooling medium includes a liquid cooling medium or a gaseous cooling medium.
8. The method of manufacturing according to claim 1, characterized in that: the method of etching the support substrate based on the slit includes an isotropic etching method; the method of forming the third trench in the support substrate includes a Bosch process.
9. A hetero-integrated gallium oxide field effect transistor having a microchannel, the hetero-integrated gallium oxide field effect transistor comprising:
the gallium oxide heterogeneous integrated structure comprises a support substrate and a gallium oxide layer positioned on the support substrate, wherein a first groove with a first width penetrating through the gallium oxide layer is formed in the gallium oxide layer, a second groove with a second width and a third groove with a cooling medium inlet and outlet are formed in the support substrate, the second width is larger than the first width, and the second groove is connected with the first groove and the third groove;
the metal electrodes are arranged at intervals and positioned on the gallium oxide layer, and seal the first grooves;
and the grid structure is positioned on the gallium oxide layer and between the metal electrodes.
10. The hetero-integrated gallium oxide field effect transistor of claim 9 wherein: the second grooves comprise crisscross net grooves or strip grooves.
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