CN115831877B - Gallium oxide cascades structure based on heterogeneous integration and preparation method - Google Patents
Gallium oxide cascades structure based on heterogeneous integration and preparation method Download PDFInfo
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Abstract
The application provides a gallium oxide cascades structure based on heterogeneous integration and a preparation method thereof, wherein a cascades structure is prepared by integrating a gallium oxide semiconductor material which cannot realize P-type doping with an enhanced device by the heterogeneous integration method, and the cascades structure is prepared on a substrate with high heat dissipation capacity, so that the enhanced cascade power device can be prepared based on the cascades structure, and high heat conduction can be realized, and the problems that gallium oxide cannot prepare normally-closed devices and dissipate heat are solved.
Description
Technical Field
The application belongs to the field of semiconductors, and relates to a gallium oxide cascades structure based on heterogeneous integration and a preparation method thereof.
Background
Gallium oxide (Ga) 2 O 3 ) As an ultra-wide band-gap semiconductor material, the maximum critical breakdown field strength of the ultra-wide band-gap semiconductor material reaches 8MV/cm due to the extremely large band-gap width, and meanwhile, gallium oxide is easy to carry out n-type doping and easy to prepare good ohmic contact, so that a power device prepared based on the ultra-wide band-gap semiconductor material not only has high breakdown voltage, but also has low conduction loss, and therefore, the power conversion efficiency of the device is greatly improved. Gallium oxide power quality factor (PFOM) is 4 times that of gallium nitride (GaN) and 10 times that of silicon carbide (SiC), which are wide band gap semiconductor materials. The gallium oxide material has very wide application prospect in power devices in the future.
However, gallium oxide has two key bottlenecks. Firstly, the gallium oxide is difficult to realize P-type doping due to the hole self-trapping effect, so that the gallium oxide power device is a normally-open device, and the reliability and the power loss of the device are greatly improved. In addition, due to the extremely low thermal conductivity of gallium oxide, the gallium oxide power device has a very serious self-heating effect, so that the power characteristics of the gallium oxide device are reduced.
Therefore, it is necessary to provide a gallium oxide cascades structure based on heterogeneous integration and a preparation method.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present application is directed to providing a gallium oxide cascades structure based on heterogeneous integration and a preparation method thereof, which are used for solving the problems that a gallium oxide wide bandgap semiconductor material in the prior art cannot be used for preparing normally-off devices and is difficult to solve heat dissipation.
To achieve the above and other related objects, the present application provides a method for preparing a gallium oxide cascades structure based on heterogeneous integration, comprising the steps of:
providing a substrate;
forming a gallium oxide layer on the substrate to prepare a heterogeneous integrated substrate;
patterning the gallium oxide layer to expose a portion of the surface of the substrate;
forming a P-well region on the exposed surface of the substrate;
n-type doping is carried out on the P-well region, and a first source region and a first drain region which are positioned in the P-well region are formed;
performing metal deposition to form a first metal source electrode in ohmic contact with the first source region and a first metal drain electrode in ohmic contact with the first drain region;
forming a first gate stack structure on the P-well region, wherein the first gate stack structure comprises a first gate dielectric layer in contact with the P-well region and a first gate electrode positioned on the first gate dielectric layer, and preparing an enhanced device;
forming a first passivation layer to cover the enhanced device;
exposing the gallium oxide layer and part of the substrate;
n-type doping is carried out on the gallium oxide layer, and a second source region and a second drain region which are positioned in the gallium oxide layer are formed;
performing metal deposition to form a second metal source electrode in ohmic contact with the second source region and a second metal drain electrode in ohmic contact with the second drain region;
forming a second gate stack structure on the gallium oxide layer, wherein the second gate stack structure comprises a second gate dielectric layer contacted with the gallium oxide layer and a second gate electrode positioned on the second gate dielectric layer, and preparing a power device;
forming a second passivation layer to cover the power device;
patterning the first passivation layer and the second passivation layer to form a through hole exposing the first metal source electrode, the first metal drain electrode, the first grid electrode, the second metal source electrode, the second metal drain electrode and the second grid electrode;
and forming a metal interconnection piece in the through hole, wherein the first metal drain electrode and the second metal source electrode are interconnected through the metal interconnection piece, and the first metal source electrode and the second gate electrode are interconnected through the metal interconnection piece.
Optionally, the method of preparing the heterogeneous integrated substrate includes a bond lapping method comprising:
providing a gallium oxide substrate;
bonding the gallium oxide substrate with the substrate;
and grinding the gallium oxide substrate to form a gallium oxide layer on the substrate to prepare the heterogeneous integrated base.
Optionally, the method for preparing the heterogeneous integrated substrate includes a smart lift-off transfer method, the smart lift-off transfer method including:
providing a gallium oxide substrate;
performing defect ion implantation in the gallium oxide substrate to form a defect layer in the gallium oxide substrate;
bonding an implantation surface of the gallium oxide substrate to the substrate;
annealing and stripping are carried out, and part of the gallium oxide substrate is stripped and removed from the defect layer;
grinding to form a gallium oxide layer on the substrate to prepare the heterogeneous integrated substrate.
Optionally, an insulating layer is further formed between the gallium oxide layer and the substrate in the heterogeneous integrated base, and the insulating layer includes a silicon oxide layer.
Optionally, the thickness of the gallium oxide layer is 0.01-10 mu m; the substrate comprises a Si substrate, a SiC substrate or a diamond substrate; the resistivity range of the substrate is greater than 10000 Ω cm.
Optionally, the method further comprises the step of forming an isolation structure in the substrate that isolates the enhancement device from the power device, the isolation structure comprising an STI isolation structure.
Optionally, when forming the second gate stack structure, a step of etching the gallium oxide layer is further included to form a concave gate stack structure.
Optionally, square ion implantation is adopted when the second source region and the second drain region are formed, the ion implantation depth is 100nm, and the ion implantation concentration is 1E18-1E20/cm 3 。
The application also provides a gallium oxide cascades structure based on heterogeneous integration, which comprises the following components:
a substrate;
the enhancement mode device comprises a P-well region, a first source region, a first drain region, a first metal source electrode, a first metal drain electrode and a first gate stack structure, wherein the first source region and the first drain region are positioned in the P-well region, the first metal source electrode is in ohmic contact with the first source region, the first metal drain electrode is in ohmic contact with the first drain region, the first gate stack structure is positioned on the P-well region and comprises a first gate dielectric layer in contact with the P-well region and a first gate electrode positioned on the first gate dielectric layer; the power device comprises a gallium oxide layer, a second source region, a second drain region, a second metal source electrode, a second metal drain electrode and a second gate stack structure, wherein the second source region and the second drain region are positioned in the gallium oxide layer, the second metal source electrode is in ohmic contact with the second source region, the second metal drain electrode is in ohmic contact with the second drain region, the second gate stack structure is positioned on the gallium oxide layer and comprises a second gate dielectric layer in contact with the gallium oxide layer and a second gate electrode positioned on the second gate dielectric layer;
the first passivation layer coats the enhanced device, and the second passivation layer coats the power device;
the through hole penetrates through the first passivation layer and the second passivation layer and exposes the first metal source electrode, the first metal drain electrode, the first grid electrode, the second metal source electrode, the second metal drain electrode and the second grid electrode;
the metal interconnection piece is located in the through hole, the first metal drain electrode and the second metal source electrode are interconnected through the metal interconnection piece, and the first metal source electrode and the second gate electrode are interconnected through the metal interconnection piece.
Optionally, the thickness of the gallium oxide layer is 0.01-10 mu m; the substrate comprises a Si substrate, a SiC substrate or a diamond substrate; the resistivity range of the substrate is greater than 10000 Ω cm.
As described above, according to the gallium oxide cascades structure and the preparation method based on heterogeneous integration, the cascades structure is prepared by integrating the gallium oxide semiconductor material which cannot realize P-type doping with the enhanced device by the heterogeneous integration method, and the cascades structure is prepared on the substrate which has high heat dissipation capacity, so that the enhanced cascade power device can be prepared based on the cascades structure, and high heat conduction can be realized, and the problems that gallium oxide cannot prepare normally-off devices and dissipate heat are solved.
Drawings
Fig. 1 is a schematic view showing a structure after a gallium oxide substrate is bonded to a substrate in an embodiment.
Fig. 2 is a schematic structural diagram of a heterogeneous integrated substrate formed by polishing the gallium oxide substrate in fig. 1 according to an embodiment.
Fig. 3 is a schematic diagram of a structure of a gallium oxide substrate after performing a defect ion implantation to form a defect layer in the embodiment.
Fig. 4 is a schematic view showing a structure after the gallium oxide substrate of fig. 3 is bonded to the substrate.
Fig. 5 is a schematic structural diagram of a hetero-integrated substrate formed by annealing and stripping the structure in fig. 4.
Fig. 6 is a schematic diagram of a structure of a patterned gallium oxide layer according to an embodiment.
Fig. 7 is a schematic diagram of a structure after forming the enhancement device and the first passivation layer in the embodiment.
Fig. 8 is a schematic structural diagram of the power device and the second passivation layer after forming the power device according to the embodiment.
Fig. 9 is a schematic diagram of a structure after forming metal interconnections in an embodiment.
Fig. 10 is a schematic diagram of an interconnection structure based on a hetero-integrated gallium oxide cascades structure in an embodiment.
Fig. 11 is a schematic circuit diagram of a gallium oxide cascades structure based on heterogeneous integration in an embodiment.
Description of element reference numerals
100 substrate
200 gallium oxide substrate
210 gallium oxide layer
201 defect layer
200a injection plane
300 enhancement mode device
301P-well region
302 first drain region
303 first source region
304 first metal drain
305 first metal source
306 a first gate dielectric layer
307 first grid electrode
410 a first passivation layer
420 a second passivation layer
500 power device
502 second drain region
503 second source region
504 second metal drain
505 second metal source electrode
506 a second gate dielectric layer
507 second grid electrode
600 metal interconnect
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
Referring to fig. 1 to 9, the present embodiment provides a preparation method of a gallium oxide cascades structure based on heterogeneous integration. The preparation of the cascades will be described below with reference to the accompanying drawings.
First, referring to fig. 1 to 5, step S1 and step S2 are performed to provide a substrate 100, and a gallium oxide layer 210 is formed on the substrate 100 to prepare a heterogeneous integrated base.
As an example, the method of preparing the heterogeneous integrated substrate includes a bond grinding method or a smart cut transfer method.
Specifically, referring to fig. 1 to 2, when the bonding polishing method is adopted, the method may include the following steps:
providing a gallium oxide substrate 200 and bonding the gallium oxide substrate 200 to the substrate 100, as shown in fig. 1;
the gallium oxide substrate 200 is ground to form a gallium oxide layer on the substrate 100 to prepare the heterogeneous integrated base.
Referring to fig. 3 to 5, when the smart lift-off transfer method is adopted, the method may include the steps of:
providing a gallium oxide substrate 200, and performing defect ion implantation, such as implantation H, he plasma, in the gallium oxide substrate 200 to form a defect layer 201 in the gallium oxide substrate 200, as shown in fig. 3;
bonding an implantation surface 200a of the gallium oxide substrate 200 to the substrate 100 as shown in fig. 4;
performing annealing delamination, removing part of the gallium oxide substrate 200 from the defect layer 201, and grinding to form a gallium oxide layer 210 on the substrate 100 to prepare the hetero-integrated base, as shown in fig. 5.
The polishing method may include one or a combination of mechanical polishing and CMP polishing, and the thickness of the gallium oxide layer 210 is preferably 0.01 to 10 μm, such as 0.01 μm, 0.1 μm, 1 μm, 10 μm, etc., after polishing, and may be specifically selected according to the need.
As an example, the substrate 100 may include a Si substrate, a SiC substrate, or a diamond substrate to provide a highly thermally conductive substrate to improve heat dissipation capability; the resistivity of the substrate 100 is in the range of greater than 10000 Ω·cm. Wherein the substrate 100 may be a high-resistance or semi-insulating semiconductor substrate or a P-type semiconductor substrate to provide the substrate 100 with high resistivity.
As an example, in the heterogeneous integrated base, an insulating layer (not shown) may be further formed between the gallium oxide layer 210 and the substrate 100, and the insulating layer may include a silicon oxide layer to realize isolation between subsequent devices through the insulating layer. The insulating layer is formed on one or a combination of the surface of the substrate 100 and the surface of the gallium oxide substrate 200, as before bonding, so that the insulating layer having a good insulating effect can be formed between the gallium oxide layer 210 and the substrate 100 after bonding.
Next, referring to fig. 6, step S3 is performed to pattern the gallium oxide layer 210, and expose a portion of the surface of the substrate 100.
Specifically, the patterning operation may be performed by using a photolithography and etching process, and in this embodiment, the photoresist or other masks used for photolithography and etching are not shown, and may be specifically set as required, which is not limited herein.
Next, referring to fig. 7, steps S4 to S8 are performed to prepare the enhancement mode device 300 and the first passivation layer 410 covering the enhancement mode device 300.
Wherein, preparing the enhanced device 300 may comprise the steps of:
s4: forming a P-well region 301 on the exposed surface of the substrate 100;
s5: n-type doping is carried out on the P-well region 301 to form a first source region 303 and a first drain region 302 which are positioned in the P-well region 301;
s6: performing metal deposition to form a first metal source 305 in ohmic contact with the first source region 303 and a first metal drain 304 in ohmic contact with the first drain region 302;
s7: a first gate stack structure is formed on the P-well region 301, and the first gate stack structure includes a first gate dielectric layer 306 contacting the P-well region 301 and a first gate 307 on the first gate dielectric layer 306.
In particular, an ion implantation process or an epitaxial process may be employed on the substrate 100The target region forms the P-well region 301, such as a P-doped Si substrate, siC substrate, or diamond substrate. The first metal drain 304 and the first metal source 305 may include a Ti/Au metal layer, but are not limited thereto. The first gate dielectric layer 306 may comprise SiO 2 、Al 2 O 3 HfO (HfO) 2 The first gate 307 may include, but is not limited to, poly Si, ni/Au, or the like.
In step S8, the material of the first passivation layer 410 may include silicon oxide, silicon nitride, etc., which is not limited herein.
Next, referring to fig. 8, steps S9 to S12 are performed to prepare a power device 500 and a second passivation layer 420 covering the power device 500.
Wherein, the preparation of the power device 500 may include the steps of:
s9: exposing the gallium oxide layer 210 and a portion of the substrate 100;
s10: n-type doping is performed on the gallium oxide layer 210 to form a second source region 503 and a second drain region 502 located in the gallium oxide layer 210;
s11: performing metal deposition to form a second metal source electrode 505 in ohmic contact with the second source region 503 and a second metal drain electrode 504 in ohmic contact with the second drain region 502;
s12: a second gate stack structure is formed on the gallium oxide layer 210, and the second gate stack structure includes a second gate dielectric layer 506 in contact with the gallium oxide layer 210 and a second gate 507 on the second gate dielectric layer 506.
Wherein after performing step S9 and before step S10, a step of forming an isolation structure (not shown) in the substrate 100 to isolate the enhancement device 300 from the power device 500, the isolation structure may include an STI isolation structure to ensure electrical insulation on the substrate 100 by the isolation structure. Square ion implantation may be used in forming the second source region 503 and the second drain region 502, and the ion implantation depth may be 100nm, and the ion implantation concentration may be 1E18-1E20/cm 3 For example 1E18/cm 3 、1E19/cm 3 、1E20/cm 3 Etc. The second metal drain 504 and the second metal source 505 may include a Ti/Au metal layer, but are not limited thereto. The second gate dielectric layer 506 may comprise SiO 2 、Al 2 O 3 HfO (HfO) 2 The second gate electrode 507 may include, but is not limited to, pt/Au, ni/Au, etc.
In step S13, the material of the second passivation layer 420 may include silicon oxide, silicon nitride, etc., which is not limited herein.
As an example, in forming the second gate stack structure, a step of etching the gallium oxide layer 210 is preferably included to form a concave gate stack structure, as shown in fig. 8, to increase the current density of the device.
Next, referring to fig. 9, step S14 is performed to pattern the first passivation layer 410 and the second passivation layer 420, form a via (not shown) exposing the first metal source 305, the first metal drain 304, the first gate 307, the second metal source 505, the second metal drain 504 and the second gate 507, and step S15 is performed to form a metal interconnection 600 in the via, wherein the first metal drain 304 and the second metal source 505 are interconnected by the metal interconnection 600, and the first metal source 305 and the second gate 507 are interconnected by the metal interconnection 600.
Specifically, referring to fig. 10 and 11, an interconnection structure and a circuit based on a hetero-integrated gallium oxide cascades structure are illustrated, the cascades structure can be prepared by integrating a gallium oxide semiconductor material which cannot realize P-type doping with an enhanced device through a hetero-integration method, and the cascades structure is prepared on the substrate 100 with high heat dissipation capability, so that an enhanced cascade power device can be prepared based on the cascades structure, and high heat conduction can be realized, thereby solving the problem that gallium oxide cannot prepare normally-off devices and dissipate heat.
Referring to fig. 8 to fig. 10, the present embodiment further provides a gallium oxide cascades structure based on heterogeneous integration, where the cascades structure includes:
a substrate 100;
the enhancement mode device 300 and the power device 500 are located on the substrate 100, wherein the enhancement mode device 300 comprises a P-well region 301, a first source region 303 and a first drain region 302 located in the P-well region 301, a first metal source 305 in ohmic contact with the first source region 303, a first metal drain 304 in ohmic contact with the first drain region 302, and a first gate stack structure located on the P-well region 301, the first gate stack structure comprising a first gate dielectric layer 306 in contact with the P-well region 301 and a first gate 307 located on the first gate dielectric layer 306; the power device 500 includes a gallium oxide layer 210, a second source region 503 and a second drain region 502 in the gallium oxide layer 210, a second metal source 505 in ohmic contact with the second source region 503, a second metal drain 504 in ohmic contact with the second drain region 502, and a second gate stack structure on the gallium oxide layer 210, where the second gate stack structure includes a second gate dielectric layer 506 in contact with the gallium oxide layer 210 and a second gate 507 on the second gate dielectric layer 506;
a first passivation layer 410 and a second passivation layer 420, the first passivation layer 410 coating the enhancement mode device 300, the second passivation layer 420 coating the power device 500;
a via (not shown) penetrating the first passivation layer 410 and the second passivation layer 420 and exposing the first metal source 305, the first metal drain 304, the first gate 307, the second metal source 505, the second metal drain 504 and the second gate 507;
a metal interconnect 600, the metal interconnect 600 is located in the via, and the first metal drain 304 and the second metal source 505 are interconnected by the metal interconnect 600, and the first metal source 305 and the second gate 507 are interconnected by the metal interconnect 600.
For the preparation, materials, structures, etc. of the cascades, reference may be made to the above description about the preparation of the cascades, and details thereof are omitted herein.
As an example, the thickness of the gallium oxide layer 210 may be 0.01 to 10 μm; the substrate 100 may include a Si substrate, a SiC substrate, or a diamond substrate to provide a highly thermally conductive substrate to improve heat dissipation capability; the resistivity of the substrate 100 is in the range of greater than 10000 Ω·cm. Wherein the substrate 100 may be a high-resistance or semi-insulating semiconductor substrate or a P-type semiconductor substrate to provide the substrate 100 with high resistivity.
In summary, according to the gallium oxide cascades structure and the preparation method based on heterogeneous integration, the cascades structure is prepared by integrating the gallium oxide semiconductor material which cannot realize P-type doping and the enhancement type device through the heterogeneous integration method, and the cascades structure is prepared on the substrate with high heat dissipation capability, so that the enhancement type cascade power device can be prepared based on the cascades structure, high heat conduction can be realized, and the problems that gallium oxide cannot prepare normally-off devices and dissipate heat are solved.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. The preparation method of the gallium oxide cascades structure based on heterogeneous integration is characterized by comprising the following steps of:
providing a substrate, wherein the substrate comprises a Si substrate, a SiC substrate or a diamond substrate, and the resistivity range of the substrate is larger than 10000 Ω & cm;
forming a gallium oxide layer on the substrate to prepare a heterogeneous integrated substrate;
patterning the gallium oxide layer to expose a portion of the surface of the substrate;
forming a P-well region on the exposed surface of the substrate;
n-type doping is carried out on the P-well region, and a first source region and a first drain region which are positioned in the P-well region are formed;
performing metal deposition to form a first metal source electrode in ohmic contact with the first source region and a first metal drain electrode in ohmic contact with the first drain region;
forming a first gate stack structure on the P-well region, wherein the first gate stack structure comprises a first gate dielectric layer in contact with the P-well region and a first gate electrode positioned on the first gate dielectric layer, and preparing an enhanced device;
forming a first passivation layer to cover the enhanced device;
exposing the gallium oxide layer and part of the substrate;
n-type doping is carried out on the gallium oxide layer, and a second source region and a second drain region which are positioned in the gallium oxide layer are formed;
performing metal deposition to form a second metal source electrode in ohmic contact with the second source region and a second metal drain electrode in ohmic contact with the second drain region;
forming a second gate stack structure on the gallium oxide layer, wherein the second gate stack structure comprises a second gate dielectric layer contacted with the gallium oxide layer and a second gate electrode positioned on the second gate dielectric layer, and preparing a power device, and the second gate stack structure further comprises a step of etching the gallium oxide layer to form a concave gate stack structure;
forming a second passivation layer to cover the power device;
patterning the first passivation layer and the second passivation layer to form a through hole exposing the first metal source electrode, the first metal drain electrode, the first grid electrode, the second metal source electrode, the second metal drain electrode and the second grid electrode;
and forming a metal interconnection piece in the through hole, wherein the first metal drain electrode and the second metal source electrode are interconnected through the metal interconnection piece, and the first metal source electrode and the second gate electrode are interconnected through the metal interconnection piece.
2. The method for preparing the gallium oxide cascades based on heterogeneous integration according to claim 1, which is characterized in that: the method of preparing the heterogeneous integrated substrate includes a bond lapping process comprising:
providing a gallium oxide substrate;
bonding the gallium oxide substrate with the substrate;
and grinding the gallium oxide substrate to form a gallium oxide layer on the substrate to prepare the heterogeneous integrated base.
3. The method for preparing the gallium oxide cascades based on heterogeneous integration according to claim 1, which is characterized in that: the method for preparing the heterogeneous integrated substrate comprises a smart lift-off transfer method, wherein the smart lift-off transfer method comprises the following steps:
providing a gallium oxide substrate;
performing defect ion implantation in the gallium oxide substrate to form a defect layer in the gallium oxide substrate;
bonding an implantation surface of the gallium oxide substrate to the substrate;
annealing and stripping are carried out, and part of the gallium oxide substrate is stripped and removed from the defect layer;
grinding to form a gallium oxide layer on the substrate to prepare the heterogeneous integrated substrate.
4. The method for preparing a heterointegrated cascades structure according to claim 1, wherein the method comprises the following steps: in the heterogeneous integrated substrate, an insulating layer is further formed between the gallium oxide layer and the substrate, and the insulating layer comprises a silicon oxide layer.
5. The method for preparing a heterointegrated cascades structure according to claim 1, wherein the method comprises the following steps: the thickness of the gallium oxide layer is 0.01-10 mu m.
6. The method for preparing a heterointegrated cascades structure according to claim 1, wherein the method comprises the following steps: further comprising the step of forming an isolation structure in the substrate that isolates the enhancement device from the power device, the isolation structure comprising an STI isolation structure.
7. The method for preparing the gallium oxide cascades based on heterogeneous integration according to claim 1, which is characterized in that: square ion implantation is adopted when the second source region and the second drain region are formed, the ion implantation depth is 100nm, and the ion implantation concentration is 1E18-1E20/cm 3 。
8. A gallium oxide scale structure based on heterogeneous integration, the scale structure comprising:
a substrate comprising a Si substrate, a SiC substrate or a diamond substrate, and having a resistivity range of greater than 10000 Ω -cm;
the enhancement mode device comprises a P-well region, a first source region, a first drain region, a first metal source electrode, a first metal drain electrode and a first gate stack structure, wherein the first source region and the first drain region are positioned in the P-well region, the first metal source electrode is in ohmic contact with the first source region, the first metal drain electrode is in ohmic contact with the first drain region, the first gate stack structure is positioned on the P-well region and comprises a first gate dielectric layer in contact with the P-well region and a first gate electrode positioned on the first gate dielectric layer; the power device comprises a gallium oxide layer, a second source region and a second drain region which are positioned in the gallium oxide layer, a second metal source electrode in ohmic contact with the second source region, a second metal drain electrode in ohmic contact with the second drain region, and a second gate stack structure positioned on the gallium oxide layer, wherein the second gate stack structure comprises a second gate dielectric layer in contact with the gallium oxide layer and a second gate electrode positioned on the second gate dielectric layer, the gallium oxide layer is formed on the substrate by adopting a bonding grinding method or an intelligent stripping transfer method, and the second gate stack structure comprises a concave gate stack structure formed by etching the gallium oxide layer;
the first passivation layer coats the enhanced device, and the second passivation layer coats the power device;
the through hole penetrates through the first passivation layer and the second passivation layer and exposes the first metal source electrode, the first metal drain electrode, the first grid electrode, the second metal source electrode, the second metal drain electrode and the second grid electrode;
the metal interconnection piece is located in the through hole, the first metal drain electrode and the second metal source electrode are interconnected through the metal interconnection piece, and the first metal source electrode and the second gate electrode are interconnected through the metal interconnection piece.
9. The heterogeneous integration-based cascades structure of claim 8, wherein: the thickness of the gallium oxide layer is 0.01-10 mu m.
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| CN109427822A (en) * | 2017-08-28 | 2019-03-05 | 拉碧斯半导体株式会社 | The manufacturing method of semiconductor device and semiconductor device |
| CN113224155A (en) * | 2021-04-08 | 2021-08-06 | 中山大学 | Gallium nitride transistor with high conduction capability and preparation method thereof |
| CN114582861A (en) * | 2022-03-09 | 2022-06-03 | 西安电子科技大学 | Single event effect reinforced printing transfer GaN/Ga2O3Cascode power device |
| CN114582862A (en) * | 2022-03-09 | 2022-06-03 | 西安电子科技大学 | Monolithic integration GaN/Ga2O3Cascode enhanced single-particle burnout resistant device and preparation method thereof |
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| CN111863806A (en) * | 2020-07-30 | 2020-10-30 | 西安电子科技大学 | Bidirectional blocking monolithic heterogeneous integrated Cascode structure field effect transistor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109427822A (en) * | 2017-08-28 | 2019-03-05 | 拉碧斯半导体株式会社 | The manufacturing method of semiconductor device and semiconductor device |
| CN113224155A (en) * | 2021-04-08 | 2021-08-06 | 中山大学 | Gallium nitride transistor with high conduction capability and preparation method thereof |
| CN114582861A (en) * | 2022-03-09 | 2022-06-03 | 西安电子科技大学 | Single event effect reinforced printing transfer GaN/Ga2O3Cascode power device |
| CN114582862A (en) * | 2022-03-09 | 2022-06-03 | 西安电子科技大学 | Monolithic integration GaN/Ga2O3Cascode enhanced single-particle burnout resistant device and preparation method thereof |
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