CN115831877A - Gallium oxide cascade structure based on heterogeneous integration and preparation method - Google Patents
Gallium oxide cascade structure based on heterogeneous integration and preparation method Download PDFInfo
- Publication number
- CN115831877A CN115831877A CN202211599584.XA CN202211599584A CN115831877A CN 115831877 A CN115831877 A CN 115831877A CN 202211599584 A CN202211599584 A CN 202211599584A CN 115831877 A CN115831877 A CN 115831877A
- Authority
- CN
- China
- Prior art keywords
- substrate
- gallium oxide
- metal
- layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 124
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 124
- 230000010354 integration Effects 0.000 title claims abstract description 30
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 132
- 238000000034 method Methods 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims description 97
- 239000002184 metal Substances 0.000 claims description 97
- 238000002161 passivation Methods 0.000 claims description 36
- 238000005468 ion implantation Methods 0.000 claims description 14
- 238000000227 grinding Methods 0.000 claims description 13
- 230000007547 defect Effects 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 11
- 229910003460 diamond Inorganic materials 0.000 claims description 7
- 239000010432 diamond Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 abstract description 12
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8256—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252 and H01L21/8254
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a gallium oxide cascade structure based on heterogeneous integration and a preparation method thereof, wherein a gallium oxide semiconductor material which can not realize P-type doping and an enhanced device are integrated to prepare the cascade structure by the heterogeneous integration method, the cascade structure is prepared on a substrate with high heat dissipation capacity, and an enhanced cascade power device can be prepared and high heat conduction can be realized based on the cascade structure, so that the problems that a normally-closed device can not be prepared and heat dissipation can not be realized by gallium oxide are solved.
Description
Technical Field
The invention belongs to the field of semiconductors, and relates to a gallium oxide cascade structure based on heterogeneous integration and a preparation method thereof.
Background
Gallium oxide (Ga) 2 O 3 ) As a semiconductor material with ultra-wide forbidden band, the maximum critical breakdown field strength of the material reaches 8MV/cm due to the extremely large forbidden band width, and meanwhile, gallium oxide is easy to carry out n-type doping and is easy to prepare good European-type dopingDue to the ohmic contact, the power device prepared based on the ohmic contact not only has high breakdown voltage, but also has low conduction loss, so that the power conversion efficiency of the device is greatly improved. The power quality factor (PFOM) of gallium oxide is 4 times that of gallium nitride (GaN) and 10 times that of silicon carbide (SiC), which are both wide bandgap semiconductor materials. The gallium oxide material has very wide application prospect in power devices in the future.
However, gallium oxide has two key bottlenecks. Firstly, the gallium oxide is difficult to realize P type doping due to the hole self-trapping effect, so that the gallium oxide power device is a normally-on device, and the reliability and the power loss of the device are greatly improved. In addition, due to the extremely low thermal conductivity of gallium oxide, the power device of gallium oxide has a very serious self-heating effect, thereby reducing the power characteristics of the gallium oxide device.
Therefore, it is necessary to provide a gallium oxide cascade structure based on heterogeneous integration and a preparation method thereof.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a gallium oxide cascade structure based on heterogeneous integration and a fabrication method thereof, so as to solve the problems that a normally-off device cannot be fabricated and heat dissipation is difficult to solve in the gallium oxide wide bandgap semiconductor material in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a method for preparing a gallium oxide cascade structure based on heterogeneous integration, comprising the following steps:
providing a substrate;
forming a gallium oxide layer on the substrate to prepare a heterogeneous integrated substrate;
patterning the gallium oxide layer to expose part of the surface of the substrate;
forming a P-well area on the exposed surface of the substrate;
carrying out N-type doping on the P-well region to form a first source region and a first drain region which are positioned in the P-well region;
carrying out metal deposition to form a first metal source electrode in ohmic contact with the first source region and a first metal drain electrode in ohmic contact with the first drain region;
forming a first gate stack structure on the P-well region, wherein the first gate stack structure comprises a first gate dielectric layer which is in contact with the P-well region and a first gate electrode which is positioned on the first gate dielectric layer, and preparing an enhancement device;
forming a first passivation layer to cover the enhancement mode device;
exposing the gallium oxide layer and part of the substrate;
carrying out N-type doping on the gallium oxide layer to form a second source region and a second drain region which are positioned in the gallium oxide layer;
performing metal deposition to form a second metal source electrode in ohmic contact with the second source region and a second metal drain electrode in ohmic contact with the second drain region;
forming a second gate stack structure on the gallium oxide layer, wherein the second gate stack structure comprises a second gate dielectric layer in contact with the gallium oxide layer and a second gate electrode positioned on the second gate dielectric layer, and preparing a power device;
forming a second passivation layer to cover the power device;
patterning the first passivation layer and the second passivation layer to form a through hole exposing the first metal source electrode, the first metal drain electrode, the first grid electrode, the second metal source electrode, the second metal drain electrode and the second grid electrode;
and forming a metal interconnection piece in the through hole, wherein the first metal drain electrode and the second metal source electrode are interconnected through the metal interconnection piece, and the first metal source electrode and the second gate electrode are interconnected through the metal interconnection piece.
Optionally, the method of preparing the heterogeneous integrated substrate comprises a bond-grinding method, the bond-grinding method comprising:
providing a gallium oxide substrate;
bonding the gallium oxide substrate with the substrate;
and grinding the gallium oxide substrate to form a gallium oxide layer positioned on the substrate to prepare the heterogeneous integrated base.
Optionally, the method of preparing the heterogeneous integrated substrate comprises a smart peel transfer process comprising:
providing a gallium oxide substrate;
performing defect ion implantation in the gallium oxide substrate to form a defect layer in the gallium oxide substrate;
bonding the implantation surface of the gallium oxide substrate with the substrate;
performing annealing stripping to strip off part of the gallium oxide substrate from the defect layer;
and grinding to form a gallium oxide layer on the substrate to prepare the heterogeneous integrated base.
Optionally, in the hetero-integrated base, an insulating layer is further formed between the gallium oxide layer and the substrate, and the insulating layer includes a silicon oxide layer.
Optionally, the thickness of the gallium oxide layer is 0.01 to 10 μm; the substrate comprises a Si substrate, a SiC substrate or a diamond substrate; the resistivity range of the substrate is larger than 10000 omega cm.
Optionally, the method further comprises forming an isolation structure in the substrate to isolate the enhancement mode device from the power device, the isolation structure comprising an STI isolation structure.
Optionally, when the second gate stack structure is formed, the method further includes a step of etching the gallium oxide layer to form a recessed gate stack structure.
Optionally, when the second source region and the second drain region are formed, square ion implantation is adopted, the ion implantation depth is 100nm, and the ion implantation concentration is 1E18-1E20/cm 3 。
The invention also provides a gallium oxide cascade structure based on heterogeneous integration, and the cascade structure comprises:
a substrate;
the enhancement mode device and the power device are positioned on the substrate, wherein the enhancement mode device comprises a P-well region, a first source region and a first drain region which are positioned in the P-well region, a first metal source electrode in ohmic contact with the first source region, a first metal drain electrode in ohmic contact with the first drain region, and a first gate stack structure positioned on the P-well region, and the first gate stack structure comprises a first gate dielectric layer in contact with the P-well region and a first gate electrode positioned on the first gate dielectric layer; the power device comprises a gallium oxide layer, a second source region and a second drain region which are positioned in the gallium oxide layer, a second metal source electrode in ohmic contact with the second source region, a second metal drain electrode in ohmic contact with the second drain region, and a second gate stacking structure positioned on the gallium oxide layer, wherein the second gate stacking structure comprises a second gate dielectric layer in contact with the gallium oxide layer and a second gate positioned on the second gate dielectric layer;
a first passivation layer and a second passivation layer, the first passivation layer encapsulating the enhancement mode device, the second passivation layer encapsulating the power device;
the through hole penetrates through the first passivation layer and the second passivation layer and exposes the first metal source electrode, the first metal drain electrode, the first grid electrode, the second metal source electrode, the second metal drain electrode and the second grid electrode;
the metal interconnection piece is located in the through hole, the first metal drain electrode is connected with the second metal source electrode through the metal interconnection piece, and the first metal source electrode is connected with the second grid electrode through the metal interconnection piece.
Optionally, the thickness of the gallium oxide layer is 0.01 to 10 μm; the substrate comprises a Si substrate, a SiC substrate or a diamond substrate; the resistivity range of the substrate is larger than 10000 omega cm.
As described above, according to the gallium oxide cascade structure based on heterogeneous integration and the preparation method thereof, the gallium oxide semiconductor material which cannot realize P-type doping and the enhancement type device are integrated to prepare the cascade structure by the heterogeneous integration method, and the cascade structure is prepared on the substrate with high heat dissipation capability, so that the enhancement type cascade power device can be prepared based on the casade structure, high heat conduction can be realized, and the problems that the normally-closed device cannot be prepared and the heat dissipation cannot be realized by the gallium oxide are solved.
Drawings
Fig. 1 is a schematic structural view of a gallium oxide substrate bonded to a substrate in the embodiment.
Fig. 2 is a schematic structural diagram of a heterogeneous integrated base formed by grinding the gallium oxide substrate in fig. 1 in the example.
FIG. 3 is a schematic structural diagram of a gallium oxide substrate after defect ion implantation to form a defect layer in the embodiment.
Fig. 4 is a schematic structural diagram of the gallium oxide substrate and the substrate in fig. 3 after bonding.
Fig. 5 is a schematic structural diagram of a heterogeneous integrated substrate formed after the structure in fig. 4 is subjected to annealing stripping.
Fig. 6 is a schematic structural diagram after patterning the gallium oxide layer in the embodiment.
FIG. 7 is a schematic diagram illustrating an embodiment of a structure after forming an enhancement device and a first passivation layer.
Fig. 8 is a schematic structural diagram of the power device and the second passivation layer after being formed in the embodiment.
Fig. 9 is a schematic structural view of the embodiment after forming a metal interconnection.
Fig. 10 is a schematic diagram illustrating an interconnection structure of a gallium oxide cascade structure based on heterogeneous integration in the embodiment.
Fig. 11 is a schematic circuit diagram of a gallium oxide cascade structure based on heterogeneous integration in the embodiment.
Description of the element reference
100 substrate
200 gallium oxide substrate
210 gallium oxide layer
201 defective layer
200a implantation surface
300 enhancement mode device
301P-well area
302 first drain region
303 first source region
304 first metal drain
305 first metal source
306 first gate dielectric layer
307 first grid
410 first passivation layer
420 second passivation layer
500 power device
502 second drain region
503 second source region
504 second metal drain
505 second metal source
506 second gate dielectric layer
507 second grid
600 metal interconnection
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between 8230 \ 8230;" between "means both end points are included.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1 to 9, the present embodiment provides a method for fabricating a gallium oxide cascade structure based on heterogeneous integration. The preparation of the cascade structure is described below with reference to the accompanying drawings.
First, referring to fig. 1 to 5, step S1 and step S2 are performed to provide a substrate 100, and a gallium oxide layer 210 is formed on the substrate 100 to prepare a heterogeneous integrated substrate.
As an example, the method of preparing the heterogeneous integration substrate includes a bonding grinding method or a smart cut transfer method.
Specifically, referring to fig. 1 to 2, when the bond grinding method is used, the following steps may be included:
providing a gallium oxide substrate 200, and bonding the gallium oxide substrate 200 with the substrate 100, as shown in fig. 1;
and grinding the gallium oxide substrate 200 to form a gallium oxide layer on the substrate 100 to prepare the heterogeneous integrated base.
Referring to fig. 3 to 5, when the smart cut transfer method is used, the following steps may be included:
providing a gallium oxide substrate 200, and performing defect ion implantation, such as implanting ions of H, he, etc., in the gallium oxide substrate 200 to form a defect layer 201 in the gallium oxide substrate 200, as shown in fig. 3;
bonding the implantation surface 200a of the gallium oxide substrate 200 with the substrate 100, as shown in fig. 4;
and performing annealing stripping, stripping and removing part of the gallium oxide substrate 200 from the defect layer 201, and grinding to form a gallium oxide layer 210 on the substrate 100 to prepare the heterogeneous integrated base, as shown in fig. 5.
The polishing method may include one or a combination of a mechanical polishing method and CMP polishing, and after polishing, the thickness of the gallium oxide layer 210 is preferably 0.01 to 10 μm, such as 0.01 μm, 0.1 μm, 1 μm, 10 μm, and the like, and may be specifically selected according to needs.
As an example, the substrate 100 may include a Si substrate, a SiC substrate, or a diamond substrate to provide a highly thermally conductive substrate to improve heat dissipation capability; the resistivity range of the substrate 100 is greater than 10000 Ω · cm. The substrate 100 may be a high-resistance or semi-insulating semiconductor substrate or a P-type semiconductor substrate, so as to provide the substrate 100 with high resistivity.
As an example, in the hetero-integrated base, an insulating layer (not shown) may be further formed between the gallium oxide layer 210 and the substrate 100, and the insulating layer may include a silicon oxide layer, so as to achieve isolation between subsequent devices through the insulating layer. The insulating layer is formed on one or a combination of the surface of the substrate 100 and the surface of the gallium oxide substrate 200 as before bonding, so that the insulating layer having a good insulating effect can be formed between the gallium oxide layer 210 and the substrate 100 after bonding.
Next, referring to fig. 6, step S3 is performed to pattern the gallium oxide layer 210 to expose a portion of the surface of the substrate 100.
Specifically, the patterning operation may be performed by using photolithography and etching processes, in this embodiment, neither a photoresist nor other masks used for photolithography and etching are shown, and the patterning operation may be specifically set as required, which is not limited herein.
Next, referring to fig. 7, steps S4 to S8 are performed to prepare the enhancement device 300 and a first passivation layer 410 covering the enhancement device 300.
Wherein the preparation of the enhanced device 300 may comprise the steps of:
s4: forming a P-well region 301 on the exposed surface of the substrate 100;
s5: carrying out N-type doping on the P-well area 301 to form a first source area 303 and a first drain area 302 which are positioned in the P-well area 301;
s6: performing metal deposition to form a first metal source 305 in ohmic contact with the first source region 303 and a first metal drain 304 in ohmic contact with the first drain region 302;
s7: a first gate stack structure is formed on the P-well region 301, and the first gate stack structure includes a first gate dielectric layer 306 in contact with the P-well region 301 and a first gate 307 located on the first gate dielectric layer 306.
Specifically, the P-well region 301 may be formed in a target region of the substrate 100 by an ion implantation process or an epitaxy process, such as a P-type doped Si substrate, a SiC substrate, or a diamond substrate. The first metal drain 304 and the first metal source 305 may include, but are not limited to, a Ti/Au metal layer. The first gate dielectric layer 306 may comprise SiO 2 、Al 2 O 3 And HfO 2 One or a combination thereof, but not limited thereto, the first gate 307 may include poly Si, ni/Au, etc.
In step S8, the material of the first passivation layer 410 may include silicon oxide, silicon nitride, etc., which is not limited herein.
Next, referring to fig. 8, steps S9 to S12 are performed to prepare the power device 500 and the second passivation layer 420 covering the power device 500.
Wherein, the preparation of the power device 500 may comprise the following steps:
s9: exposing the gallium oxide layer 210 and a part of the substrate 100;
s10: performing N-type doping on the gallium oxide layer 210 to form a second source region 503 and a second drain region 502 in the gallium oxide layer 210;
s11: performing metal deposition to form a second metal source 505 in ohmic contact with the second source region 503 and a second metal drain 504 in ohmic contact with the second drain region 502;
s12: and forming a second gate stack structure on the gallium oxide layer 210, wherein the second gate stack structure comprises a second gate dielectric layer 506 in contact with the gallium oxide layer 210 and a second gate 507 located on the second gate dielectric layer 506.
After step S9 and before step S10, an isolation structure (not shown) for isolating the enhancement mode device 300 from the power device 500 may be formed in the substrate 100, and the isolation structure may include an STI isolation structure, so as to ensure electrical insulation on the substrate 100 by the isolation structure. When the second source region 503 and the second drain region 502 are formed, square ion implantation may be adopted, the ion implantation depth may be 100nm, and the ion implantation concentration may be 1E18-1E20/cm 3 E.g. 1E18/cm 3 、1E19/cm 3 、1E20/cm 3 And the like. The second metal drain 505 and the second metal source 504 may include, but are not limited to, a Ti/Au metal layer. The second gate dielectric layer 506 may comprise SiO 2 、Al 2 O 3 And HfO 2 And the second gate electrode 507 may include Pt/Au, ni/Au, etc., but is not limited thereto.
In step S13, the material of the second passivation layer 420 may include silicon oxide, silicon nitride, etc., which is not limited herein.
As an example, when forming the second gate stack structure, it is preferable to include a step of etching the gallium oxide layer 210 to form a recessed gate stack structure, as shown in fig. 8, so as to improve the current density of the device.
Next, referring to fig. 9, step S14 is performed to pattern the first passivation layer 410 and the second passivation layer 420 to form a via (not shown) exposing the first metal source 305, the first metal drain 304, the first gate 307, the second metal source 505, the second metal drain 504 and the second gate 507, and step S15 is performed to form a metal interconnection 600 in the via, wherein the first metal drain 304 and the second metal source 503 are interconnected by the metal interconnection 600, and the first metal source 305 and the second gate 506 are interconnected by the metal interconnection 600.
Specifically, referring to fig. 10 and fig. 11, an interconnection structure and a circuit of a gallium oxide cascade structure based on heterogeneous integration are illustrated, the gallium oxide semiconductor material which cannot realize P-type doping and an enhancement-mode device can be integrated to prepare the cascade structure by a heterogeneous integration method, and the cascade structure is prepared on the substrate 100 which has high heat dissipation capability, so that an enhancement-mode cascade power device can be prepared based on the cascade structure, and high heat conduction can be realized, thereby solving the problem that the gallium oxide cannot prepare a normally-closed device and dissipate heat.
Referring to fig. 8 to 10, the present embodiment further provides a gallium oxide cascade structure based on heterogeneous integration, where the cascade structure includes:
a substrate 100;
an enhancement mode device 300 and a power device 500 located on the substrate 100, wherein the enhancement mode device 300 includes a P-well region 301, a first source region 303 and a first drain region 302 located in the P-well region 301, a first metal source 305 in ohmic contact with the first source region 303, a first metal drain 304 in ohmic contact with the first drain region 302, and a first gate stack structure located on the P-well region 301, the first gate stack structure includes a first gate dielectric layer 306 in contact with the P-well region 301 and a first gate 307 located on the first gate dielectric layer 306; the power device 500 includes a gallium oxide layer 210, a second source region 503 and a second drain region 502 located in the gallium oxide layer 210, a second metal source 505 in ohmic contact with the second source region 503, a second metal drain 504 in ohmic contact with the second drain region 502, and a second gate stack structure located on the gallium oxide layer 210, where the second gate stack structure includes a second gate dielectric layer 506 in contact with the gallium oxide layer 210 and a second gate 507 located on the second gate dielectric layer 506;
a first passivation layer 410 and a second passivation layer 420, the first passivation layer 410 encapsulating the enhancement device 300, the second passivation layer 420 encapsulating the power device 500;
a via (not shown) penetrating the first passivation layer 410 and the second passivation layer 420 and exposing the first metal source 305, the first metal drain 304, the first gate 307, the second metal source 505, the second metal drain 504 and the second gate 507;
a metal interconnection 600, wherein the metal interconnection 600 is located in the through hole, the first metal drain 304 and the second metal source 503 are interconnected through the metal interconnection 600, and the first metal source 305 and the second gate 506 are interconnected through the metal interconnection 600.
For the preparation, materials, structures, etc. of the cascade structure, reference may be made to the above description of the preparation of the cascade structure, which is not repeated herein.
By way of example, the thickness of the gallium oxide layer 210 may be 0.01 to 10 μm; the substrate 100 may include a Si substrate, a SiC substrate, or a diamond substrate to provide a highly thermally conductive substrate to improve heat dissipation capability; the resistivity range of the substrate 100 is greater than 10000 Ω · cm. The substrate 100 may be a high-resistance or semi-insulating semiconductor substrate or a P-type semiconductor substrate, so as to provide the substrate 100 with high resistivity.
In summary, according to the gallium oxide cascade structure based on heterogeneous integration and the preparation method thereof, the gallium oxide semiconductor material incapable of realizing P-type doping and the enhanced device are integrated to prepare the cascade structure by the heterogeneous integration method, and the cascade structure is prepared on the substrate with high heat dissipation capacity, so that the enhanced cascade power device can be prepared based on the casade structure, high heat conduction can be realized, and the problems that the gallium oxide can not prepare a normally-closed device and dissipate heat are solved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (10)
1. A preparation method of a gallium oxide cascade structure based on heterogeneous integration is characterized by comprising the following steps:
providing a substrate;
forming a gallium oxide layer on the substrate to prepare a heterogeneous integrated substrate;
patterning the gallium oxide layer to expose part of the surface of the substrate;
forming a P-well region on the exposed surface of the substrate;
n-type doping is carried out on the P-well region, and a first source region and a first drain region which are located in the P-well region are formed;
carrying out metal deposition to form a first metal source electrode in ohmic contact with the first source region and a first metal drain electrode in ohmic contact with the first drain region;
forming a first gate stack structure on the P-well region, wherein the first gate stack structure comprises a first gate dielectric layer which is in contact with the P-well region and a first gate electrode which is positioned on the first gate dielectric layer, and preparing an enhancement device;
forming a first passivation layer to cover the enhancement mode device;
exposing the gallium oxide layer and part of the substrate;
carrying out N-type doping on the gallium oxide layer to form a second source region and a second drain region which are positioned in the gallium oxide layer;
performing metal deposition to form a second metal source electrode in ohmic contact with the second source region and a second metal drain electrode in ohmic contact with the second drain region;
forming a second gate stack structure on the gallium oxide layer, wherein the second gate stack structure comprises a second gate dielectric layer in contact with the gallium oxide layer and a second gate electrode positioned on the second gate dielectric layer, and preparing a power device;
forming a second passivation layer to cover the power device;
patterning the first passivation layer and the second passivation layer to form a through hole exposing the first metal source electrode, the first metal drain electrode, the first grid electrode, the second metal source electrode, the second metal drain electrode and the second grid electrode;
and forming a metal interconnection piece in the through hole, wherein the first metal drain electrode and the second metal source electrode are interconnected through the metal interconnection piece, and the first metal source electrode and the second gate electrode are interconnected through the metal interconnection piece.
2. The method for preparing a heterogeneous integration based gallium oxide cascade structure according to claim 1, wherein: the method for preparing the heterogeneous integrated substrate comprises a bonding grinding method, wherein the bonding grinding method comprises the following steps:
providing a gallium oxide substrate;
bonding the gallium oxide substrate with the substrate;
and grinding the gallium oxide substrate to form a gallium oxide layer positioned on the substrate to prepare the heterogeneous integrated base.
3. The method for preparing a heterogeneous integration based gallium oxide cascade structure according to claim 1, wherein: the method of preparing the heterogeneous integrated substrate includes a smart peel transfer process, the smart peel transfer process comprising:
providing a gallium oxide substrate;
performing defect ion implantation in the gallium oxide substrate to form a defect layer in the gallium oxide substrate;
bonding the implantation surface of the gallium oxide substrate with the substrate;
performing annealing stripping to strip off part of the gallium oxide substrate from the defect layer;
and grinding to form a gallium oxide layer on the substrate to prepare the heterogeneous integrated base.
4. The method for preparing a cascade structure based on heterogeneous integration according to claim 1, wherein: in the heterogeneous integrated base, an insulating layer is further formed between the gallium oxide layer and the substrate, and the insulating layer comprises a silicon oxide layer.
5. The preparation method of a cascade structure based on heterogeneous integration according to claim 1, characterized in that: the thickness of the gallium oxide layer is 0.01-10 mu m; the substrate comprises a Si substrate, a SiC substrate or a diamond substrate; the resistivity range of the substrate is larger than 10000 omega cm.
6. The method for preparing a cascade structure based on heterogeneous integration according to claim 1, wherein: further comprising the step of forming an isolation structure in the substrate that isolates the enhancement mode device from the power device, the isolation structure comprising an STI isolation structure.
7. The method for preparing a heterogeneous integration based gallium oxide cascade structure according to claim 1, wherein: and when the second gate stack structure is formed, etching the gallium oxide layer to form a concave gate stack structure.
8. The method for preparing a heterogeneous integration based gallium oxide cascade structure according to claim 1, wherein: when the second source region and the second drain region are formed, square ion implantation is adopted, the ion implantation depth is 100nm, and the ion implantation concentration is 1E18-1E20/cm 3 。
9. A gallium oxide cascade structure based on heterogeneous integration, the cascade structure comprising:
a substrate;
the enhancement mode device and the power device are positioned on the substrate, wherein the enhancement mode device comprises a P-well region, a first source region and a first drain region which are positioned in the P-well region, a first metal source electrode in ohmic contact with the first source region, a first metal drain electrode in ohmic contact with the first drain region, and a first gate stack structure positioned on the P-well region, and the first gate stack structure comprises a first gate dielectric layer in contact with the P-well region and a first gate electrode positioned on the first gate dielectric layer; the power device comprises a gallium oxide layer, a second source region and a second drain region which are positioned in the gallium oxide layer, a second metal source electrode in ohmic contact with the second source region, a second metal drain electrode in ohmic contact with the second drain region, and a second gate stacking structure positioned on the gallium oxide layer, wherein the second gate stacking structure comprises a second gate dielectric layer in contact with the gallium oxide layer and a second gate positioned on the second gate dielectric layer;
a first passivation layer and a second passivation layer, the first passivation layer encapsulating the enhancement mode device, the second passivation layer encapsulating the power device;
the through hole penetrates through the first passivation layer and the second passivation layer and exposes the first metal source electrode, the first metal drain electrode, the first grid electrode, the second metal source electrode, the second metal drain electrode and the second grid electrode;
the metal interconnection piece is located in the through hole, the first metal drain electrode is connected with the second metal source electrode through the metal interconnection piece, and the first metal source electrode is connected with the second grid electrode through the metal interconnection piece.
10. The heterogeneous integration based cascade structure of claim 9, wherein: the thickness of the gallium oxide layer is 0.01-10 mu m; the substrate comprises a Si substrate, a SiC substrate or a diamond substrate; the resistivity range of the substrate is larger than 10000 omega cm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211599584.XA CN115831877B (en) | 2022-12-12 | 2022-12-12 | Gallium oxide cascades structure based on heterogeneous integration and preparation method |
| PCT/CN2023/137554 WO2024125419A1 (en) | 2022-12-12 | 2023-12-08 | Gallium oxide cascade structure based on heterogeneous integration, and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211599584.XA CN115831877B (en) | 2022-12-12 | 2022-12-12 | Gallium oxide cascades structure based on heterogeneous integration and preparation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115831877A true CN115831877A (en) | 2023-03-21 |
| CN115831877B CN115831877B (en) | 2023-09-05 |
Family
ID=85546955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211599584.XA Active CN115831877B (en) | 2022-12-12 | 2022-12-12 | Gallium oxide cascades structure based on heterogeneous integration and preparation method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115831877B (en) |
| WO (1) | WO2024125419A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117276352A (en) * | 2023-11-23 | 2023-12-22 | 三峡智能工程有限公司 | Transistor structure, preparation method thereof, recording medium and system |
| WO2024125419A1 (en) * | 2022-12-12 | 2024-06-20 | 中国科学院上海微系统与信息技术研究所 | Gallium oxide cascade structure based on heterogeneous integration, and preparation method |
| CN118248646A (en) * | 2024-05-30 | 2024-06-25 | 杭州积海半导体有限公司 | Semiconductor device and method for manufacturing the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180269229A1 (en) * | 2015-09-21 | 2018-09-20 | Monolithic 3D Inc. | 3D Semiconductor Device and Structure |
| CN109427822A (en) * | 2017-08-28 | 2019-03-05 | 拉碧斯半导体株式会社 | The manufacturing method of semiconductor device and semiconductor device |
| CN113224155A (en) * | 2021-04-08 | 2021-08-06 | 中山大学 | Gallium nitride transistor with high conduction capability and preparation method thereof |
| US20220037515A1 (en) * | 2020-07-30 | 2022-02-03 | Xidian University | Bidirectional blocking monolithic heterogeneous integrated cascode-structure field effect transistor, and manufacturing method thereof |
| CN114582861A (en) * | 2022-03-09 | 2022-06-03 | 西安电子科技大学 | Single event effect reinforced printing transfer GaN/Ga2O3Cascode power device |
| CN114582862A (en) * | 2022-03-09 | 2022-06-03 | 西安电子科技大学 | Monolithic integration GaN/Ga2O3Cascode enhanced single-particle burnout resistant device and preparation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10991722B2 (en) * | 2019-03-15 | 2021-04-27 | International Business Machines Corporation | Ultra low parasitic inductance integrated cascode GaN devices |
| CN115831877B (en) * | 2022-12-12 | 2023-09-05 | 中国科学院上海微系统与信息技术研究所 | Gallium oxide cascades structure based on heterogeneous integration and preparation method |
-
2022
- 2022-12-12 CN CN202211599584.XA patent/CN115831877B/en active Active
-
2023
- 2023-12-08 WO PCT/CN2023/137554 patent/WO2024125419A1/en unknown
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180269229A1 (en) * | 2015-09-21 | 2018-09-20 | Monolithic 3D Inc. | 3D Semiconductor Device and Structure |
| CN109427822A (en) * | 2017-08-28 | 2019-03-05 | 拉碧斯半导体株式会社 | The manufacturing method of semiconductor device and semiconductor device |
| US20220037515A1 (en) * | 2020-07-30 | 2022-02-03 | Xidian University | Bidirectional blocking monolithic heterogeneous integrated cascode-structure field effect transistor, and manufacturing method thereof |
| CN113224155A (en) * | 2021-04-08 | 2021-08-06 | 中山大学 | Gallium nitride transistor with high conduction capability and preparation method thereof |
| CN114582861A (en) * | 2022-03-09 | 2022-06-03 | 西安电子科技大学 | Single event effect reinforced printing transfer GaN/Ga2O3Cascode power device |
| CN114582862A (en) * | 2022-03-09 | 2022-06-03 | 西安电子科技大学 | Monolithic integration GaN/Ga2O3Cascode enhanced single-particle burnout resistant device and preparation method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024125419A1 (en) * | 2022-12-12 | 2024-06-20 | 中国科学院上海微系统与信息技术研究所 | Gallium oxide cascade structure based on heterogeneous integration, and preparation method |
| CN117276352A (en) * | 2023-11-23 | 2023-12-22 | 三峡智能工程有限公司 | Transistor structure, preparation method thereof, recording medium and system |
| CN117276352B (en) * | 2023-11-23 | 2024-02-06 | 三峡智能工程有限公司 | Transistor structure, preparation method thereof, recording medium and system |
| CN118248646A (en) * | 2024-05-30 | 2024-06-25 | 杭州积海半导体有限公司 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115831877B (en) | 2023-09-05 |
| WO2024125419A1 (en) | 2024-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN115831877B (en) | Gallium oxide cascades structure based on heterogeneous integration and preparation method | |
| US10134640B1 (en) | Semiconductor device structure with semiconductor wire | |
| JP5475535B2 (en) | Horizontal HEMT and method for manufacturing horizontal HEMT | |
| TWI696242B (en) | Method for forming a thin semiconductor-on-insulator (soi) substrate | |
| CN111509041B (en) | Semiconductor device and method for manufacturing the same | |
| JP5405847B2 (en) | III-nitride monolithic power IC structure and manufacturing method thereof | |
| CN109300874B (en) | Parallel structure, manufacturing method thereof and electronic device comprising parallel structure | |
| JP2007533137A (en) | SOI (Semiconductor Conductor Insulator) Substrate and Device Formed from This Substrate | |
| TWI553743B (en) | Semiconductor device and method for manufacturing the same and method for manufacturing transistor | |
| CN108649071A (en) | Semiconductor devices and its manufacturing method | |
| KR20200092381A (en) | Systems and methods for integrated devices on machined substrates | |
| CN109841569A (en) | The gate structure and its method of gate contact and threshold voltage with enhancing | |
| CN110957257B (en) | Semiconductor-on-insulator substrate, method of forming the same, and integrated circuit | |
| CN110291645A (en) | Method and system for vertical-type power device | |
| CN113035783B (en) | Graphene device and GaN device heterogeneous integrated structure and preparation method thereof | |
| JP3534394B2 (en) | Complementary field effect transistor structure and method of manufacturing the same | |
| CN113113480A (en) | HEMT device with p-GaN cap layer and preparation method thereof | |
| US20150091021A1 (en) | Method of Manufacturing Semiconductor Device and the Semiconductor Device | |
| TWI747046B (en) | Capacitor structure amd fabricating method thereof and power semiconductor device | |
| CN108352408A (en) | The manufacturing method of semiconductor device, electronic unit, electronic equipment and semiconductor device | |
| CN113053742A (en) | GaN device and preparation method | |
| CN102725850B (en) | Body contacted transistor with reduced parasitic capacitance | |
| JP2006303393A (en) | Semiconductor device and manufacturing method thereof | |
| CN113035934B (en) | GaN-based HEMT device and preparation method thereof | |
| CN115663015B (en) | Semiconductor device structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |