CN113053742A - GaN device and preparation method - Google Patents

GaN device and preparation method Download PDF

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Publication number
CN113053742A
CN113053742A CN202110269241.6A CN202110269241A CN113053742A CN 113053742 A CN113053742 A CN 113053742A CN 202110269241 A CN202110269241 A CN 202110269241A CN 113053742 A CN113053742 A CN 113053742A
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layer
sio
metal
algan barrier
gan
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CN113053742B (en
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王文博
邱士起
周康
黄捷
马飞
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Zhejiang Jimaike Microelectronics Co Ltd
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Zhejiang Jimaike Microelectronics Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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Abstract

The invention provides a GaN device and a preparation method thereof, and SiO is formed on an epitaxial lamination layer2Layer of SiO2Forming a metal source and a metal drain on the layer by SiO2The affinity of the metal electrode is increased by layer, so that the metal electrode is higher than the conduction band energy level of the AlGaN barrier layer to eliminate the Schottky barrier of the metal-semiconductor material during contact, and electrons are injected into the AlGaN barrier layer mainly through an in-band tunneling process and do not pass through the Schottky barrier and SiO2The layer can effectively reduce ohmThe contact resistance improves the performance of the GaN device; according to the GaN device and the preparation method, in the process of forming the metal grid electrode, the groove with the preset depth is formed in the AlGaN barrier layer, and then the reserved AlGaN barrier layer is removed in the modes of pretreatment, oxidation and wet etching to expose the GaN channel layer, so that the nondestructive etching of grid electrode preparation can be realized, and the performance of the GaN device can be further improved.

Description

GaN device and preparation method
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a GaN device and a preparation method thereof.
Background
As a representative of the third generation semiconductor materials, gallium nitride (GaN) has many excellent characteristics such as a high critical breakdown electric field, high electron mobility, a high two-dimensional electron gas concentration, and good high-temperature operation ability. Therefore, third generation GaN-based semiconductor devices, such as High Electron Mobility Transistors (HEMTs), Heterojunction Field Effect Transistors (HFETs), etc., have been used, which have significant advantages especially in the fields of radio frequency, microwave, etc., where high power and high frequency are required.
The basic structure of the existing GaN device generally includes a substrate, a GaN channel layer, a barrier layer, an electrode and the like, and the material properties of each layer and related manufacturing process technology have important influences on the physical characteristics of the device, such as current collapse, current density, transconductance, gate leakage current, device reliability and the like.
In the preparation process of the electrode of the GaN device, the barrier layer is formed by the contact of the semiconductor material with the metal source electrode material and the metal drain electrode material, the ohmic contact is closely related to the performance of the GaN device, and the good ohmic contact is formed to be beneficial to the input and the output of current, so that how to reduce the ohmic contact resistance of the source electrode and the drain electrode in the GaN device is of great importance for preparing the GaN device with excellent performance. Furthermore, gate non-destructive etching is also a key to the fabrication of high performance GaN devices.
Therefore, it is necessary to provide a novel GaN device and a method for manufacturing the same.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a GaN device and a fabrication method thereof, which are used to solve the problem of the prior art that the performance of the GaN device is affected by the fabrication of electrodes.
To achieve the above and other related objects, the present invention provides a GaN device and a method for fabricating the same, comprising the steps of:
providing an epitaxial lamination layer, wherein the epitaxial lamination layer comprises a GaN channel layer and an AlGaN barrier layer which are stacked from bottom to top;
forming SiO on the epitaxial stack2A layer;
on the SiO2Forming a metal source and a metal drain on the layer;
dry etching with oxygen plasma gas to pattern the SiO2Exposing part of the AlGaN barrier layer;
performing dry etching by using chlorine-based plasma gas, patterning the AlGaN barrier layer, and forming a groove with a preset depth in the AlGaN barrier layer;
preprocessing is carried out, an oxide layer is formed, plasma oxidation and wet etching are carried out, the AlGaN barrier layer is removed from the groove, and a part of the GaN channel layer is exposed;
and forming a gate oxide dielectric layer and a metal gate in the groove.
Optionally, the SiO2The thickness of the layer is 2nm to 10 nm.
Optionally, the AlGaN barrier layer has a thickness of 20nm to 30nm, and the preset depth is 15nm to 20 nm.
Optionally, the oxide layer formed in the groove comprises Al2O3Layer or SiO2And the thickness of the oxide layer is 1 nm-3 nm.
Optionally, after the pretreatment and before the formation of the gate oxide dielectric layer, the step of forming the oxide layer and performing plasma oxidation and wet etching includes N times, where N is greater than or equal to 2.
Optionally, the chemical reagent to be pretreated is NH3:H2O, the volume ratio is 1: 6; the chemical reagent for wet etching is HCl H2O, the volume ratio is 1: 5.
Optionally, after the metal source and the metal drain are formed, a step of forming a SiN passivation layer is further included, and the thickness of the SiN passivation layer is 50nm to 300 nm.
The present invention also provides a GaN device, comprising:
the epitaxial lamination comprises a GaN channel layer and an AlGaN barrier layer which are stacked from bottom to top;
SiO2layer of said SiO2A layer on the epitaxial stack;
a metal source and a metal drain on the SiO2On the layer;
a groove between the metal source and the metal drain and penetrating the SiO2A layer and an AlGaN barrier layer exposing a portion of the GaN channel layer;
and the gate oxide dielectric layer and the metal grid are positioned in the groove.
Optionally, the SiO2The thickness of the layer is 2nm to 10 nm; the AlGaN barrier layer is 20 nm-30 nm thick.
Optionally, the SiO2The layer also comprises a SiN passivation layer, and the thickness of the SiN passivation layer is 50 nm-300 nm.
As described above, the GaN device and the fabrication method of the invention form SiO on the epitaxial stack2Layer of and on SiO2Forming a metal source and a metal drain on the layer to pass through SiO2The affinity of the metal electrode is increased by the layer, so that the metal source electrode and the metal drain electrode are higher than the conduction band energy level of the AlGaN barrier layer, the Schottky barrier of the metal-semiconductor material in contact is eliminated, electrons injected by the electrode can be mainly injected into the AlGaN barrier layer through the in-band tunneling process without passing through the Schottky barrier, and therefore, SiO2The layer can effectively reduce ohmic contact resistance and improve the performance of the GaN device; in addition, in the process of forming the metal grid electrode, the GaN device and the preparation method firstly form a groove with a preset depth in the AlGaN barrier layer, and then adopt a method of pretreatment, additional oxidation and wet etchingThe reserved AlGaN barrier layer is removed to expose the GaN channel layer, so that the nondestructive etching of grid preparation can be realized, and the performance of the GaN device can be further improved.
Drawings
FIG. 1 is a flow chart of a process for fabricating a GaN device according to an embodiment of the invention.
Fig. 2 is a schematic structural diagram of an embodiment of the present invention after an epitaxial stack is formed.
FIG. 3 illustrates the formation of SiO on an epitaxial stack in accordance with an embodiment of the present invention2Schematic structure after lamination.
FIG. 4 shows SiO in an embodiment of the present invention2The structure of the metal source and the metal drain are formed on the layer.
FIG. 5 shows SiO in an embodiment of the present invention2And the SiN passivation layer is formed on the layer.
Fig. 6 is a schematic structural diagram illustrating a groove with a predetermined depth formed in the embodiment of the present invention.
Fig. 7 is a schematic structural diagram of the embodiment of the invention after performing pretreatment, forming an oxide layer, performing plasma oxidation, and performing wet etching.
Fig. 8 is a schematic structural diagram after a gate oxide dielectric layer is formed in the embodiment of the invention.
Fig. 9 is a schematic structural diagram after forming a metal gate according to an embodiment of the invention.
FIG. 10 shows a metal electrode/SiO in an embodiment of the present invention2Energy level schematic of layer/AlGaN barrier layer.
Description of the element reference numerals
A 100-GaN channel layer; a 200-AlGaN barrier layer; 300-SiO2A layer; 401-a metal source; 402-metal drain; 500-SiN passivation layer; 601-a first groove; 602-a second groove; 700-a gate oxide dielectric layer; 800-metal gate.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, the present invention provides a method for fabricating a GaN device, comprising the steps of:
providing an epitaxial lamination layer, wherein the epitaxial lamination layer comprises a GaN channel layer and an AlGaN barrier layer which are stacked from bottom to top;
forming SiO on the epitaxial stack2A layer;
on the SiO2Forming a metal source and a metal drain on the layer;
dry etching with oxygen plasma gas to pattern the SiO2Exposing part of the AlGaN barrier layer;
performing dry etching by using chlorine-based plasma gas, patterning the AlGaN barrier layer, and forming a groove with a preset depth in the AlGaN barrier layer;
preprocessing is carried out, an oxide layer is formed, plasma oxidation and wet etching are carried out, the AlGaN barrier layer is removed from the groove, and a part of the GaN channel layer is exposed;
and forming a gate oxide dielectric layer and a metal gate in the groove.
In the method for manufacturing the GaN device of this embodiment, the SiO layer is formed on the epitaxial stack2Layer of and in the SiO2Forming the metal source and drain on the layer to pass through the SiO2The layer is pulled up to the affinity of the metal electrode, so that the metal source electrode and the metal drain electrode are higher than the conduction band energy level of the AlGaN barrier layer, the Schottky barrier of the metal-semiconductor material in contact is eliminated, electrons injected by the electrode can be mainly injected into the AlGaN barrier layer through an in-band tunneling process without passing through the Schottky barrier, and therefore, the SiO gas is injected into the AlGaN barrier layer2The layer can effectively reduce ohmic contact resistance and improve the performance of the GaN device; in addition, in the method for manufacturing the GaN device according to the embodiment, in the process of forming the metal gate, the groove with the preset depth is formed in the AlGaN barrier layer, and then the reserved AlGaN barrier layer is removed by adopting a pretreatment plus oxidation and wet etching mode to expose the GaN channel layer, so that the gate can be manufactured without damage, and therefore, the performance of the GaN device can be further improved.
Referring to fig. 2 to 10, the steps for fabricating the GaN device will be described below with reference to the accompanying drawings.
Referring to fig. 2, an epitaxial stack including a GaN channel layer 100 and an AlGaN barrier layer 200 stacked from bottom to top is first provided.
Specifically, the epitaxial stack may include a substrate (not shown), which may include one of a Si substrate, a SiC substrate, a GaN substrate, and a sapphire substrate, but the selection of the substrate is not limited thereto. Wherein, the substrate can adopt a Si (111) substrate to meet the requirement of saving cost, and the (111) oriented Si substrate is favorable for the growth of subsequent GaN material based on lattice adaptability, and the size of the substrate can adopt 8-inch wafers, 12-inch wafers and the like, which is not limited too. The epitaxial stack may then be formed on the substrate.
As an example, the epitaxial stack may include a buffer layer between the substrate and the GaN channel layer 100, and the buffer layer may include one or a combination of an AlGaN buffer layer and a GaN buffer layer.
Specifically, the epitaxial stack may include an AlN nucleation layer and a buffer layer on the substrate, so that the AlN nucleation layer serves as a seed layer, and the buffer layer may be used to alleviate lattice mismatch and thermal expansion coefficient mismatch between the channel layer and the substrate. Wherein the buffer layer may include one or a combination of an AlGaN buffer layer and a GaN buffer layer, and the AlGaN buffer layer may include a single layer or AlxGa1-xN laminated layers, wherein x is in a value range of 0 < x < 1 and is far away from Al of the GaN channel layer 100xGa1-xThe value of x of the N layer is larger than that of Al adjacent to the GaN channel layer 100xGa1-xN to mitigate lattice mismatch and cte mismatch issues between the substrate and the GaN channel layer 100; after the AlGaN buffer layer is formed, the GaN buffer layer with high resistance can be formed to form the GaN device with good leak-proof performance; and after the high-resistance GaN buffer layer is formed, an AlN back barrier layer can be formed to further improve the concentration of two-dimensional electron gas through the self-polarization capability of the back barrier layer, so that the GaN with good leak-proof performance and higher breakdown voltage can be preparedA device.
Next, referring to FIG. 3, SiO is formed on the epitaxial stack2Layer 300.
As an example, the SiO2The thickness of the layer 300 is 2nm to 10 nm.
Specifically, the SiO is formed2The method of layer 300 may include, but is not limited to, CVD or ALD, the SiO formed2 Layer 300 covers the AlGaN barrier layer 200, the SiO2The thickness of layer 300 may be 2nm, 5nm, 8nm, 10nm, etc.
Next, referring to FIG. 4, in the SiO2 A metal source 401 and a metal drain 402 are formed on layer 300.
Specifically, the forming regions of the metal source 401 and the metal drain 402 may be defined by photolithography, and then the SiO may be formed by depositing metal and stripping photoresist2The metal source 401 and the metal drain 402 are formed on the layer 300, and the material and the preparation method of the metal source 401 and the metal drain 402 are not limited herein.
This example is based on the SiO2The layer 300 can pull the affinity of the metal source 401 and metal drain 402 high above the conduction band energy level of the AlGaN barrier 200 to eliminate the schottky barrier when metal-semiconductor material is in contact, so that the electrons injected by the electrode can be injected into the AlGaN barrier 200 mainly by the in-band tunneling process without passing through the schottky barrier, and thus, the SiO can increase the affinity of the metal source 401 and metal drain 402 to the extent that the electrons injected by the electrode can be injected into the AlGaN barrier 200 without passing through the schottky barrier2Layer 300 can effectively reduce ohmic contact resistance, improve GaN device performance, metal electrode/SiO2The energy level schematic of the layer/AlGaN barrier layer can be seen in fig. 10.
Illustratively, the method further comprises a step of forming a SiN passivation layer 500, wherein the thickness of the SiN passivation layer 500 is 50 nm-300 nm.
Specifically, referring to fig. 5, the embodiment includes a step of forming the SiN passivation layer 500, and the SiN passivation layer 500 covers the SiO layer2The SiN passivation layer 500 of the layer 300 may serve as a protection layer to prevent damage to the semiconductor structure during the process. The SiN passivation layerThe thickness of 500 nm may be 50nm to 300nm, such as 50nm, 100nm, 200nm, 300nm, etc., but is not limited thereto.
Next, as shown in FIG. 6, the SiO is patterned by dry etching with ion gas2Part of the AlGaN barrier layer 200 is exposed from the layer 300, and the AlGaN barrier layer 200 is patterned by dry etching using chlorine-based plasma gas, and a groove having a predetermined depth H1 is formed in the AlGaN barrier layer 200.
Specifically, referring to fig. 6, in the present embodiment, since the SiN passivation layer 500 is included, the SiO layer is patterned2Patterning the SiO before layer 3002The step of layer 300 may specifically be comprised in the SiO2Forming a photoresist on the layer 300, defining a formation region required for the subsequent metal gate 800 by photolithography, and sequentially etching away the SiN passivation layer 500 and the SiO layer in the gate region by RIE dry etching2Layer 300 to reveal a portion of the AlGaN barrier layer 200. Then, removing a part of the AlGaN barrier layer 200 by ICP dry etching, and forming the groove with a preset depth H1 in the AlGaN barrier layer 200, wherein the etching comprises removing the SiN passivation layer 500 by fluorine-based plasma gas dry etching, and then removing the SiO by oxygen plasma gas dry etching2And removing most of the exposed AlGaN barrier layer 200 by etching the layer 300 by using a chlorine-based plasma gas dry method, as shown in FIG. 6, the preset depth of the AlGaN barrier layer 200 etched by the dry method is H1, and the AlGaN barrier layer 200 still has the AlGaN barrier layer 200 with the thickness of H2 after the dry etching, so that the GaN channel layer 100 is protected by the remained AlGaN barrier layer 200 with the thickness of H2, the GaN channel layer 100 is prevented from being damaged, and a first groove 601 is formed.
Illustratively, the AlGaN barrier layer 200 has a thickness of 20nm to 30nm, and the predetermined depth H1 is 15nm to 20 nm.
Specifically, the predetermined depth of the AlGaN barrier layer 200 that is dry etched away is H1, and the ratio H1: H2 of the thickness H2 of the AlGaN barrier layer 200 that remains is in a range of 4:1 to 2:1, such as 4:1, 3:1, 2:1, and the like. The AlGaN barrier layer 200 may have a thickness of 20nm, 25nm, 30nm, etc., the predetermined depth H1 may have a value of 15nm, 18nm, 20nm, etc., and the thickness H2 may have a value of 5nm to 10nm, such as 5nm, 8nm, 10nm, etc.
Next, as shown in fig. 7, a pretreatment is performed to form an oxide layer, and plasma oxidation and wet etching are performed to remove the AlGaN barrier layer 200 from the recess, thereby exposing a portion of the GaN channel layer 100.
As an example, the chemical reagent to be pretreated is NH3:H2O, the volume ratio is 1: 6; the chemical reagent for wet etching is HCl H2O, the volume ratio is 1: 5.
As an example, the oxide layer formed in the groove includes Al2O3Layer or SiO2And the thickness of the oxide layer is 1 nm-3 nm.
Specifically, O can be used2/N2The plasma oxidation is carried out, during which the time dependence of the thickness of the oxide layer depends on the diffusion of the oxidizing agent in the oxide layer and on the chemical reaction of the oxide layer/GaN interface. Wherein the thickness of the oxide layer may be 1nm, 2nm, 3nm, etc. Due to Al2O3The layer has low oxygen permeability and the oxidant diffuses much slower than the oxidation process, thus facilitating the complete reaction of the oxidant with the etched nitride surface, therefore, in this embodiment, the oxide layer is preferably made of Al2O3Layer, but is not so limited.
As an example, the steps of performing pretreatment, forming an oxide layer, performing plasma oxidation, and performing wet etching may include:
1. immersion in NH at 55 ℃3:H2In O, NH3:H2Cleaning for 5 minutes to remove impurities and residual photoresist, wherein the volume ratio of O is 1: 6;
2. depositing the oxide layer of 1 nm-3 nm including the Al2O3Or SiO2A layer;
3. by using O2/N2Performing plasma oxidation to oxidize the AlGaN barrier layer 200;
4. using HCl:H2And O, the volume ratio is 1:5, and the oxide layer is subjected to wet etching.
For example, after the pre-treatment and before the formation of the gate oxide dielectric layer, the steps of forming the oxide layer, performing plasma oxidation and wet etching may include N times, where N is greater than or equal to 2.
Specifically, after the pretreatment, after the oxide layer is formed once and the plasma oxidation and wet etching circulation steps are performed, that is, when N is 1, the oxidized barrier layer material with the thickness of 1nm to 5nm may be etched, so that the steps may be repeated as needed, that is, N is greater than or equal to 2, to expose the GaN channel layer 100, and form the second recess 602.
In this embodiment, the recess with the preset depth H1 is formed in the AlGaN barrier layer 200, and then the AlGaN barrier layer is removed in a manner of pretreatment, additional oxidation, and wet etching, so as to expose the GaN channel layer 100, thereby implementing lossless etching of gate preparation, and further improving the performance of the GaN device.
Next, referring to fig. 8 and 9, a gate oxide dielectric layer 700 and a metal gate 800 are formed in the recess.
Specifically, a photolithography process may be used to form the gate oxide dielectric layer 700 and the metal gate 800 in the groove, and the material and the preparation method of the gate oxide dielectric layer 700 and the metal gate 800 are not limited herein.
Referring to fig. 9, the present embodiment further provides a GaN device, which can be fabricated by the above fabrication method, but is not limited thereto, and details regarding the material and fabrication method of the GaN device are not described herein.
The GaN device of the embodiment, the SiO is formed on the epitaxial stack2Layer 300 of said SiO2The metal source 401 and metal drain 402 are formed on layer 300 to pass through the SiO2The layer 300 pulls the affinity of the metal source 401 and the metal drain 402 high, making the metal source 401 and the metal drain 402 higher than the conduction band energy level of the AlGaN barrier layer 300, so as to eliminate schottky of metal-semiconductor material when in contactA barrier such that electrons injected from an electrode can be injected into the AlGaN barrier layer 200 mainly through an in-band tunneling process without crossing a Schottky barrier, and thus, the SiO2The layer 300 can effectively reduce ohmic contact resistance and improve the performance of the GaN device.
Specifically, the GaN device includes:
an epitaxial stack comprising a GaN channel layer 100 and an AlGaN barrier layer 200 stacked from bottom to top;
SiO2layer 300 of SiO2A layer 300 is located on the epitaxial stack;
a metal source 401 and a metal drain 402, the metal source 401 and the metal drain 402 being located on the SiO2On the layer 300;
a groove between the metal source 401 and the metal drain 402 and penetrating the SiO2A layer 300 and an AlGaN barrier layer 200 exposing a portion of the GaN channel layer 100;
a gate oxide dielectric layer 700 and a metal gate 800, wherein the gate oxide dielectric layer 700 and the metal gate 800 are positioned in the groove.
As an example, the SiO2The thickness of layer 300 is 2nm to 10 nm; the AlGaN barrier layer 200 has a thickness of 20nm to 30 nm.
As an example, the SiO2The layer 300 further comprises a SiN passivation layer 500, wherein the thickness of the SiN passivation layer 500 is 50 nm-300 nm.
In summary, in the GaN device and the fabricating method of the present invention, the SiO is formed on the epitaxial stack2Layer of and in the SiO2Forming the metal source and drain on the layer to pass through the SiO2The layer raises the affinity of the metal source electrode and the metal drain electrode to enable the metal source electrode and the metal drain electrode to be higher than the conduction band energy level of the AlGaN barrier layer so as to eliminate the Schottky barrier of the metal-semiconductor material when in contact, so that electrons injected by the electrode can be mainly injected into the AlGaN barrier layer through an in-band tunneling process without passing through the Schottky barrier, and therefore, the SiO layer is formed2The layer can effectively reduce ohmic contact resistance and improve the GaN device performanceEnergy is saved; in addition, in the GaN device and the manufacturing method of the embodiment, in the process of forming the metal gate, the groove with the preset depth is formed in the AlGaN barrier layer, and then the reserved AlGaN barrier layer is removed by adopting a pretreatment plus oxidation and wet etching mode to expose the GaN channel layer, so that the gate can be etched without damage, and the performance of the GaN device can be further improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A preparation method of a GaN device is characterized by comprising the following steps:
providing an epitaxial lamination layer, wherein the epitaxial lamination layer comprises a GaN channel layer and an AlGaN barrier layer which are stacked from bottom to top;
forming SiO on the epitaxial stack2A layer;
on the SiO2Forming a metal source and a metal drain on the layer;
dry etching with oxygen plasma gas to pattern the SiO2Exposing part of the AlGaN barrier layer;
performing dry etching by using chlorine-based plasma gas, patterning the AlGaN barrier layer, and forming a groove with a preset depth in the AlGaN barrier layer;
preprocessing is carried out, an oxide layer is formed, plasma oxidation and wet etching are carried out, the AlGaN barrier layer is removed from the groove, and a part of the GaN channel layer is exposed;
and forming a gate oxide dielectric layer and a metal gate in the groove.
2. According to claim 1The preparation method of the GaN device is characterized by comprising the following steps: the SiO2The thickness of the layer is 2nm to 10 nm.
3. The method of manufacturing a GaN device according to claim 1, wherein: the AlGaN barrier layer is 20 nm-30 nm thick, and the preset depth is 15 nm-20 nm.
4. The method of manufacturing a GaN device according to claim 1, wherein: the oxide layer formed in the groove includes Al2O3Layer or SiO2And the thickness of the oxide layer is 1 nm-3 nm.
5. The method of manufacturing a GaN device according to claim 1, wherein: after the pretreatment and before the formation of the gate oxide dielectric layer, the steps of forming the oxide layer and performing plasma oxidation and wet etching comprise N times, wherein N is more than or equal to 2.
6. The method of manufacturing a GaN device according to claim 1, wherein: the chemical reagent for pretreatment is NH3:H2O, the volume ratio is 1: 6; the chemical reagent for wet etching is HCl H2O, the volume ratio is 1: 5.
7. The method of manufacturing a GaN device according to claim 1, wherein: and after the metal source electrode and the metal drain electrode are formed, a step of forming a SiN passivation layer is further included, and the thickness of the SiN passivation layer is 50 nm-300 nm.
8. A GaN device, characterized in that the GaN device comprises:
the epitaxial lamination comprises a GaN channel layer and an AlGaN barrier layer which are stacked from bottom to top;
SiO2layer of said SiO2A layer on the epitaxial stack;
metal source and drain, said metal source anda metal drain electrode is positioned on the SiO2On the layer;
a groove between the metal source and the metal drain and penetrating the SiO2A layer and an AlGaN barrier layer exposing a portion of the GaN channel layer;
and the gate oxide dielectric layer and the metal grid are positioned in the groove.
9. The GaN device of claim 8 wherein: the SiO2The thickness of the layer is 2nm to 10 nm; the AlGaN barrier layer is 20 nm-30 nm thick.
10. The GaN device of claim 8 wherein: the SiO2The layer also comprises a SiN passivation layer, and the thickness of the SiN passivation layer is 50 nm-300 nm.
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