CN116483154B - Low-delay reference output circuit and output method - Google Patents

Low-delay reference output circuit and output method Download PDF

Info

Publication number
CN116483154B
CN116483154B CN202310744553.7A CN202310744553A CN116483154B CN 116483154 B CN116483154 B CN 116483154B CN 202310744553 A CN202310744553 A CN 202310744553A CN 116483154 B CN116483154 B CN 116483154B
Authority
CN
China
Prior art keywords
circuit
pmos tube
low
trigger
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202310744553.7A
Other languages
Chinese (zh)
Other versions
CN116483154A (en
Inventor
卢泽垚
陈建球
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Hailichuang Technology Co ltd
Original Assignee
Shanghai Hailichuang Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hailichuang Technology Co ltd filed Critical Shanghai Hailichuang Technology Co ltd
Priority to CN202310744553.7A priority Critical patent/CN116483154B/en
Publication of CN116483154A publication Critical patent/CN116483154A/en
Application granted granted Critical
Publication of CN116483154B publication Critical patent/CN116483154B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)

Abstract

The invention provides a low-delay reference output circuit and an output method, comprising a reference voltage power supply circuit, a delay circuit, a trigger and a filter circuit; the trigger outputs different control signals to control the delay circuit to adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage input into the filter circuit according to the impedance states. In the low-resistance state, the reference voltage is quickly boosted after being connected into the filter circuit, so that the starting requirement of the circuit requiring quick starting is met.

Description

Low-delay reference output circuit and output method
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a low-delay reference output circuit and an output method.
Background
In integrated circuit design, the power supply voltage in the reference voltage power supply circuit needs to be filtered by the filter circuit to output a stable and reliable reference voltage for supplying power to other circuits or loads. In order to achieve the purpose, the resistor and the capacitor in the RC filter circuit are usually larger, but the larger resistor and the capacitor represent a larger time constant when the filter circuit filters, and cannot meet the starting requirement of the circuit requiring quick starting.
Disclosure of Invention
The invention aims to provide a low-delay reference output circuit and an output method, which realize quick boosting on the basis that the reference voltage output by a filter circuit has higher power supply rejection ratio and smaller noise.
The invention provides a low-delay reference output circuit; the circuit comprises a delay circuit, a trigger and a filter circuit;
the delay circuit includes a charging circuit;
when a high-level voltage is input to the D end of the trigger and the CK end of the trigger is in a rising edge, the charging circuit outputs a high-level signal to the RN end of the trigger, and the Q end of the trigger outputs a high-level signal to control the filter circuit to be in a low-resistance state so as to realize rapid boosting;
when the D end of the trigger inputs high-level voltage and the CK end of the trigger is at a rising edge, the charging circuit starts to charge, when the voltage rises to a threshold voltage, the charging circuit outputs a low-level signal to the RN end of the trigger, the trigger is reset, and the Q end of the trigger outputs a low-level signal to control the filter circuit to be in a high-resistance state for filtering.
Further, the circuit also comprises a reference voltage power supply circuit;
the reference voltage supply circuit supplies power to the delay circuit and outputs the reference voltage; the trigger outputs different control signals, the delay circuit is controlled to delay and adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage output by the reference voltage power supply circuit according to the impedance states.
Further, the D end of the D trigger is connected with a power supply voltage, the CK end is connected with a clock enabling signal, the RN end is connected with the delay circuit, and the Q end outputs a control signal to control the filter circuit to be in different impedance states.
Further, the reference voltage power supply circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first triode, a second triode, a first resistor, a second resistor, a third resistor, a fourth resistor and a comparator;
the power supply voltage is respectively connected to the source electrodes of the first PMOS tube and the second PMOS tube, the drain electrode of the first PMOS tube is connected with the emitter electrode of the first triode through the first resistor, the drain electrode of the second PMOS tube is connected with the emitter electrode of the second triode, the drain electrodes of the first PMOS tube and the second PMOS tube are respectively connected with the positive input end and the negative input end of the comparator, and the base electrodes of the first triode and the second triode are grounded; the second resistor and the third resistor are respectively connected to the positive input end and the negative input end of the comparator; the second resistor and the third resistor are also grounded; the collector electrodes of the first triode and the second triode are grounded;
the gates of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected in series and then connected to the output end of the comparator; and the source electrode of the third PMOS tube is connected with the power supply voltage, and the drain electrode of the third PMOS tube is grounded through the fourth resistor and connected with the filter circuit.
Further, the triggers are SR triggers, JK triggers and T triggers.
Further, the delay circuit further comprises a power supply circuit and a judging circuit;
the power supply circuit outputs voltage signals to the judging circuit and the charging circuit, controls the charging circuit to charge according to the conduction condition of the judging circuit, and outputs different level signals to the trigger according to the charging condition.
Further, the power supply circuit comprises a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube;
the grid electrodes of the sixth PMOS tube, the fifth PMOS tube and the fourth PMOS tube are respectively connected and then connected with the reference voltage power supply circuit, the power supply voltage is connected into the source electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the judging circuit and the charging circuit.
Further, the channel lengths of the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are the same.
Further, the power supply circuit further comprises a fourth PMOS tube and a fifth resistor;
and the source electrode of the fourth PMOS tube is connected with the power supply voltage, the grid electrode of the fourth PMOS tube is connected with the trigger, and the drain electrode of the fourth PMOS tube is connected with the judging circuit and the charging circuit through the fifth resistor.
Further, the power supply circuit further comprises a fourth PMOS tube;
and the source electrode of the fourth PMOS tube is connected with a current source between the power supply voltage, the grid electrode of the fourth PMOS tube is connected with a trigger, and the drain electrode of the fourth PMOS tube is connected with the judging circuit and the charging circuit.
Further, the judging circuit comprises an NMOS tube and a first inverter;
the CK end of the trigger is connected with the input end of the first inverter; the grid electrode of the NMOS tube is connected with the output end of the first phase inverter, the drain electrode of the NMOS tube is connected with the power supply circuit, and the source electrode of the NMOS tube is grounded.
Further, the charging circuit comprises a first capacitor and a second inverter;
the drain electrode of the fourth PMOS tube is connected with the input end of the second inverter, and the output end of the second inverter is connected with the RN end of the trigger; the drain electrode of the fourth PMOS tube is also connected with the first capacitor, and the lower polar plate of the first capacitor is grounded.
Further, the filter circuit is an RC filter circuit and comprises a switch, a fifth resistor and a second capacitor;
and after the first resistor and the switch are connected in parallel, one end of the first resistor is connected with the reference voltage power supply circuit, and the other end of the first resistor is grounded through a second capacitor and is connected with a load or other circuits.
The invention also provides a low-delay reference output method, which adopts the low-delay reference output circuit, and the method comprises the following steps:
the trigger outputs different control signals, the delay circuit is controlled to adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage input into the filter circuit according to the impedance states.
Further, a reference voltage supply circuit supplies power to the delay circuit and outputs the reference voltage; the trigger outputs different control signals, the delay circuit is controlled to delay and adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage output by the reference voltage power supply circuit according to the impedance states.
Further, when the CK end of the trigger is at a low level, the RN end is at a high level, and the Q end of the trigger outputs a low level;
when the D end of the trigger inputs high-level voltage and the CK end is at a rising edge, the charging circuit outputs a high-level signal to the RN end of the trigger, and the Q end of the trigger outputs high level;
when the CK end is at the rising edge, a charging node in a charging circuit starts to charge, and when the voltage of the charging node rises to the threshold voltage of an NMOS tube, the charging circuit outputs a low-level signal to the RN end, the trigger is reset, and the Q end outputs a low level.
Furthermore, the switching function is realized through the MOS tube.
Further, the charging node is a connection point between the drain electrode of the fourth PMOS transistor, the input end of the second inverter and the non-grounded end of the first capacitor;
when the D end inputs high-level voltage and the CK end is at the rising edge, the NMOS tube is not conducted; the Q end outputs a high-level control signal to control the switch to be closed, and the filter circuit is in a low-resistance state, so that quick boosting is realized;
when the voltage of the charging node rises to the threshold voltage of the NMOS tube, the second inverter outputs a low-level control signal to the RN end, the Q end outputs a low-level control switch to be disconnected, and the filter circuit is in a high-resistance state for filtering.
Further, the charging node is charged through the first capacitor.
Compared with the prior art, the invention has at least the following beneficial effects:
according to the invention, the trigger is controlled to reverse from outputting a high level to outputting a low level signal by setting the delay circuit to delay outputting the level signal, so that the filter circuit is switched from a high-resistance state to a low-resistance state rapidly, and when the filter circuit is in the low-resistance state, the reference voltage is switched into the filter circuit and then is boosted rapidly, and the starting requirement of the circuit which needs to be started rapidly is met.
Furthermore, the reference voltage is boosted before filtering, so that the resistance and the voltage of the filter circuit can take larger values when the circuit is filtered, the power supply rejection ratio of the reference voltage is improved, noise is reduced, and the circuit performance is improved.
Drawings
FIG. 1 is a block diagram of a low-delay reference output circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of another embodiment of a low-delay reference output circuit;
FIG. 3 is a schematic diagram of a circuit structure of a low-delay reference output circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of signal output from each end of a flip-flop and a charging node according to an embodiment of the invention;
FIG. 5 is a schematic diagram of another circuit structure of a low-delay reference output circuit according to an embodiment of the invention;
fig. 6 is a schematic diagram of another circuit structure of a low-delay reference output circuit according to an embodiment of the invention.
Detailed Description
The low-delay reference output circuit and the output method of the present invention will be described in conjunction with the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
The present embodiment provides a low-delay reference output circuit, please refer to fig. 1, which includes a delay circuit, a flip-flop and a filter circuit.
The trigger outputs different control signals to control the delay circuit to adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage input into the filter circuit according to the impedance states.
Further, referring to fig. 2, the reference voltage supply circuit is further included.
The reference voltage supply circuit supplies power to the delay circuit and outputs the reference voltage; the different control signals of the trigger control the delay circuit to delay and adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage output by the reference voltage power supply circuit according to the impedance states.
Specifically, the trigger is a D trigger, the D end of the D trigger is connected with a reference power supply, the CK end of the D trigger is connected with a clock enabling signal, the RN end outputs a high or low level signal through the delay circuit, and the Q end outputs a control signal to control the filter circuit to be in different impedance states.
It is understood that the flip-flop may be a D flip-flop, and may also be a SR flip-flop, a JK flip-flop, a T flip-flop, or the like.
The low-delay reference output circuit in this example includes a power supply circuit, a charging circuit, and a determination circuit.
The power supply circuit outputs voltage signals to the judging circuit and the charging circuit, controls the charging circuit to charge according to the conduction condition of the judging circuit, and outputs different level signals to the trigger according to the charging condition.
In addition, the delay circuit includes a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, an NMOS tube NM1, a first capacitor C1, a first inverter INV1, and a second inverter INV2.
Referring to fig. 3, gates of the fourth PMOS tube PM4, the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are respectively connected and then connected to a gate of the third PMOS tube PM3, a power supply voltage VDD is connected to a source of the sixth PMOS tube PM6, a drain of the sixth PMOS tube PM6 is connected to a source of the fifth PMOS tube PM5, a drain of the fifth PMOS tube PM5 is connected to a source of the fourth PMOS tube PM4, a drain of the fourth PMOS tube PM4 is connected to a drain of the NMOS tube NM1, the CK is connected to an input end of the first inverter INV1, a gate of the NMOS tube NM1 is connected to an output end of the first inverter INV1, and a source of the NMOS tube NM1 is grounded; the drain electrode of the fourth PMOS PM4 is further connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the RN end; the drain electrode of the fourth PMOS tube PM4 is also connected with the first capacitor C1, and the lower polar plate of the first capacitor C1 is grounded.
As can be seen from fig. 2, assuming that the connection point between the drain of the fourth PMOS transistor PM4, the input end of the second inverter INV2, and the non-grounded end of the first capacitor C1 is the charging node (point a), then:
referring to the timing chart shown in fig. 4 and fig. 3, when the D terminal of the flip-flop is at a high level (i.e. the power supply voltage VDD is connected), the Q terminal outputs a low level to control the switch S1 to be turned off. When the CK end is at the rising edge, the NMOS tube NM1 is not turned on, the current flows from the node B to the node a, the voltage of the charging node (point a) gradually changes from low to high, but the point a does not reach the threshold voltage Vth of the MOS tube, the RN end is connected to high level, the Q end outputs high level to control the switch S1 to be closed, and at this time, the filter circuit is in a low-resistance state to perform filtering. When the voltage at the point a rises to the threshold voltage Vth of the NMOS transistor NM1, the second inverter INV2 outputs a low level signal to the RN terminal, the Q terminal outputs a low level control switch S1 to be turned off, and the filtering circuit is in a high resistance state again to perform filtering.
In a specific example, the MOS transistor is an NMOS transistor NM1, and the threshold voltage Vth thereof may be 0.7V, that is, the inversion voltage of the second inverter INV2 is 0.7V.
Further, the channel lengths of the third PMOS tube PM3, the fourth PMOS tube PM4, the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are the same, and when certain matching performance is kept, the third PMOS tube PM3 can duplicate mirror currents for the fourth PMOS tube PM4, the fifth PMOS tube PM5 and the sixth PMOS tube PM6 in multiple numbers, so that the area of a current mirror is saved, and the preparation cost of a circuit is reduced.
In addition, the power supply circuit is further connected with a first inverter INV1, and the first inverter INV1 can control the on and off of the power supply circuit and the judging circuit.
Specifically, referring to fig. 5, the power supply circuit further includes a fourth PMOS tube PM4 and a fifth resistor R5.
In a specific example, the source electrode of the sixth PMOS PM6 is connected to the power supply voltage VDD, the base electrode is connected to the trigger, and the drain electrode is connected to the judging circuit and the charging circuit through the fifth resistor R5, that is, the fifth resistor R5 charges the first capacitor C1.
Furthermore, referring to fig. 6, the power supply circuit may be further connected to the fourth PMOS PM4 separately, and a current source idc l is connected between the source of the fourth PMOS PM4 and the power supply voltage VDD, where the current source idc l charges the first capacitor C1.
It can be appreciated that the present embodiment provides various delay circuit connection modes for performing diversified control of the flip-flop. The specific connection modes of the power supply circuit, the charging circuit and the judging circuit can be adjusted according to actual working conditions, and electronic elements in the power supply circuit, the charging circuit and the judging circuit can be replaced according to actual conditions.
Further, the first capacitor C1 is charged through the node a, and the charging time is a delay time, where the specific delay time is determined by the capacitance value of the first capacitor C1, the charging current, and the inversion voltage of the second inverter INV2.
In a specific example, the capacitance value of the first capacitor C1 is 10pF, and the time difference between closing and opening of the switch S1, i.e. the delay time, is 5-10 μs.
In addition, the filter circuit is an RC filter circuit and comprises a switch S1, a sixth resistor R6 and a second capacitor C2.
After the sixth resistor R6 and the switch S1 are connected in parallel, one end of the sixth resistor R6 is connected to the drain electrode of the third PMOS tube PM3 of the reference voltage power supply circuit, and the other end of the sixth resistor R6 is grounded through the second capacitor C2 and connected with a load or other circuits.
Specifically, when the switch S1 is closed, current is led to the load or other circuits through the switch S1, and rapid boosting of the other circuits or the load is completed. And when S1 is turned off, current is led into a load or other circuits through a sixth resistor R6, so that a filtering function is realized.
In the prior art, the reference voltage output by the filter circuit needs about 3 RC time constants, namely about 30 μs, when the reference voltage rises to 90% of the original reference voltage, and in the low-resistance state in this example, the switch S1 can be a MOS transistor, the on-resistance value of the MOS transistor is about 4Kohm, and when the switch S1 is opened, the reference voltage rising time is about 3 time constants, namely 0.12us, which is far smaller than the conventional 30 μs. As can be seen from the power consumption calculation formula p=u×i×t, compared with the power consumption when the conventional filter circuit powers on other circuits or loads, the power-on power consumption of the embodiment is smaller.
Preferably, the reference voltage supply circuit includes a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a first triode Q1, a first triode Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a comparator.
The power supply voltage VDD is respectively connected to the sources of the first PMOS tube PM1 and the second PMOS tube PM2, the drain electrode of the first PMOS tube PM1 is connected with the emitter electrode of the first triode Q1 through the first resistor R1, the drain electrode of the second PMOS tube PM2 is connected with the emitter electrode of the second triode Q2, the drains of the first PMOS tube PM1 and the second PMOS tube PM2 are respectively connected to the positive input end and the negative input end of the comparator, the base electrode of the first triode Q1 and the base electrode of the first triode Q2 are grounded, and the second resistor R2 and the third resistor R3 are respectively connected to the positive input end and the negative input end of the comparator; the second resistor R2 and the third resistor R3 are also grounded. The collectors of the first triode Q1 and the first triode Q2 are grounded.
The bases of the first PMOS tube PM1, the second PMOS tube PM2 and the third PMOS tube PM3 are connected and then connected to the output end of the comparator; the source electrode of the third PMOS tube PM3 is connected with the power supply voltage VDD, and the drain electrode is grounded through the fourth resistor R4 and connected with the filter circuit.
Specifically, the comparator enables the first PMOS tube PM1, the second PMOS tube PM2 and the third PMOS tube PM3 to have stable gate voltages, and simultaneously enables the fourth PMOS tube PM4, the fifth PMOS tube PM5 and the sixth PMOS tube PM6 to have stable gate input voltages.
Example two
The embodiment provides a low-delay reference output method, which comprises the following steps:
the trigger outputs a control signal to control the delay circuit to adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage input into the filter circuit according to the impedance states.
Further, the reference voltage supply circuit supplies power to the delay circuit and outputs the reference voltage; the trigger output control signal controls the delay circuit to delay and adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage output by the reference voltage power supply circuit according to the impedance states.
It will be appreciated that taking the D flip-flop as an example, when the CK terminal of the flip-flop is at a low level, the RN terminal is at a high level, and the Q terminal of the flip-flop outputs a low level.
When the D end of the trigger inputs high level voltage and the CK end is at a rising edge, the charging circuit outputs a high level signal to the RN end of the trigger, and the Q end of the trigger outputs high level.
When the CK end is at the rising edge, a charging node in a charging circuit starts to charge, when the voltage of the charging node rises to the threshold voltage Vth of the NMOS tube NM1, the charging circuit outputs a low-level signal to the RN end, the trigger is reset, and the Q end outputs a low level.
Further specifically, the connection point between the drain of the sixth PMOS tube PM6, the input end of the second inverter INV2, and the non-grounded end of the first capacitor C1 is point a.
When the D end of the trigger outputs high-level voltage and the CK end is in rising edge, the Q end outputs high-level control signal to control the switch S1 to be closed, and the filter circuit is in a low-resistance state, so that quick boosting is realized.
At this time, after the reference voltage is rapidly boosted and output is stable, other circuits or loads are enabled to work by means of the voltage.
Meanwhile, since the NMOS tube NM1 is not turned on, the power supply circuit starts to charge the charging node, and after the voltage of the charging node increases to the threshold voltage Vth of the NMOS tube NM1, the second inverter INV2 outputs a low level control signal to the RN end, the Q end outputs a low level control switch S1 to be turned off, and the filtering circuit is in a high resistance state to perform filtering.
At this time, most of the power supply rejection ratio and noise of the reference voltage are determined by the sixth resistor R6 and the capacitor C1, and the switch S1 does not affect.
In a specific example, the capacitance value of the second capacitor C2 includes, but is not limited to, approximately 10pF, and the resistance value of the sixth resistor R6 includes, but is not limited to, approximately 1Mohm, and different capacitors and resistors are selected according to the actual reference voltage. It can be seen that the capacitor and the voltage have larger values, so that the reference voltage can be ensured to have higher power supply rejection ratio and smaller noise, the variation of the reference voltage in different impedance states is reduced, and the stability of the output reference voltage is improved.
In summary, in this embodiment, a delay circuit is provided to delay the output level signal to control the flip-flop to invert from the output high level to the output low level signal, so as to realize the fast switching from the high-resistance state to the low-resistance state of the filter circuit, and the reference voltage is quickly boosted after being connected to the filter circuit, thereby meeting the starting requirement of the circuit requiring fast starting.
Furthermore, the resistance and voltage of the filter circuit in this embodiment can take larger values, so as to improve the power supply rejection ratio of the reference voltage and reduce noise, and improve the circuit performance.
Moreover, the delay circuit and the D trigger in the embodiment have small occupied area, so that the cost of the integrated circuit can be saved, the MOS tube is conducted for a short time, and the power consumption in switching is reduced.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (19)

1. The low-delay reference output circuit is characterized by comprising a delay circuit, a trigger, a reference voltage power supply circuit and a filter circuit;
the delay circuit includes a charging circuit;
when a high-level voltage is input to the D end of the trigger and the CK end of the trigger is at a rising edge, the charging circuit outputs a high-level signal to the RN end of the trigger, and the Q end of the trigger outputs a high-level signal to control the filter circuit to be in a low-resistance state so as to boost the reference voltage output by the reference voltage power supply circuit;
when the D end of the trigger inputs high-level voltage and the CK end of the trigger is in a rising edge, the charging circuit starts charging, when the voltage rises to a threshold voltage, the charging circuit outputs a low-level signal to the RN end of the trigger, the trigger is reset, the Q end of the trigger outputs a low-level signal, the filter circuit is controlled to be in a high-resistance state, and reference voltage output by the reference voltage power supply circuit is filtered.
2. A low delay reference output circuit as defined in claim 1,
the reference voltage supply circuit supplies power to the delay circuit and outputs the reference voltage; the trigger outputs different control signals, the delay circuit is controlled to delay and adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage output by the reference voltage power supply circuit according to the impedance states.
3. A low delay reference output circuit as claimed in claim 1 or 2, wherein the flip-flop is a D-flip-flop;
and the D end of the D trigger is connected with the power supply voltage, the CK end is connected with the clock enabling signal, the RN end is connected with the delay circuit, and the Q end outputs a control signal to control the filter circuit to be in different impedance states.
4. The low-delay reference output circuit of claim 2, wherein the reference voltage supply circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first triode, a second triode, a first resistor, a second resistor, a third resistor, a fourth resistor, and a comparator;
the power supply voltage is respectively connected to the source electrodes of the first PMOS tube and the second PMOS tube, the drain electrode of the first PMOS tube is connected with the emitter electrode of the first triode through the first resistor, the drain electrode of the second PMOS tube is connected with the emitter electrode of the second triode, the drain electrodes of the first PMOS tube and the second PMOS tube are respectively connected with the positive input end and the negative input end of the comparator, and the base electrodes of the first triode and the second triode are grounded; the second resistor and the third resistor are respectively connected to the positive input end and the negative input end of the comparator; the second resistor and the third resistor are also grounded; the collector electrodes of the first triode and the second triode are grounded;
the gates of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected in series and then connected to the output end of the comparator; and the source electrode of the third PMOS tube is connected with the power supply voltage, and the drain electrode of the third PMOS tube is grounded through the fourth resistor and connected with the filter circuit.
5. The low-delay reference output circuit of claim 1, wherein the flip-flops are SR flip-flops, JK flip-flops, and T flip-flops.
6. The low-delay reference output circuit of claim 1, wherein the delay circuit further comprises a power supply circuit and a decision circuit;
the power supply circuit outputs a voltage signal to the judging circuit and the charging circuit; and controlling the charging circuit to charge according to the conduction condition of the judging circuit, and outputting different level signals to the trigger according to the charging condition.
7. The low-delay reference output circuit of claim 6, wherein the power supply circuit comprises a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor;
the grid electrodes of the sixth PMOS tube, the fifth PMOS tube and the fourth PMOS tube are respectively connected and then connected with the reference voltage power supply circuit, the power supply voltage is connected into the source electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the judging circuit and the charging circuit.
8. The low-delay reference output circuit of claim 7, wherein channel lengths of a third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are the same.
9. The low delay reference output circuit of claim 6, wherein the power supply circuit further comprises a fourth PMOS transistor and a fifth resistor;
and the source electrode of the fourth PMOS tube is connected with the power supply voltage, the grid electrode of the fourth PMOS tube is connected with the trigger, and the drain electrode of the fourth PMOS tube is connected with the judging circuit and the charging circuit through the fifth resistor.
10. The low delay reference output circuit of claim 6, wherein the power supply circuit further comprises a fourth PMOS transistor;
and the source electrode of the fourth PMOS tube is connected with a current source between the power supply voltage, the grid electrode of the fourth PMOS tube is connected with a trigger, and the drain electrode of the fourth PMOS tube is connected with the judging circuit and the charging circuit.
11. The low-delay reference output circuit of claim 6, wherein the judging circuit comprises an NMOS transistor and a first inverter;
the CK end of the trigger is connected with the input end of the first inverter; the grid electrode of the NMOS tube is connected with the output end of the first phase inverter, the drain electrode of the NMOS tube is connected with the power supply circuit, and the source electrode of the NMOS tube is grounded.
12. The low delay reference output circuit of claim 1, wherein the charging circuit comprises a first capacitor and a second inverter;
the drain electrode of the fourth PMOS tube is connected with the input end of the second inverter, and the output end of the second inverter is connected with the RN end of the trigger; the drain electrode of the fourth PMOS tube is also connected with the first capacitor, and the lower polar plate of the first capacitor is grounded.
13. A low delay reference output circuit as claimed in claim 1 or 2, wherein the filter circuit is an RC filter circuit comprising a switch, a sixth resistor and a second capacitor;
and after the sixth resistor is connected with the switch in parallel, one end of the sixth resistor is connected with the reference voltage power supply circuit, and the other end of the sixth resistor is grounded through the second capacitor and is connected with a load or other circuits.
14. A low delay reference output method employing the low delay reference output circuit of any one of claims 1-13, the method comprising the steps of:
the trigger outputs different control signals, the delay circuit is controlled to adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage input into the filter circuit according to the impedance states.
15. A low latency reference output method according to claim 14,
the reference voltage supply circuit supplies power to the delay circuit and outputs the reference voltage; the trigger outputs different control signals, the delay circuit is controlled to delay and adjust the filter circuit to be in different impedance states, and the filter circuit boosts or filters the reference voltage output by the reference voltage power supply circuit according to the impedance states.
16. A low latency reference output method according to claim 14,
when the D end of the trigger inputs high-level voltage and the CK end is at a rising edge, the charging circuit outputs a high-level signal to the RN end of the trigger, and the Q end of the trigger outputs high level;
when the CK end is at the rising edge, a charging node in a charging circuit starts to charge, and when the voltage of the charging node rises to the threshold voltage of an NMOS tube, the charging circuit outputs a low-level signal to the RN end, the trigger is reset, and the Q end outputs a low level.
17. The low-delay reference output method of claim 16, wherein the switching function is implemented by a MOS transistor.
18. A low latency reference output method according to claim 16,
the charging node is a connection point between the drain electrode of the fourth PMOS tube, the input end of the second inverter and the non-grounding end of the first capacitor;
when the D end inputs high-level voltage and the CK end is at the rising edge, the NMOS tube is not conducted; the Q end outputs a high-level control signal to control the switch to be closed, and the filter circuit is in a low-resistance state, so that quick boosting is realized;
when the voltage of the charging node rises to the threshold voltage of the NMOS tube, the second inverter outputs a low-level control signal to the RN end, the Q end outputs a low-level control switch to be disconnected, and the filter circuit is in a high-resistance state for filtering.
19. A low delay reference output method as defined in claim 18, wherein said charging node is charged by a first capacitor.
CN202310744553.7A 2023-06-25 2023-06-25 Low-delay reference output circuit and output method Active CN116483154B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310744553.7A CN116483154B (en) 2023-06-25 2023-06-25 Low-delay reference output circuit and output method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310744553.7A CN116483154B (en) 2023-06-25 2023-06-25 Low-delay reference output circuit and output method

Publications (2)

Publication Number Publication Date
CN116483154A CN116483154A (en) 2023-07-25
CN116483154B true CN116483154B (en) 2023-09-12

Family

ID=87223559

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310744553.7A Active CN116483154B (en) 2023-06-25 2023-06-25 Low-delay reference output circuit and output method

Country Status (1)

Country Link
CN (1) CN116483154B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009195022A (en) * 2008-02-14 2009-08-27 Mitsumi Electric Co Ltd Dc-dc converter and semiconductor integrated circuit for controlling power supply
CN102195466A (en) * 2010-03-02 2011-09-21 登丰微电子股份有限公司 Anti-noise switching-type conversion circuit and controller thereof
CN103683907A (en) * 2012-09-12 2014-03-26 德克萨斯仪器股份有限公司 Fixed frequency DC to DC converter control circuit with improved load transient response
CN110771043A (en) * 2017-06-19 2020-02-07 派赛公司 Timing controller for dead time control
CN114744997A (en) * 2022-06-08 2022-07-12 深圳芯能半导体技术有限公司 Level shift circuit and integrated circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7054170B2 (en) * 2004-01-05 2006-05-30 System General Corp. Power-mode controlled power converter
JP2010146526A (en) * 2008-12-22 2010-07-01 Panasonic Corp Reference voltage generating circuit
JP5481161B2 (en) * 2009-10-30 2014-04-23 ルネサスエレクトロニクス株式会社 Semiconductor device and power supply device
US9696350B2 (en) * 2013-03-15 2017-07-04 Intel Corporation Non-linear control for voltage regulator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009195022A (en) * 2008-02-14 2009-08-27 Mitsumi Electric Co Ltd Dc-dc converter and semiconductor integrated circuit for controlling power supply
CN102195466A (en) * 2010-03-02 2011-09-21 登丰微电子股份有限公司 Anti-noise switching-type conversion circuit and controller thereof
CN103683907A (en) * 2012-09-12 2014-03-26 德克萨斯仪器股份有限公司 Fixed frequency DC to DC converter control circuit with improved load transient response
CN110771043A (en) * 2017-06-19 2020-02-07 派赛公司 Timing controller for dead time control
CN114744997A (en) * 2022-06-08 2022-07-12 深圳芯能半导体技术有限公司 Level shift circuit and integrated circuit

Also Published As

Publication number Publication date
CN116483154A (en) 2023-07-25

Similar Documents

Publication Publication Date Title
JP2504647B2 (en) Current source circuit
CN107276587B (en) Oscillator circuit with external synchronization function
CN108429445B (en) Soft start circuit applied to charge pump
CN107947539B (en) Switching power supply driving power supply circuit and switching power supply
CN107317568B (en) Oscillator for eliminating offset voltage of comparator
JP2014206825A (en) Bias circuit
CN101166021B (en) Controllable resistive circuit for providing a continuous variable resistance and filter circuit
WO2023134381A1 (en) Switch power source circuit and terminal device
CN116483154B (en) Low-delay reference output circuit and output method
CN115826660B (en) High-speed high-precision low-dropout linear voltage regulator starting circuit
CN115102384B (en) Soft start control circuit, control method thereof and power supply circuit
US20220407406A1 (en) High speed driver for high frequency dcdc converter
US20230083079A1 (en) Relaxation oscillator, integrated circuit and electronic apparatus
CN116131594A (en) Turn-off time generating circuit and chip
CN112350568B (en) Low-power-consumption high-switching-rate charge pump circuit
CN108599745B (en) Single-capacitor duty ratio controllable oscillator
CN109635943B (en) Digital-analog hybrid neuron circuit
CN210864451U (en) DC-DC converter
CN116436132B (en) Charging circuit and charging method
CN111354388B (en) Time sequence control module and power management chip
CN110858767B (en) Conversion circuit for phase-locked loop and method for forming conversion circuit
CN115498873B (en) Charge pump unit and chip
CN216649649U (en) Burr filter
CN111176366B (en) Wide-voltage memory current mirror circuit
CN116155250A (en) Load switch device and slow start control circuit thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant