CN116469768A - Forming method of groove type MOSFET device - Google Patents
Forming method of groove type MOSFET device Download PDFInfo
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- CN116469768A CN116469768A CN202310425767.8A CN202310425767A CN116469768A CN 116469768 A CN116469768 A CN 116469768A CN 202310425767 A CN202310425767 A CN 202310425767A CN 116469768 A CN116469768 A CN 116469768A
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- mosfet device
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 23
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000000969 carrier Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims 2
- 239000002131 composite material Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000006731 degradation reaction Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a method for forming a groove type MOSFET device, which belongs to the technical field of semiconductor devices and comprises the following steps: growing a layer of P-epitaxial layer on the P+ type silicon substrate; forming an N-type region on the P-epitaxial layer, and forming a groove extending into the epitaxial layer in the N-type region; forming a gate insulating film on the inner wall and bottom of the trench; depositing doped polysilicon in the gate insulating film as a gate electrode; the polysilicon is recessed into the trench, and the thickness of the polysilicon is lower than the surface of the N-type region; depositing an interlayer insulating film while doping the gate electrode; forming a contact hole in the interlayer insulating film to communicate the N-type region and the source region; performing a high temperature heat treatment on the wafer so that impurities in the interlayer insulating film diffuse into the N-type region to form a source region in contact with the trench; forming a source electrode by expanding a metal film over the entire wafer; and forming a drain region on the back of the P+ type silicon substrate by expanding metal. Suppressing diffusion of impurities from the source region to the gate insulating film, improving the breakdown voltage of the gate insulating film; the breakdown voltage degradation of the gate insulating film is eliminated.
Description
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a forming method of a groove type MOSFET device.
Background
With the rapid development of social economy, the demands of various social circles on electronic products are increasing, and the requirements on the performance of electronic devices are also increasing, so that innovative improvements are made from various aspects of the structure of the devices in order to improve the electronic performance of the devices.
In the prior art, the source region of the trench MOSFET device is formed by ion implantation, and the technique of the present invention is to form the source region by doping impurities in an interlayer insulating film while depositing the interlayer insulating film, and then performing a high temperature heat treatment to diffuse the impurities into an N-type region. This is a method capable of further improving the withstand voltage of the gate insulating film and eliminating the deterioration of the withstand voltage of the gate insulating film.
Such as trench MOSFET devices formed in accordance with prior art methods, can create problems during processing that can have an impact on device performance. For example, when a gate insulating film is grown by a thermal oxidation method, boron and phosphorus are absorbed by an oxide layer, holes of conductive carriers of a source region are injected into the oxide layer, traps are continuously increased in the oxide layer, and when the traps of the oxide layer are accumulated to a certain threshold value at local points, electrons can tunnel through the oxide layer through a plurality of traps of the oxide layer to form a tiny electric channel, so that the current of the oxide layer is suddenly increased. This reduces the withstand voltage of the gate insulating film; because of the structural feature of this trench MOSFET, that is, the source region and the gate electrode are opposed to each other via the insulating film, application of a large electric field to the portion where the gate insulating film is the weakest in withstand voltage further produces a detrimental structure that promotes breakdown of the gate insulating film.
Disclosure of Invention
In order to solve the above two problems, we propose a method for suppressing the diffusion of source carrier holes into the gate insulating film, improving the withstand voltage of the gate insulating film, and eliminating the withstand voltage degradation of the gate insulating film, i.e. a method for forming a trench MOSFET device.
The technical proposal of the invention is that, a forming method of a groove type MOSFET device,
(1) Preparing a P+ type silicon substrate;
(2) Growing a layer of P-epitaxial layer on the P+ type silicon substrate;
(3) Forming an N-type region on the epitaxial layer;
(4) Forming a groove extending into the epitaxial layer on the N-type region;
(5) Forming a gate insulating film on the inner wall and the bottom of the trench by a thermal oxidation method;
(6) Depositing doped polysilicon in the gate insulating film as a gate electrode;
(7) The polysilicon is recessed into the trench, and the thickness of the polysilicon is lower than the surface of the N-type region;
(8) Depositing an interlayer insulating film while doping the gate electrode;
(9) Forming a contact hole in the interlayer insulating film to communicate the N-type region and the source region;
(10) Performing a high temperature heat treatment on the wafer so that impurities in the interlayer insulating film diffuse into the N-type region to form a source region in contact with the trench;
(11) Depositing a metal film on the whole wafer to form a source electrode;
(12) Expanding metal on the back of the P+ type silicon substrate to form a drain region;
the gate electrode terminal G, the source electrode terminal S, and the drain electrode terminal D are connected to the gate electrode, the source electrode, and the drain electrode, respectively.
Further, an induced channel is arranged outside the groove and is used for carriers to reach the silicon substrate.
Further, the depth of the groove is 1-1.5 mu m.
Further, the insulating film thickness
Further, the polysilicon film thickness
Further, the thickness of the interlayer insulating film is 1.0-1.5 μm, and the doping concentration of the interlayer insulating film is 1E 18-1E 19/cm2.
Further, the heat treatment temperature is 900-1000 ℃.
Further, the concentration of the source region is 5E 19-2E 20/cm2, and the size of the source region is 0.1-0.3 mu m.
Compared with the prior art, the method has the following advantages that (1) the original injection mode of the source region forming mode is changed into the mode that impurities are doped in an interlayer insulating film between a grid electrode and a source electrode, and then the impurities are diffused into an N-type region through high-temperature heat treatment, so that the source region is formed. The one-step injection procedure is reduced, and the cost and the wafer flowing time are reduced. (2) Suppressing diffusion of impurities from the source region to the gate insulating film, improving the breakdown voltage of the gate insulating film; (3) A new structure is proposed that eliminates the voltage withstand degradation of the gate insulating film.
Drawings
FIG. 1 is a schematic view of the structure of the present invention, FIG. 1;
FIG. 2 is a schematic view of the structure of the present invention, FIG. 2;
FIG. 3 is a schematic view of the structure of the present invention, FIG. 3;
fig. 4 is a schematic structural view of the device of the present invention.
Wherein 1 is an epitaxial layer, 2 is an N-type region, 3 is a p+ -type silicon substrate, 4 is a trench, 5 is a silicon oxide insulating film, 6 is a gate electrode, 7 is a position where a source region is opposed to an interlayer insulating film, 8 is an interlayer insulating film, 9 is a contact hole, 10 is a source region, 11 is a source electrode, 12 is a drain region, and 13 is an induced channel.
Detailed Description
The technical scheme of the invention is further explained below with reference to the accompanying drawings,
taking a P-type semiconductor trench MOSFET as an example, as shown in fig. 1, 2 and 3:
(1) Preparing a P+ type silicon substrate 3;
(2) Growing an epitaxial layer 1 on a P+ type silicon substrate 3
(3) Forming an N-type region 2 on the epitaxial layer 1;
(4) Forming a trench 4 (trench depth 1-1.5 μm) extending into the epitaxial layer 1 on the N-type region;
(5) A silicon oxide insulating film 5 (silicon oxide insulating film thickness) is formed on the inner wall and bottom of the trench 4 )；
(6) Depositing doped polysilicon (polysilicon film thickness) in silicon dioxide insulating film) As a gate electrode 6;
(7) Then, the polysilicon is recessed into the trench 4, and the thickness of the polysilicon is lower than the surface of the N-type region 2;
(8) Then, the interlayer insulating film 8 is expanded while doping the gate electrode 6 (the thickness of the interlayer insulating film is 1.0-1.5 μm, the doping concentration of the interlayer insulating film is 1E 18-1E 19/cm 2);
(9) Forming a contact hole 9 in the interlayer insulating film 8 for communicating the N-type region and a source region 10 to be formed by diffusion;
(10) Then, carrying out heat treatment (the heat treatment temperature is 900-1000 ℃) on the wafer so that the impurity B in the 8 diffuses into the N-type region 2 to form a source region 10 (the concentration of the source region is 5E 19-2E 20/cm < 2 >, and the size of the source region is 0.1-0.3 mu m) which is in contact with the groove;
(11) Forming a source electrode 11 by expanding a metal film over the entire wafer;
(12) Expanding metal on the back of the metal layer 3 to form a drain region 12;
reference numeral 13 denotes an induced channel for a passage of carriers to the silicon substrate 1.
The gate terminal G, the source terminal S, and the drain terminal D are connected to the gate, the source, and the drain, respectively.
As shown in fig. 4, in the MOSFET device structure formed according to the above embodiments and steps, when the gate insulating film is grown by thermal oxidation, no gate insulating film is opposite to the source region, and no phenomenon of boron absorption and phosphorus removal occurs, and no fine electric channel is formed. Accordingly, the abrupt increase of the oxide current is completely eliminated, and the withstand voltage of the gate oxide film is improved. At the same time, the withstand voltage of the gate insulating film is not deteriorated.
Claims (8)
1. A method for forming a trench MOSFET device is characterized in that,
(1) Preparing a P+ type silicon substrate;
(2) Growing a P-type epitaxial layer on the P+ type silicon substrate;
(3) Forming an N-type region on the epitaxial layer;
(4) Forming a groove extending into the epitaxial layer on the N-type region;
(5) Forming an insulating film on the inner wall and the bottom of the trench by a thermal oxidation method;
(6) Depositing doped polysilicon in the insulating film as a gate electrode;
(7) The polysilicon is recessed into the trench, and the thickness of the polysilicon is lower than the surface of the N-type region;
(8) Depositing an interlayer insulating film while doping the gate electrode;
(9) Forming a contact hole in the interlayer insulating film to communicate the N-type region and the source region;
(10) Performing a high temperature heat treatment on the wafer so that impurities in the interlayer insulating film diffuse into the N-type region to form a source region in contact with the trench;
(11) Depositing a metal film on the whole wafer to form a source electrode;
(12) Depositing metal on the back of the P+ type silicon substrate to form a drain electrode;
the gate electrode terminal G, the source electrode terminal S, and the drain electrode terminal D are connected to the gate electrode, the source electrode, and the drain electrode, respectively.
2. The method of forming a trench MOSFET device of claim 1, wherein an induced channel is located outside of the trench for carriers to reach the silicon substrate.
3. The method of forming a trench MOSFET device of claim 1, wherein said trench depth is 1-1.5 μm.
4. The method of forming a trench MOSFET device of claim 1, wherein said insulating film thickness
5. The method of forming a trench MOSFET device of claim 1, wherein said polysilicon is thick
6. The method of forming a trench MOSFET device according to claim 1, wherein the interlayer insulating film is BPSG or USG or a composite of BPSG and SIN, and has a thickness of 1.0 to 1.5 μm and a doping concentration of 1E18 to 1E19/cm2.
7. The method of forming a trench MOSFET device of claim 1, wherein said heat treatment temperature is 900 ℃ to 1000 ℃.
8. The method of forming a trench MOSFET device of claim 1, wherein said source region concentration is between 5E19 and 2E20/cm2 and the source region size is between 0.1 and 0.3 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310425767.8A CN116469768A (en) | 2023-04-20 | 2023-04-20 | Forming method of groove type MOSFET device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310425767.8A CN116469768A (en) | 2023-04-20 | 2023-04-20 | Forming method of groove type MOSFET device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116469768A true CN116469768A (en) | 2023-07-21 |
Family
ID=87174828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310425767.8A Pending CN116469768A (en) | 2023-04-20 | 2023-04-20 | Forming method of groove type MOSFET device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116469768A (en) |
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2023
- 2023-04-20 CN CN202310425767.8A patent/CN116469768A/en active Pending
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