CN116454098A - Flexible copper indium gallium selenide/crystalline silicon laminated solar cell module and preparation method thereof - Google Patents
Flexible copper indium gallium selenide/crystalline silicon laminated solar cell module and preparation method thereof Download PDFInfo
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- CN116454098A CN116454098A CN202310264549.0A CN202310264549A CN116454098A CN 116454098 A CN116454098 A CN 116454098A CN 202310264549 A CN202310264549 A CN 202310264549A CN 116454098 A CN116454098 A CN 116454098A
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- indium gallium
- copper indium
- crystalline silicon
- battery
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- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 148
- KTSFMFGEAAANTF-UHFFFAOYSA-N [Cu].[Se].[Se].[In] Chemical compound [Cu].[Se].[Se].[In] KTSFMFGEAAANTF-UHFFFAOYSA-N 0.000 title claims abstract description 71
- 238000002360 preparation method Methods 0.000 title abstract description 58
- HVMJUDPAXRRVQO-UHFFFAOYSA-N copper indium Chemical compound [Cu].[In] HVMJUDPAXRRVQO-UHFFFAOYSA-N 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000004806 packaging method and process Methods 0.000 claims abstract description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 57
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 57
- 239000010703 silicon Substances 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 51
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 48
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000013078 crystal Substances 0.000 claims abstract description 43
- ZZEMEJKDTZOXOI-UHFFFAOYSA-N digallium;selenium(2-) Chemical compound [Ga+3].[Ga+3].[Se-2].[Se-2].[Se-2] ZZEMEJKDTZOXOI-UHFFFAOYSA-N 0.000 claims abstract description 33
- 230000008569 process Effects 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 288
- 238000005530 etching Methods 0.000 claims description 39
- 229920006280 packaging film Polymers 0.000 claims description 30
- 239000012785 packaging film Substances 0.000 claims description 30
- 238000005520 cutting process Methods 0.000 claims description 27
- 238000010329 laser etching Methods 0.000 claims description 24
- 239000011521 glass Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000009459 flexible packaging Methods 0.000 claims description 16
- 239000011265 semifinished product Substances 0.000 claims description 15
- 239000004642 Polyimide Substances 0.000 claims description 14
- 229920001721 polyimide Polymers 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- -1 polyethylene terephthalate Polymers 0.000 claims description 10
- 239000002346 layers by function Substances 0.000 claims description 9
- 230000003287 optical effect Effects 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 8
- 239000004372 Polyvinyl alcohol Substances 0.000 claims description 7
- 239000011112 polyethylene naphthalate Substances 0.000 claims description 7
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 7
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 7
- 229920002451 polyvinyl alcohol Polymers 0.000 claims description 7
- 239000010935 stainless steel Substances 0.000 claims description 7
- 229910001220 stainless steel Inorganic materials 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 238000010292 electrical insulation Methods 0.000 claims description 6
- 239000002861 polymer material Substances 0.000 claims description 6
- 239000002131 composite material Substances 0.000 claims description 5
- 239000011888 foil Substances 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 229910000599 Cr alloy Inorganic materials 0.000 claims description 3
- 229910001093 Zr alloy Inorganic materials 0.000 claims description 3
- GXDVEXJTVGRLNW-UHFFFAOYSA-N [Cr].[Cu] Chemical compound [Cr].[Cu] GXDVEXJTVGRLNW-UHFFFAOYSA-N 0.000 claims description 3
- QZLJNVMRJXHARQ-UHFFFAOYSA-N [Zr].[Cr].[Cu] Chemical compound [Zr].[Cr].[Cu] QZLJNVMRJXHARQ-UHFFFAOYSA-N 0.000 claims description 3
- 239000000788 chromium alloy Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 claims description 3
- 229910000640 Fe alloy Inorganic materials 0.000 claims description 2
- 229910001260 Pt alloy Inorganic materials 0.000 claims description 2
- 229910000676 Si alloy Inorganic materials 0.000 claims description 2
- 229910001215 Te alloy Inorganic materials 0.000 claims description 2
- ZUPBPXNOBDEWQT-UHFFFAOYSA-N [Si].[Ni].[Cu] Chemical compound [Si].[Ni].[Cu] ZUPBPXNOBDEWQT-UHFFFAOYSA-N 0.000 claims description 2
- XRBURMNBUVEAKD-UHFFFAOYSA-N chromium copper nickel Chemical compound [Cr].[Ni].[Cu] XRBURMNBUVEAKD-UHFFFAOYSA-N 0.000 claims description 2
- BIJOYKCOMBZXAE-UHFFFAOYSA-N chromium iron nickel Chemical compound [Cr].[Fe].[Ni] BIJOYKCOMBZXAE-UHFFFAOYSA-N 0.000 claims description 2
- WBLJAACUUGHPMU-UHFFFAOYSA-N copper platinum Chemical compound [Cu].[Pt] WBLJAACUUGHPMU-UHFFFAOYSA-N 0.000 claims description 2
- 238000003698 laser cutting Methods 0.000 claims description 2
- 229910000623 nickel–chromium alloy Inorganic materials 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 238000010248 power generation Methods 0.000 abstract description 16
- 238000006243 chemical reaction Methods 0.000 abstract description 10
- 230000008901 benefit Effects 0.000 abstract description 3
- 210000004027 cell Anatomy 0.000 description 212
- 239000000463 material Substances 0.000 description 36
- 239000010408 film Substances 0.000 description 22
- 238000004544 sputter deposition Methods 0.000 description 21
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052698 phosphorus Inorganic materials 0.000 description 14
- 239000011574 phosphorus Substances 0.000 description 14
- 239000000741 silica gel Substances 0.000 description 14
- 229910002027 silica gel Inorganic materials 0.000 description 14
- 239000003431 cross linking reagent Substances 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- QNWMNMIVDYETIG-UHFFFAOYSA-N gallium(ii) selenide Chemical compound [Se]=[Ga] QNWMNMIVDYETIG-UHFFFAOYSA-N 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 229910052711 selenium Inorganic materials 0.000 description 7
- 239000011669 selenium Substances 0.000 description 7
- 238000001228 spectrum Methods 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000000137 annealing Methods 0.000 description 5
- 239000002585 base Substances 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 239000013077 target material Substances 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000006096 absorbing agent Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000499 gel Substances 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 229910052717 sulfur Inorganic materials 0.000 description 4
- 239000011701 zinc Substances 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000004205 dimethyl polysiloxane Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000011282 treatment Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000006750 UV protection Effects 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000032683 aging Effects 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 210000003850 cellular structure Anatomy 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000005482 strain hardening Methods 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000282414 Homo sapiens Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000005922 Phosphane Substances 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000003712 anti-aging effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
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- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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- 238000005260 corrosion Methods 0.000 description 1
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- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000007770 graphite material Substances 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- 229910001092 metal group alloy Inorganic materials 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011224 oxide ceramic Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910000064 phosphane Inorganic materials 0.000 description 1
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- 238000007704 wet chemistry method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 210000002268 wool Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/142—Energy conversion devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/032—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
- H01L31/0322—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312 comprising only AIBIIICVI chalcopyrite compounds, e.g. Cu In Se2, Cu Ga Se2, Cu In Ga Se2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
- H01L31/03926—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate comprising a flexible substrate
- H01L31/03928—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate comprising a flexible substrate including AIBIIICVI compound, e.g. CIS, CIGS deposited on metal or polymer foils
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Sustainable Energy (AREA)
- Sustainable Development (AREA)
- Life Sciences & Earth Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention discloses a flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module, which comprises a bottom crystalline silicon cell and a top copper indium gallium diselenide cell connected through an intermediate connecting layer, wherein the back surface of the bottom crystalline silicon cell is provided with a flexible substrate packaging layer, a lead wire of the bottom crystalline silicon cell is led out from the substrate packaging layer, the top copper indium gallium diselenide cell and the intermediate connecting layer are etched and cut into laminated cell units with small areas, and only the flexible substrate packaging layer is reserved and not cut; the structure of each laminated cell unit is that the top layer copper indium gallium selenide cells of each 1 cell correspond to n bottom layer crystal silicon cells, and the number of the top layer copper indium gallium selenide cells is more than or equal to 10 and more than or equal to 2. Its preparing process is also disclosed. The battery structure of the invention can effectively improve the photoelectric conversion efficiency and the power generation of the flexible laminated battery assembly, and the preparation method can exert the advantage characteristics of large-area preparation of the copper indium gallium selenide film battery, has simple preparation process and low production cost, and is suitable for industrialization.
Description
Technical Field
The invention relates to a flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module and a preparation method thereof, and belongs to the technical field of solar cells.
Background
With the continuous and intensive research of human beings in the field of solar cells, the photoelectric conversion efficiency of single-junction solar cells (such as crystalline silicon cells and thin film cells of cadmium telluride, copper indium gallium selenide, perovskite and the like) is continuously improved and approaches the theoretical limit of Shockley-Queisser. By using different optical forbidden bandwidths (E g ) The structural design of the laminated solar cell formed by the materials of the solar cell can comprehensively widen the wave band range of the solar spectrum absorption and utilization of the cell, so that the cell efficiency breaks through the theoretical limit of Shockley-Queisser. However, the current preparation process of the laminated battery is still relatively complex, the preparation cost is high, the requirement of industrialized production cost still cannot be met, and the preparation process is required to be further simplified to reduce the preparation cost.
The flexible solar cell is a solar cell prepared on a flexible material substrate and is characterized by being bendable and foldable, light in application and flexible and wide in application range. However, the existing flexible solar cells are mainly single junction cells, such as copper indium gallium selenide cells, perovskite cells, organic solar cells and the like, and have insufficient photoelectric conversion efficiency, so that further application of the flexible solar cells is limited. Preparing laminated solar cells into flexible cells will further increase the competitiveness of flexible solar cells in the market and applications.
Disclosure of Invention
The invention aims to provide a flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module and a preparation method thereof.
The invention adopts the technical scheme that:
the flexible copper indium gallium selenide/crystalline silicon laminated solar cell module comprises a bottom layer crystalline silicon cell and is characterized by further comprising a top layer copper indium gallium selenide cell, wherein the bottom layer crystalline silicon cell is connected with the top layer copper indium gallium selenide cell through an intermediate connecting layer, a flexible substrate packaging layer is arranged on the back surface of the bottom layer crystalline silicon cell, a lead of the bottom layer crystalline silicon cell is led out of the substrate packaging layer, the top layer copper indium gallium selenide cell and the intermediate connecting layer are etched and cut into laminated cell units with small areas, and only the flexible substrate packaging layer is reserved and not cut;
the structure of each laminated cell unit is that the top layer copper indium gallium selenide cell of each 1 unit corresponds to n bottom layer crystal silicon cells through etching and cutting, and n is more than or equal to 10 and more than or equal to 2;
the substrate packaging layer is provided with a through hole for leading out an electrode lead;
the flexible packaging layer is positioned on the surface of the top-layer copper indium gallium selenide battery and is positioned on the outermost side of the back surface of the crystalline silicon battery;
the flexible substrate packaging layer is made of flexible stainless steel, flexible metal foil or flexible coated glass, or made of polymer material, wherein the polymer material is any one of polyethylene terephthalate, polyimide, polyethylene naphthalate and polyvinyl alcohol.
In the battery assembly of the invention, the top sub-battery is an optical forbidden bandwidth (E g ) Wider copper indium gallium selenide cells mainly utilize high energy (short wavelength) and medium energy (medium wavelength) photons in the solar spectrum. The bottom sub-cell is a crystalline silicon cell (E) g =1.12 eV), photons of medium and long bands of medium and low energy of the solar spectrum are mainly utilized. Therefore, photons in the wavelength ranges of short waves, medium waves and long waves in solar spectrums can be utilized more comprehensively and efficiently, so that the battery efficiency breaks through the theoretical limit of Shockley-Queisser, and the power generation capacity of the component is higher. The laminated battery component is a flexible solar battery, and expands the application field of the high-efficiency laminated solar battery. In addition, the invention also provides a novel structure of the flexible copper indium gallium selenide/crystalline silicon laminated solar cell module, and the structure can more effectively utilize the area of the active region of the top copper indium gallium selenide cell to carry out photovoltaic power generation, so that the photovoltaic current matching between the top copper indium gallium selenide cell and the bottom crystalline silicon cell in the flexible laminated cell can be realized, and the photoelectric conversion efficiency and the power generation of the flexible laminated solar cell module can be further effectively improved.
For the above-mentioned n values (i.e., the n crystalline silicon cells of the bottom layer), n is greater than or equal to 2, and the n values are specifically and flexibly determined according to the cell area of the crystalline silicon cells of the bottom layer: if the unit area of the bottom layer crystal silicon battery is the area of a conventional industrialized crystal silicon battery, n is generally smaller, for example, n=2 is a better choice; if the unit area of the bottom layer crystalline silicon cell is smaller than that of a conventional industrial crystalline silicon cell (such as half a slice, one third slice, … …, and n half a slice) after the conventional industrial crystalline silicon cell is manufactured, n can be larger.
For the area between every 2 crystal silicon batteries, when the intermediate connecting layer with large area and the top copper indium gallium selenide film battery are carried out after the preparation of the bottom crystal silicon battery module of the semi-finished product is finished, the surface, four sides and the adjacent intermediate area of every 2 crystal silicon batteries of the bottom crystal silicon battery are covered with the intermediate connecting layer material with large area and the film material of the top copper indium gallium selenide battery, so that the structure diagram of the laminated battery assembly is shown in fig. 3-b. It should be noted that, in the photovoltaic power generation of the laminated cell assembly, one of the photo-generated carriers generated by the four sides of the bottom layer crystalline silicon cell and the top layer copper indium gallium selenide cell in the middle area adjacent to each 2 crystalline silicon cells, such as photo-generated electrons (or holes), is firstly collected and led out by the front surface electrode of the top layer copper indium gallium selenide cell through the lateral transmission mode of the electron (or hole) transmission layer of the top layer cell; another photo-generated carrier, such as photo-generated hole (or electron), is transported to the upper side of the bottom layer cell by means of transverse transport in the middle connection layer, and then is recombined with the photo-generated electron (or hole) transported from the bottom layer crystalline silicon cell, thereby completing the photovoltaic power generation operation. Therefore, the four sides of the bottom layer of the crystalline silicon cells, and the top layer of the copper indium gallium selenide cells (the active region) in the middle region adjacent to each 2 crystalline silicon cells can be utilized for photovoltaic power generation.
The invention also discloses a preparation method of the flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module, which comprises the following steps:
(1) Preparing a semi-finished crystalline silicon cell only provided with a back electrode, and preparing a part of an intermediate connecting layer on the surface of the semi-finished crystalline silicon cell;
(2) And (3) carrying out laser edge isolation on the periphery of the semi-finished crystalline silicon battery, so that the periphery of the edge of the battery becomes an electrical insulation property.
(3) Conducting assembly lead wire of the back electrode;
(4) Etching electrode lead through holes and interconnection through holes distributed in patterns on a flexible substrate packaging film, leading out leads of a back electrode through the electrode lead through holes on the flexible substrate packaging film, and then packaging the semi-finished crystalline silicon battery on the flexible substrate packaging film in an array structure, so that a flexible substrate packaging layer is formed on the back surface of a bottom layer semi-finished crystalline silicon battery;
(5) Growing another part of a large-area intermediate connecting layer on the front surface of the bottom semi-finished crystalline silicon cell, wherein the area of the intermediate connecting layer can completely cover all the bottom semi-finished crystalline silicon cells on the flexible substrate packaging film, and the intermediate connecting layer has the function of enabling optical coupling and electrical coupling to be formed between the bottom crystalline silicon cell and the copper indium gallium selenide cell on the top layer;
(6) Preparing a top layer copper indium gallium selenide battery on the front surface of the middle connecting layer and a front electrode on the top of the top layer copper indium gallium selenide battery;
(7) Component lead of the front electrode is carried out;
(8) Etching and cutting are carried out on the top copper indium gallium selenide battery with a large area and the middle connecting layer, only the flexible substrate packaging layer is reserved and is not cut, the large-area battery is divided into a plurality of small-area laminated battery units which are independent in the longitudinal direction, the structure of each laminated battery unit is that the top copper indium gallium selenide battery of each 1 unit corresponds to n bottom crystal silicon batteries, and the number of the top copper indium gallium selenide batteries is more than or equal to 10 and more than or equal to 2, so that the laminated battery is obtained;
(9) And (5) interconnecting and packaging the laminated battery to prepare the flexible copper indium gallium diselenide/crystalline silicon laminated solar battery.
The scheme of the invention is illustrated from five aspects as follows: the method comprises the following steps of (a) general principles of a subcell structure, materials and preparation process of a flexible copper indium gallium diselenide/crystalline silicon laminated cell assembly, (b) a structure, materials and preparation process of a bottom flexible crystalline silicon cell assembly, (c) a middle layer performance requirement, a material selection and preparation process, (c) a structure, materials and preparation process of a top flexible copper indium gallium diselenide cell assembly, and (c) interconnecting and packaging laminated cells to finish the preparation of a final flexible laminated cell assembly.
1. General principles of subcell structure, materials and fabrication process for flexible CIGS/CIGS stacked cell assemblies
1. The flexible CIGS/crystalline silicon laminated cell assembly is of a series type, and can be of a 2-terminal (2T) series type or a 3-terminal (3T) series type. For a 2T type tandem type laminated cell, the bottom layer crystal silicon cell only needs to lead out one photo-generated carrier of electrons and holes, and the other photo-generated carrier is led out from the top layer copper indium gallium selenide cell. For a 3T type tandem type laminated cell, the bottom layer crystal silicon cell needs to simultaneously export electrons and holes, and the top layer copper indium gallium selenide cell can also simultaneously export one of the electrons and the holes.
In terms of material selection and corresponding preparation process, the requirements of the intermediate connection layer and the top layer copper indium gallium selenium battery assembly are as follows: individual parts of the already prepared bottom layer semi-finished flexible crystalline silicon cell assembly cannot be affected.
2. The preparation process of the flexible copper indium gallium diselenide/crystalline silicon laminated battery component is to flexibly combine the preparation processes of a bottom crystalline silicon battery, a top copper indium gallium diselenide battery and the component, and the preparation method is summarized as follows: (1) firstly, preparing a crystalline silicon semi-finished battery, and combining a preparation process of a crystalline silicon component, packaging an electrode lead and a back flexible substrate packaging layer on the back of the semi-finished crystalline silicon battery, so that a flexible 'bottom crystalline silicon battery module' is formed. (2) Based on the bottom flexible crystal silicon module in the description of (1), the middle connecting layer and the top copper indium gallium selenium battery with large area are prepared, and the bottom flexible crystal silicon module can be completely covered. (3) Etching and cutting are carried out on the top copper indium gallium selenide battery and the middle connecting layer with large area, and only the back flexible substrate packaging layer of the bottom flexible crystal silicon module is kept from being etched and cut; the copper indium gallium selenide battery (and the intermediate connecting layer) with the large area on the top layer is etched and cut into copper indium gallium selenide batteries with small areas, so that copper indium gallium selenide/crystal silicon laminated battery units with small areas which are independent and separated are formed one by one in the longitudinal direction, and the copper indium gallium selenide battery (and the intermediate connecting layer) on the top layer of 1 unit corresponds to n crystal silicon batteries on the bottom layer. (4) And finally, interconnecting and packaging the laminated battery to finish the preparation of the flexible CIGS/crystalline silicon laminated battery component.
Based on the above, the preparation process (and the corresponding material selection) of the middle connecting layer and the top copper indium gallium selenide battery module is selected and determined according to the material of the bottom flexible crystal silicon module of the prepared semi-finished product. The specific requirements are that the various parts of the finished "underlying flexible crystalline silicon module" including the underlying crystalline silicon cell, the metallized interconnect material, and the back-side encapsulated flexible substrate not be affected and destroyed. Specific preparation processes herein include high temperature heat treatment, physical bombardment and chemical reaction of vacuum vapor deposited films, wet chemistry, laser or plasma dry etching, and the like. On the basis of meeting the general principle, the material selection and the preparation process of the middle layer and the top layer copper indium gallium selenide battery module are not limited.
2. Structure, material and preparation process of bottom flexible crystalline silicon battery assembly
1. The bottom layer battery adopts a crystalline silicon battery, the forbidden bandwidth is 1.12eV, and photons of middle and low energy of solar spectrum in medium and long wave bands are mainly utilized. The silicon material substrate may be monocrystalline silicon or polycrystalline silicon, and the substrate doping type may be n-type (phosphorus doped) or p-type (boron doped or gallium doped).
2. The specific structure of the crystalline silicon cell assembly is not limited, but is selected according to the entire laminate cell terminal design. For the 2T series connection, an all-aluminum back surface field cell, PERC (passivated emitter and rear cell) cell, passivation contact TOPCon (Tunnel oxide and passivated contact) cell, silicon Heterojunction (HJT) cell, etc. can be employed, without being limited thereto. For the 3T tandem type, a back contact (Interdigited back contact, IBC) structure may be used, or MWT (Metal Wrap Through) or EWT (Emitter Wrap Through) cells may be used.
3. The area size of the crystalline silicon battery is not limited, and the currently industrialized popular 156mm, 182mm or 210mm side length can be adopted, and the area size can be cut into smaller areas (which can be determined according to application scenes), such as one half piece, one third piece, … …, one n-half piece and the like. It is emphasized that since the underlying crystalline silicon component needs to be made flexible, it is preferred to use smaller area crystalline silicon cells here.
4. The preparation process of the bottom flexible crystalline silicon battery component is not limited, and specifically, the following process links are needed to be completed: (1) the corresponding charge (electron or hole) transport layer preparation is completed, (2) the front surface of the underlying crystalline silicon cell need not be metallized, but the back surface need be metallized. (3) And packaging the component metallized leads on the back of the bottom-layer crystalline silicon battery and the packaging film of the back flexible substrate.
In the invention, the metallized interconnection material on the back of the bottom layer crystal silicon battery component can avoid oxidation in the subsequent preparation of the middle connecting layer and the top layer copper indium gallium selenide battery, thereby ensuring the interconnection performance of the laminated battery component. Here, a metal alloy having high electrical conductivity and high-temperature oxidation resistance, such as a copper-chromium alloy, a copper-chromium-zirconium alloy, a copper-chromium-tellurium alloy, a nickel-copper-silicon alloy, a copper-nickel-chromium alloy, or a nickel-chromium-iron alloy, a copper-platinum alloy, or the like, may be employed, and these alloys having good electrical conductivity also have excellent high-temperature oxidation resistance.
5. Flexible packaging technology for back of bottom layer crystalline silicon battery
And preparing the crystalline silicon semi-finished battery, and combining the preparation process of the crystalline silicon component, and packaging the metallized lead wire and the packaging film of the flexible substrate on the back of the crystalline silicon semi-finished battery, so that the bottom flexible crystalline silicon battery module of the laminated battery component is formed.
And (3) adopting two layers of packaging films for back flexible packaging after the metallization of the components on the back of the bottom-layer crystalline silicon battery is completed.
Wherein the first flexible packaging film, the back flexible substrate packaging layer (or the back flexible substrate layer) is used for short. The backside flexible substrate encapsulation layer needs to have good optical properties, as well as good reliability, including mechanical load resistance, attenuation and aging resistance, uv resistance, water and moisture resistance, etc. The flexible substrate may be selected from high molecular polymers, metals and alloys, flexible glass, and the like, and is not limited thereto. The organic high molecular polymer may be, for example, polyethylene terephthalate (PET), polyimide (PI), polyethylene naphthalate (PEN), polyvinyl alcohol (PVA), or the like, and is not limited thereto. The flexible metal or alloy substrate includes, but is not limited to, stainless steel, metal foil, and the like. The flexible glass may employ a flexible glass substrate suitable for solar photovoltaic. The preparation of the laminated cell component comprises the preparation of a bottom-layer crystalline silicon cell, the preparation of a top-layer copper indium gallium selenide cell and the packaging of the component, so that the flexible substrate is preferably selected from materials with good high temperature resistance. In the above flexible substrate material, the maximum applicable temperature of the flexible coated glass is 600 ℃, the maximum applicable temperature of PI (polyimide) is 300 ℃, the maximum applicable temperature of polyethylene naphthalate (PEN) is 180 ℃, the maximum applicable temperature of stainless steel is 1000 ℃, and so on.
The flexible substrate layer on the back side needs to be etched with a certain number of holes distributed in a pattern, and the holes are divided into two types. The first type of holes are called as electrode lead through holes for short, the patterns of the electrode lead through holes are distributed in the edge below the longitudinal direction of the semi-finished product crystalline silicon battery, and the specific pattern distribution of the electrode lead through holes can be designed according to the metal electrode distribution of the back surface of the semi-finished product crystalline silicon battery, and is not particularly limited. The purpose of the electrode lead through holes is to pass component metallization leads on the back side of the semi-finished crystalline silicon cell through these through holes. The second type of holes are called as interconnection through holes for short, and the patterns of the second type of holes are distributed below the longitudinal direction of the area between two adjacent semi-finished product crystal silicon batteries so as to interconnect different laminated battery units in the laminated battery assembly subsequently; it should be noted, however, that the interconnect vias cannot be distributed on the center line and on adjacent sides of the region between two adjacent stacked battery cells, but should be moderately offset from the center line in order not to be damaged (etched) during the etching and dicing process performed after the fabrication of the top-layer battery in the subsequent fabrication of the stacked battery. The diameter ranges of the electrode lead through holes and the interconnection through holes may be typically 0.2 to 1cm, and are not limited thereto. The etching opening process may be laser etching, plasma etching, or mechanical etching, but is not limited thereto.
Packaging the back flexible substrate layer. The bottom semi-finished crystalline silicon cell, the back flexible substrate layer (the component metallization leads on the back of the semi-finished crystalline silicon cell are passed through the electrode lead through holes), and the cross-linking agent are laid down and the package is completed. In this way, the metallized lead of the component on the back of the crystalline silicon cell passing through the back flexible substrate layer is isolated outside the back flexible substrate layer, and the metallized lead of the component on the back of the semi-finished crystalline silicon cell can be protected from being affected by the subsequent preparation process of the intermediate connection layer and the top copper indium gallium selenide cell. The crosslinking agent is not particularly limited, and commonly used crosslinking agents are used. The packaging process may be conventional lamination, or may be other methods, and is not particularly limited.
The second packaging film on the back is used as the flexible packaging film on the outermost layer of the back of the whole copper indium gallium diselenide/crystalline silicon laminated solar cell module. The back-side outermost flexible encapsulant layer needs to have good optical properties, as well as good reliability, including mechanical load resistance, attenuation and aging resistance, uv resistance, water and moisture resistance, and the like. The flexible substrate may be selected from high molecular polymers, metals and alloys, flexible glass, and the like, and is not limited thereto. The organic high molecular polymer may be, for example, polyethylene terephthalate (PET), polyimide (PI), polyethylene naphthalate (PEN), polyvinyl alcohol (PVA), or the like, and is not limited thereto. The flexible metal or alloy substrate includes, but is not limited to, stainless steel, metal foil, and the like. The flexible glass may employ a flexible glass substrate suitable for solar photovoltaic. The preparation of the laminated cell component comprises the preparation of a bottom-layer crystalline silicon cell, the preparation of a top-layer copper indium gallium selenide cell and the packaging of the component, so that the flexible substrate is preferably selected from materials with good high temperature resistance. In the above flexible substrate material, the maximum applicable temperature of the flexible coated glass is 600 ℃, the maximum applicable temperature of PI (polyimide) is 300 ℃, the maximum applicable temperature of polyethylene naphthalate (PEN) is 180 ℃, the maximum applicable temperature of stainless steel is 1000 ℃, and so on. And packaging the second flexible packaging film on the back, and packaging the second flexible packaging film and the front flexible packaging film of the top cell after the top cell of the laminated cell is prepared.
3. Intermediate layer performance requirements, material selection and preparation process
On the one hand, the material of the intermediate connection layer is required to enable the bottom-layer crystal silicon cell and the top-layer copper indium gallium selenide cell to have good optical coupling and electrical coupling, and the material of the intermediate connection layer is required to be selected according to the specific structures of the bottom-layer crystal silicon cell and the top-layer copper indium gallium selenide cell. On the other hand, the preparation process of the intermediate connecting layer cannot influence and destroy the prepared bottom flexible crystalline silicon battery module. On the basis of meeting the above conditions, the specific materials and preparation process of the intermediate connecting layer are not limited.
In the invention, the intermediate connecting layer can be of a composite structure and consists of a phosphorus doped polysilicon layer arranged on the surface of the bottom layer crystal silicon cell and a p-type heavily doped CIGS thin film layer grown in a large area.
Structure, material and preparation process of top-layer flexible copper indium gallium selenium battery assembly
1. The top flexible copper indium gallium selenide battery mainly utilizes photons with high energy (short wavelength) and medium energy (medium wavelength) in the solar spectrum, so that the forbidden bandwidth of the copper indium gallium selenide material can be designed. E can be regulated by adjusting the chemical composition of the CIGS film g A typical range is 1.0-1.65eV. Further, it is desirable to match the polarity of the copper indium gallium selenide cell electrode to the underlying crystalline silicon cell to form a tandem stack cell assembly. On the basis of meeting the requirements, the specific structure of the copper indium gallium selenide battery is not limited.
2. The top-layer copper indium gallium selenide battery mainly comprises a copper indium gallium selenide absorption layer, an electron transport layer, a hole transport layer, an interface passivation layer, an optical antireflection film, a metal electrode and the like. The preparation process of the top-layer copper indium gallium diselenide battery and the corresponding material selection are not particularly limited on the basis of not influencing and damaging the prepared bottom-layer flexible crystalline silicon battery module.
In the present invention, for some functional layers, such as copper indium gallium diselenide films, if annealing is required, laser annealing techniques can be used, because laser annealing is a cold working technique that does not affect and destroy the "bottom layer semi-finished crystalline silicon module" that has been prepared.
3. Etching and cutting of large-area copper indium gallium selenide/crystalline silicon laminated battery
After the preparation of the large-area middle connecting layer and the copper indium gallium selenide top layer battery is finished, etching and cutting are needed to be carried out on the large-area top layer copper indium gallium selenide battery and the middle connecting layer, and only the back flexible substrate packaging layer of the bottom layer crystal silicon module is kept from being etched and cut; in the etching dicing, it is necessary to dicing the center lines of the regions between adjacent continuous 2 times n underlying crystalline silicon cells (or some distance from the center lines) in the longitudinal space so that individual stacked battery cells are formed after dicing. Each laminated cell unit is composed of 1 top-layer copper indium gallium selenium cell with relatively large area and n bottom-layer crystal silicon cells as seen from the longitudinal space. In other words, in each independent stacked cell, one copper indium gallium diselenide cell of the top layer may correspond to n bottom layer crystalline silicon cells of the bottom layer, as seen in the longitudinal direction; the method is equivalent to connecting n crystal silicon batteries at the bottom in parallel and then connecting 1 copper indium gallium selenide battery at the top in series.
In this etching and cutting process, the functional layer films (including the charge transmission layer, the interface passivation layer, the copper indium gallium selenide absorption layer and the like) and the intermediate connection layer materials of the top-layer copper indium gallium selenide battery are selectively etched, while the etching and cutting process does not etch and cut the back substrate packaging layer of the bottom-layer crystalline silicon battery component. Therefore, there is a need for an etch cutting process that has a significant etch selectivity for the material to be etched and the material to be retained, while minimizing the cutting damage of the etch cutting process to the materials of the various parts of the fabricated laminate cell assembly. It is also noted here that the etch-cut process is not capable of etching and destroying the previously prepared interconnect vias. The cutting process may adopt laser etching, plasma etching or mechanical grooving, and the like, and is not limited thereto.
Typically, laser etching cutting techniques can be employed by selecting appropriate laser etching parametersTo achieve the selective etch cut described above. Nd: YVO can be generally used 4 The solid-state laser can select 355nm, 532nm or 1064nm laser wavelength, and is not limited to the above; pulse width is generally in the femtosecond, picosecond or nanosecond range, and is not limited thereto. In order to better realize the selective etching, alternatively, two times of laser etching with identical laser scanning etching patterns can be adopted, and part of the functional layer of the copper indium gallium selenide battery is etched by the first time of laser etching, and the other part of the functional layer and the large-area intermediate connecting layer are left to be not etched; and etching the other part of the functional layer and the large-area intermediate connecting layer by the second laser etching, and keeping the back flexible substrate packaging layer on the back of the bottom-layer crystalline silicon module not etched. In the selection of the two laser parameters, the technological parameters of the second laser etching can realize faster etching rate of the material to be etched, and the back flexible substrate packaging layer cannot be etched or has extremely weak etching capability. Nor is it limited thereto. See the examples for details.
Advantageous features in photovoltaic power generation
The novel flexible laminated cell structure has the advantages that the same partial area of the top layer copper indium gallium selenide cell seen from the longitudinal direction can generate photo-generated carriers to carry out photovoltaic power generation in the area between every n crystal silicon cells of the bottom layer, so that the area of an active area which can be used for photovoltaic power generation of the top layer copper indium gallium selenide cell is better utilized, the number of photo-generated carriers which can be generated in a laminated cell unit in unit area is effectively increased, and the performance of the laminated cell is effectively improved. Correspondingly, if a scheme that the conventional top-layer copper indium gallium selenide batteries are in one-to-one correspondence with the bottom-layer crystal silicon batteries is adopted, the same area of the top-layer copper indium gallium selenide batteries in the longitudinal space corresponding to the area between the adjacent n bottom-layer crystal silicon batteries can cause obvious waste.
The novel laminated cell structure is very suitable for the situation that the photo-generated current density of the top cell is slightly smaller than that of the bottom cell in the laminated solar cell. This is because, in the photovoltaic power generation operation of the tandem type stacked cell, the short-circuit current depends on the smaller one of the top layer cell and the bottom layer cell; that is, the cell photoelectric conversion efficiency is highly limited to a certain extent by the sub-cell in which the photo-generated current is smaller. Therefore, in order to make the photoelectric conversion efficiency of the stacked cell higher, it is often desirable that the current matching of the top cell and the bottom cell be matched to each other (i.e., that their respective photo-generated currents be as equal as possible). Since the bottom-layer crystalline silicon cell assemblies are always required to be distributed according to a certain interval in the back packaging, the area of the area between every two adjacent 2 or more crystalline silicon cells is obviously lost if a conventional one-to-one corresponding scheme is adopted for the same area of the top-layer cell corresponding to the area in the longitudinal direction. By adopting the novel etching and cutting scheme provided by the invention, the generated novel laminated battery structural design can more fully utilize the area of the active area of the top layer battery for photovoltaic power generation, so that the photo-generated current (photo-generated current = photo-generated current density multiplied by battery area) of the top layer copper indium gallium selenide battery is improved to a certain extent, the realization that the top layer battery and the bottom layer battery of the laminated battery form good current matching is more facilitated, and the whole laminated battery and the laminated assembly obtain higher battery photoelectric conversion efficiency and power generation. In addition, as more active area of the top layer battery can be fully utilized, the preparation cost of the laminated battery is reduced.
For copper indium gallium selenide/crystalline silicon laminate cells, compared to the underlying crystalline silicon cell (E g＝ 1.12 eV), top layer copper indium gallium selenium cell due to E g Wider, so it may be frequent that the top layer cell photo-generated current density is less than the bottom layer crystalline silicon cell photo-generated current density. Therefore, the novel laminated battery structure design provided by the invention has relatively strong practicability.
See for details the specific examples of implementation.
Fifthly, interconnecting and packaging the laminated batteries to finish the preparation of the final flexible laminated assembly
1. The packaging material of the front surface of the top flexible copper indium gallium selenide battery needs to have good optical anti-reflection performance, good anti-attenuation anti-aging performance, anti-ultraviolet performance, mechanical load performance, waterproof, dampproof and fireproof performance, acid and alkali resistance and other reliability on the basis of having flexibility. The specific encapsulating material is not limited, and typically, an inorganic encapsulating film having flexibility, such as flexible coated glass or the like, may be used.
For the cross-linking agent adopted in the packaging of the top-layer copper indium gallium selenide battery, the invention mainly adopts organic silica gel for packaging. It has excellent light transmittance, electrical insulation property, ultraviolet radiation resistance, high and low temperature resistance, chemical corrosion resistance, chemical stability, mechanical properties, and reliability. The organic silica gel also has good crosslinking property and sealing property. The solar cell module is packaged by using silica gel (instead of EVA cross-linking agent), and has excellent cross-linking property, sealing property, plasticity, ultraviolet radiation resistance, durability and electrical insulation property, so that the photovoltaic module is excellent in reliability and stable and efficient in working performance.
The organic silica gel is adopted to encapsulate the photovoltaic module, and the lamination process at 140-150 ℃ is not required, but the photovoltaic module can be cured at normal temperature and normal pressure, so that the prepared copper indium gallium selenide battery part and the bottom layer crystal silicon module are not affected and destroyed. The specific process method comprises the following steps: the organic silica gel is uniformly paved between the packaging material on the front surface of the top layer battery and the copper indium gallium selenide battery by adopting a method of dispensing, coating, spraying or spin coating (also without limitation), and then deep curing is carried out at room temperature and normal pressure, and the curing process can be accelerated by improving the pressure in the curing process. Since the silicon gel has good insulation, the silicon gel filled between the individual copper indium gallium diselenide/crystalline silicon laminated cells cut by the etching described above can also function as good electrical isolation between them. See the examples for details.
For the laminate battery, leads of front and rear electrodes of each laminate battery cell are interconnected. In particular interconnection, it is necessary to first pass the metallized leads on the back side of the stacked cells through the previously prepared interconnection vias and then interconnect the various stacked cells. The specific interconnection mode is not limited, and the internal series connection or parallel connection of the components can be performed according to the requirements of application scenes. And then, packaging the front flexible packaging film of the top-layer battery and the outermost flexible packaging film on the back by adopting silica gel.
2. And finally, carrying out frame sealing and junction box installation by adopting a conventional technical method to finally form the flexible CIGS/crystalline silicon laminated solar cell module.
The beneficial effects of the invention are as follows:
1) The flexible copper indium gallium selenide/crystalline silicon laminated solar cell module is composed of a top copper indium gallium selenide cell with a wide forbidden band and a bottom crystalline silicon cell with a narrow forbidden band, and photons in the wavelength ranges of short waves, medium waves and long waves in solar spectrums can be utilized more comprehensively and efficiently, so that high cell conversion efficiency and module power generation capacity are realized, and the flexible copper indium gallium selenide/crystalline silicon laminated solar cell module is suitable for different application environments (climate, geography, environment and the like).
2) The flexible copper indium gallium selenide/crystalline silicon laminated solar cell module can be flexibly prepared into a 2-terminal type or a 3-terminal type according to the requirements of application scenes, and the design is realized through the specific structure of the bottom crystalline silicon cell, so that the applicability and compatibility of the application scenes are flexibly widened.
3) The structure of the novel flexible copper indium gallium selenide/crystalline silicon laminated solar cell module provided by the invention can more effectively utilize the area of the active region of the top copper indium gallium selenide cell to carry out photovoltaic power generation, thereby helping to realize photo-generated current matching between the top copper indium gallium selenide cell and the bottom crystalline silicon cell in the flexible laminated cell, further effectively improving the photoelectric conversion efficiency and the power generation of the flexible laminated cell module and reducing the cell preparation cost.
4) The preparation process of the flexible laminated assembly fuses the preparation processes of the bottom layer battery, the top layer battery and the whole assembly, so that the advantage of large-area preparation of the copper indium gallium selenide film battery can be exerted, the preparation process is simple, the production cost is low, and the flexible laminated assembly is suitable for industrialization.
5) The flexible copper indium gallium diselenide/crystalline silicon solar cell can be bent and folded, is light in application, and expands the application scene of the high-efficiency laminated solar cell, so that the application of the high-efficiency laminated solar cell is wider and more flexible. Typically applied to building photovoltaics, the curvature of the laminate cell assembly may be designed to have the same profile curvature as the profile curvature of the building.
Drawings
Fig. 1 is a flow chart of a process for preparing a flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module.
Fig. 2 is a schematic view of a flexible copper indium gallium diselenide/crystalline silicon stacked solar cell module, which is a schematic view of a flexible cell module in a flat-laid state. Wherein 1 is the back 2 nd flexible packaging layer (i.e. the back outermost packaging layer), 2 is the back 1 st flexible packaging layer (i.e. the back flexible substrate packaging film), 3 is the bottom layer crystalline silicon cell back electrode, 4 is the component electrode lead through hole on the back of the bottom layer crystalline silicon cell, 5 is the component electrode lead on the back of the bottom layer crystalline silicon cell, 6 is the electron (or hole) transport layer, 7 is the crystalline silicon substrate, 8 is the hole (or electron) transport layer, 9 is the intermediate connection layer, 10 is the electron (or hole) transport layer, 11 is the copper indium gallium selenide absorption layer, 12 is the hole (or electron) transport layer, 13 is the front packaging layer, 14 is the electrode of the top layer copper indium gallium selenide cell, 15 is the electrode lead of the top layer copper indium gallium selenide front component package.
Fig. 3 is a schematic diagram before and after etching and cutting in the process of preparing the flexible copper indium gallium diselenide/crystalline silicon laminated battery assembly, and the flexible battery assembly is tiled. Wherein:
FIG. 3-a before etching and dicing. Wherein 1 is a bottom semi-finished product crystalline silicon cell, 2 is a large-area growth part of an intermediate connecting layer, 3 is a large-area top semi-finished product copper indium gallium selenium cell, and 4 is a back first packaging layer (namely a back flexible substrate packaging film).
Fig. 3-b, after the etching dicing, the second, new dicing method, continues to complete the front side package of the top layer copper indium gallium diselenide cell. The semiconductor device comprises a bottom layer of crystalline silicon battery 1, a large-area growth part of an intermediate connecting layer after etching and cutting, a top layer of copper indium gallium selenide battery 3 after etching and cutting, a back first layer of flexible packaging layer (namely a back flexible substrate packaging film), a front packaging layer 5, a back 2 nd layer of flexible packaging layer (namely a back outermost packaging layer), an electrode lead through hole 7 and an interconnection through hole 8. It should be noted that after the front packaging of the top-layer battery is completed, the space between each adjacent laminated battery cell is filled with the front packaging film and the cross-linking agent, and the front packaging film and the cross-linking agent have good electrical insulation, which is equivalent to the insulation effect between different laminated battery cells. Remarks: the top-layer copper indium gallium selenide cell of each cell is shown, and 2 bottom-layer crystalline silicon cells are arranged below the top-layer copper indium gallium selenide cell in the longitudinal direction, namely n=2; for the case where n is greater than 2, there are n underlying crystalline silicon cells below.
The invention is further described below with reference to the drawings and examples.
Detailed Description
Example 1 shows a flexible copper indium gallium diselenide/crystalline silicon tandem solar cell assembly (fig. 1 and 3) and a corresponding specific manufacturing process flow (fig. 2). The bottom layer of the crystalline silicon battery adopts a PERC battery, the bottom layer of the crystalline silicon battery adopts a copper indium gallium selenium battery, and the E of the absorption layer of the crystalline silicon battery g Is 1.67eV. The preparation process is as follows.
1. Firstly, preparing a semi-finished PERC battery module of a bottom layer, and specifically adopting the following process flow.
Step 1, selecting a p-type monocrystalline silicon piece with a crystal orientation of (100) 182mm, wherein the thickness of the silicon piece is 170 micrometers, and the resistivity is 1 Ω cm.
And 2, preparing a texture surface with a random pyramid morphology on the surface of the p-type silicon wafer by using an alkali texture making method. Adopting potassium hydroxide with mass concentration of 2-3%, and making wool for 5-7min at 70-75deg.C.
Step 3, preparing uniform n-type emitter junction on the front side of the p-type silicon wafer by adopting a method of implanting phosphorus by ion and annealing by combining with a furnace tube, wherein the phosphorus implantation energy is 10keV, and the dosage is 1.10 15 cm 2 The annealing temperature of the furnace tube is 830-850 ℃, the time is 30-40min, and the nitrogen atmosphere is adopted. Phosphorus surface doping concentration is 1 x 10 20 cm -3 The square resistance is 90-100 Ω/≡.
Step 4. At the p-type The front side of the silicon wafer continues to prepare the polysilicon with heavy doping phosphorus as a part of an intermediate connecting layer (a composite layer) of the copper indium gallium diselenide/crystalline silicon laminated battery. The preparation is carried out by PECVD, radio-frequency or microwave discharging, and the temperature is 400-500 ℃, and the process gas is phosphane, silane and hydrogen. And then the crystallization from amorphous silicon to polysilicon, and the activation and redistribution of phosphorus doping are completed through furnace tube annealing at 850-875 ℃ in the atmosphere of nitrogen. The thickness of the prepared phosphorus doped polysilicon layer is 75-100nm; the phosphorus surface concentration of the phosphorus doped polysilicon layer is 3 x 10 20 cm -3 The sheet resistance is 30-50Ω/≡. In this step, the amount of PECVD deposited phosphorus doped amorphous silicon that is plated around the back of the p-type silicon wafer is very small, and this effect can be subsequently eliminated by wet chemical etching.
And 5, etching the phosphorus doped junction diffused to the back surface of the p-type silicon wafer in the step 3 and the little phosphorus doped polysilicon plated in the step 4 by a mixed solution of nitric acid and hydrofluoric acid in combination with a wet etching process of water bleaching. Through the chemical etching, the suede on the back surface of the silicon wafer is etched into an acid polished surface. In the mixed solution of nitric acid and hydrofluoric acid, the mass concentration of the nitric acid is 40%, the mass concentration of the hydrofluoric acid is 4%, the temperature of the solution is 7 ℃, and the etching time is 15-30 seconds.
And 6, preparing a passivation film on the back surface of the p-type silicon wafer. Depositing an alumina and silicon nitride laminated film by adopting a PECVD (plasma enhanced chemical vapor deposition) process, wherein the thickness of the alumina is 5nm, and the refractive index is 1.65; the silicon nitride has a thickness of about 100nm and a refractive index of 2.0.
And 7, etching the aluminum oxide/silicon nitride laminated film on the back surface of the p-type silicon wafer by adopting a laser ablation process. The laser film-opening process parameters are Nd: YVO 4 The laser has a wavelength of 532nm, a pulse width of 15ps and a pulse repetition frequency of 200-1000KHz. The pattern of the laser film is designed by grid line distribution, the line width is 25-30 μm, the distance between two adjacent grid lines (between axes) is 1.6mm, and the pattern is the pattern of the aluminum back surface field doping area to be implemented later.
And 8, printing aluminum paste on the back surface of the p-type silicon wafer by adopting a screen printing technology, sintering by adopting a rapid heat treatment sintering furnace to form a back surface local aluminum back surface field and metal-semiconductor ohmic contact, wherein the sintering real peak temperature is 750 ℃, the time under the peak temperature is 2 to 4 seconds, and the atmosphere is compressed air.
And 9, performing laser edge isolation on the periphery of the semi-finished PERC battery to ensure that the periphery of the edge of the battery becomes an electrical insulation property.
Step 10, packaging the metallized lead wire of the assembly and the flexible substrate layer on the back of the bottom semi-finished crystalline silicon battery
Packaging the back of the prepared semi-finished product bottom PERC battery, firstly cutting the prepared semi-finished product PERC battery into half pieces (namely 1/2 pieces) by using a low-loss laser cutting technology, and then arranging 144 semi-finished product PERC half piece batteries into a 12 x 12 module array.
1) Firstly, the metal lead of the back aluminum electrode assembly adopts copper-chromium alloy or copper-chromium-zirconium alloy, which has good conductivity and excellent high-temperature oxidation resistance, so that oxidation in the subsequent preparation of the top-layer copper indium gallium selenide battery can be avoided, and the interconnection performance of the laminated battery assembly is ensured.
2) Backside flexible substrate layer package
The back flexible substrate packaging film adopts flexible coated glass with good flexibility and mechanical property, and needs to do the following two treatments: (1) And etching a certain number of electrode lead through holes and interconnection through holes distributed in a pattern on the flexible coated glass by adopting a low-damage laser etching technology, wherein the diameter of the electrode lead through holes can be 0.2-1 cm, and the diameter of the interconnection through holes can be generally larger than that of the electrode lead through holes according to the size of the leads. The pattern distribution of the electrode lead through holes is arranged in the edge of the longitudinal lower part of the semi-finished PERC battery, and the specific pattern distribution can be designed according to the distribution of metal electrodes on the back of the semi-finished PERC battery; the pattern of the interconnection through-holes is distributed longitudinally below the region between two adjacent laminated battery cells (but cannot be distributed at the center line and adjacent sides of the region between two adjacent laminated battery cells to avoid the interconnection through-holes from being damaged when cutting). The via etching may be accomplished using 355nm nanosecond laser technology. (2) After the through hole etching is finished, carrying out hydrofluoric acid cleaning treatment on the back flexible substrate packaging layer (flexible coated glass), wherein the HF mass fraction is 5% -10%, the time is 30-60 minutes, and then washing and drying are carried out, so that the blocking capability (not etched) on the 15 th step of laser etching cutting can be further enhanced.
Next, the component metallization leads on the back side of the semi-finished PERC cell are passed through electrode lead vias on the back side flexible substrate encapsulation film. The organic silica gel of the Dow Corning company applied to solar cell encapsulation is adopted as a cross-linking agent. And (3) arranging and paving the prepared semi-finished PERC battery and the back flexible substrate packaging film, namely the flexible coated glass, along a certain interval and an array form, and uniformly coating the organic silica gel between the semi-finished PERC battery and the back flexible coated glass by a dispensing method. And then deep curing is carried out for 1-2h at the temperature of 25-50 ℃ under the condition that nitrogen is adopted, so that the silica gel tightly adheres all parts together, and the semi-finished PERC battery, the organic silica gel and the back flexible coated glass are fully crosslinked, fixed and sealed. A curing lamination process with a slow increase in pressure may also be employed here to enhance the curing effect and accelerate the curing process. Thus, the preparation of the bottom flexible PERC crystal silicon module of the semi-finished product is completed.
2. Preparation of copper indium gallium selenium thin film battery with top layer and large area
Step 11, preparing p + CIGS back field and CIGS absorber layer
First, p is prepared + -CIGS back field, employing a Na doped CIGS thin film, wherein Na doping is used to form p-type heavy doping of the CIGS thin film as p-type + CIGS back field to enhance hole extraction and transport capability; at the same time the layer p + The CIGS back field together with the heavily doped phosphorus doped polysilicon prepared in step 4 above constitutes the intermediate connection layer (composite layer) of the copper indium gallium diselenide/silicon laminate cell. The copper indium gallium selenium four-element target is prepared by a direct current sputtering method, and a copper indium gallium selenium four-element target and a metal Na target are adopted, wherein the contents of the elements are respectively as follows: 1.5% Na,40.8% Cu,1% In,16.7% Ga,40% Se, and the purity is 99.999% or more. The temperature of the base is 25 ℃ at normal temperature, and the distance between the target and the substrate is 90mm. Background vacuum degree is 1.10 -4 Pa, the sputtering gas being argonGas (purity higher than 99.999%). Pre-sputtering for 5 minutes to remove thin layer oxide formed in air on the target; then sputter p + -CIGS layer, sputtering gas pressure 0.2Pa, sputtering power 500W, pulse frequency 100kHz.
And then preparing the CIGS absorbing layer by adopting a direct current sputtering method. The target is a copper indium gallium selenium quaternary target, wherein the contents of the elements are respectively as follows: 40.8% Cu,1% In,16.7% Ga,41.5% Se, and the purity is 99.999% or more. The temperature of the base is 25 ℃ at normal temperature, and the distance between the target and the substrate is 90mm. Background vacuum degree is 1.10 -4 Pa, the sputtering gas was argon (99.999%). Pre-sputtering for 5 minutes to remove thin layer oxide formed in air on the target; then, the CIGS absorber layer was sputtered at a sputtering pressure of 0.15Pa, a power of 450W, and a pulse frequency of 100kHz.
Then carrying out selenizing annealing on the CIGS film by adopting laser heat treatment, adopting a nanosecond pulse fiber laser, and having the wavelength of 1064nm, the pulse width of 220ns and the repetition frequency of 60kHz. N is introduced in the whole laser process 2 The carried selenium vapor is heated outside the laser processing chamber by adopting another chamber and N is used for heating the solid selenium source because the initial temperature of the sample processed by the laser processing needs to be kept at room temperature 2 Carrying into the laser processing process chamber. After selenizing treatment of laser annealing, the crystallinity of the CIGS film is well improved, the crystal grain size is uniform and grows, and the film is more compact. It should be emphasized that due to the local heat treatment properties of laser "cold working", only the copper indium gallium diselenide film will be subjected to laser heat treatment, while the prepared layers of material below the CIGS absorber layer will not be affected.
The thickness of the p-CIGS produced was 50nm, the CIGS absorber thickness was 1 micron, eg=1.67 eV.
And 12, preparing n-type Zn (S, O) serving as an electron transport layer by adopting a magnetron sputtering technology. The sputtering target material comprises ZnO, znS=40:60 and has purity higher than 99.99 percent. The temperature of the base is 25 ℃ at normal temperature, and the distance between the target and the substrate is 60mm. Background vacuum was 2 x 10 -4 Pa, the sputtering gas is a mixed gas of argon and oxygen (the purity is higher than 99.99 percent), wherein the oxygen accounts for 0.1 percent, and the sputtering pressure is 0.8Pa. Pre-sputtering for 2 minutesRemoving a thin oxide formed by the target material in the air; then sputtering Zn (S, O) layer with power of 80-100W. The thickness of n-Zn (S, O) is 50-60nm.
And 13, preparing a layer of transparent conductive oxide for improving the transmission capacity of photo-generated carriers, wherein the transparent conductive oxide is prepared by adopting aluminum-doped zinc oxide (AZO) through a magnetron sputtering technology. The target material is an aluminum tin oxide ceramic target with purity higher than 99.99%, wherein Al 2 O 3 Content 2wt.%. The temperature of the substrate is 25 ℃ at normal temperature, and the distance between the target substrates is 70-100mm. Background vacuum is lower than 1.10 - 4 Pa, sputtering atmosphere of Ar, O 2 And (3) mixing the gases. Pre-sputtering for 3min to remove thin layer oxide formed in air on the target. AZO was then sputtered at a sputtering pressure of 0.1Pa and a sputtering power of 300W. The thickness of the prepared AZO film is 150nm, the square resistance is 40-70 omega/≡and the average transmittance is 87%.
And 14, metallizing the front surface of the top-layer copper indium gallium selenide battery, and forming a grid line type Ag electrode by adopting magnetron sputtering metal Ag. The mask is made of graphite material by a sputtering process combined with the mask. In the sputtering process, the solid part of the mask plate blocks sputtered Ag atoms from flying to the substrate, and the hollow part of the mask plate allows sputtered Ag atoms to fly to the substrate, so that the mask plate pattern is the pattern of the Ag grid line. The purity of the silver target material is 99.99%, the base temperature is 25 ℃ at normal temperature, the distance between the target material and the base material is 50mm, the sputtering gas is argon (purity is 99.99%), and the background vacuum degree is 5 x 10 -5 Pa, sputtering power 160W. The thickness of the sputtered Ag layer was 200nm, and the sheet resistance was 0.25Ω/≡.
And then, adopting a tinned silver belt or a tinned copper belt to conduct bus extraction on the front surface metal electrode of the top-layer copper indium gallium diselenide battery. In the embodiment, a 2-terminal design is adopted, specifically, the electrode of the top-layer copper indium gallium selenide battery leads out photo-generated electrons, and the bottom-layer PERC battery leads out photo-generated holes.
And 15, carrying out laser etching cutting on the top copper indium gallium selenide battery with a large area and the middle connecting layer with a large area, selectively etching away all functional layer films (including a charge transmission layer, an interface passivation layer, a copper indium gallium selenide film and the like) of the top copper indium gallium selenide battery and middle layer materials with a large area, and only keeping the back flexible substrate packaging layer (namely flexible coated glass) of the bottom crystalline silicon module without etching cutting. Thus, the copper indium gallium selenide battery (and the intermediate connecting layer) with a large area on the top layer is etched and cut into copper indium gallium selenide batteries with small areas, and copper indium gallium selenide/crystal silicon laminated battery units with small areas which are independent and separated from each other are formed one by one in the longitudinal direction. It is also noted that the laser etch dicing process cannot etch and destroy the previously prepared interconnect vias, which can be accomplished by a precise scanning technique of laser etching. The laminated cell assembly was obtained by a laser etching cutting process (fig. 3-b).
Laser etching cutting patterns: here, first, the longitudinal direction is defined as the z-axis direction, and the horizontal two directions are the x-axis and y-axis directions, respectively. The laser etching cut is performed along the center line between every 4 most adjacently arranged PERC cells in the x-axis direction of the "PERC battery module of the underlying semi-finished product" and the center line between every 2 most adjacently arranged PERC cells in the y-axis direction, as viewed from the z-axis direction. Thus, the large-area top copper indium gallium selenide cell and the large-area intermediate connection layer are etched and cut into small-area patterns to form stacked cell units, and the top copper indium gallium selenide cell (and the intermediate connection layer) of each 1 cell corresponds to 2 bottom crystalline silicon cells (i.e., n=2) when seen in the z-axis direction, as shown in fig. 3-b.
The specific laser etching process is as follows. The laser beam is precisely scanned and precisely etched along a large area of flexible laminate cells by a flexible laser beam deflection, precise focusing, and highly precisely aligned camera system. Based on the same pattern as given above, one laser etching was employed. The laser etching process needs to etch away the AZO film, n-Zn (S, O), CIGS absorbing layer and p of the top CIGS cell + CIGS back field. Specifically adopts Nd-YVO 4 The solid-state laser has the wavelength of 532nm and the pulse width of 10ns, the repetition frequency is 20kHz, and the nitrogen atmosphere is introduced in the laser process.
Thirdly, interconnecting and packaging the laminated battery to finish the preparation of the copper indium gallium diselenide/crystalline silicon laminated battery component
And step 16, interconnecting the leads of the front and back electrodes of each laminated battery cell. In the interconnection, the metallized leads on the back side of the laminated battery are first passed through the previously prepared interconnection through-holes, and then interconnected in different laminated battery cells. In this example, the bottom layer PERC battery module is a 12 x 12 array formed by 144 half-cells, and the interconnection mode is that the rows are connected in series, and the columns are connected in parallel.
Then, the front and back sides of the laminated cell are encapsulated. The front packaging film adopts PDMS (polydimethylsiloxane) and flexible coated glass (front outermost layer), the back outermost layer flexible packaging film adopts Polyimide (PI), and the cross-linking agent adopts organic silica gel which is applied to solar cell packaging by Dow Corning company. The specific packaging technology is that front flexible coated glass, a PDMS packaging film, the prepared semi-finished product copper indium gallium selenide/crystalline silicon laminated battery and polyimide are uniformly paved, and organic silica gel is uniformly coated between the layers by a dispensing method. And then deep curing is carried out for 1-2 hours at the temperature of 25-50 ℃ in the presence of nitrogen, so that the silica gel tightly adheres all the components together, and the packaging film, the organic silica gel and the semi-finished laminated battery are fully crosslinked, fixed and sealed. A curing lamination process with a slow increase in pressure may also be employed herein to enhance the curing effect and accelerate the curing process. Since the silicon gel has good insulation properties, the silicon gel filled between the individual copper indium gallium diselenide/crystalline silicon laminate cells cut by the laser etching of step 15 also plays a role in good electrical isolation between them.
And 17, finally, mounting a frame, sealing and mounting a junction box by adopting a conventional technology to form the final flexible CIGS/crystalline silicon laminated solar cell module. In particular applications, the illustrated laminate battery assembly may be designed to have the same curvature (i.e., flexibility) as it is, in combination with the outer curvature of the application scene.
Finally, it should be noted that although embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above-described specific embodiments and application fields, and the above-described specific embodiments are merely illustrative and instructive, and are used to help understand the method of the present invention and its core ideas, not limiting. Many alterations, modifications and equivalents will occur to those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims, and their equivalents are intended to be embraced by the specification.
Claims (10)
1. The flexible copper indium gallium selenide/crystalline silicon laminated solar cell module comprises a bottom layer crystalline silicon cell and is characterized by further comprising a top layer copper indium gallium selenide cell, wherein the bottom layer crystalline silicon cell is connected with the top layer copper indium gallium selenide cell through an intermediate connecting layer, a flexible substrate packaging layer is arranged on the back surface of the bottom layer crystalline silicon cell, a lead of the bottom layer crystalline silicon cell is led out of the substrate packaging layer, the top layer copper indium gallium selenide cell and the intermediate connecting layer are etched and cut into laminated cell units with small areas, and only the flexible substrate packaging layer is reserved and not cut;
The structure of each laminated cell unit is that the top layer copper indium gallium selenide cell of each 1 unit corresponds to n bottom layer crystal silicon cells through etching and cutting, and n is more than or equal to 10 and more than or equal to 2;
the substrate packaging layer is provided with a through hole for leading out an electrode lead;
the flexible packaging layer is positioned on the surface of the top-layer copper indium gallium selenide battery and is positioned on the outermost side of the back surface of the crystalline silicon battery;
the flexible substrate packaging layer is made of flexible stainless steel, flexible metal foil or flexible coated glass, or made of polymer material, wherein the polymer material is any one of polyethylene terephthalate, polyimide, polyethylene naphthalate and polyvinyl alcohol.
2. The flexible copper indium gallium diselenide/crystalline silicon tandem solar cell assembly of claim 1, wherein: the through holes for leading out the electrode leads comprise electrode lead through holes and interconnection through holes, the electrode lead through holes are located right below the bottom layer crystal silicon batteries, the interconnection through holes are located longitudinally below the area between two adjacent laminated battery units, and the leads of the bottom layer crystal silicon batteries of each laminated battery unit are led out of the electrode lead through holes and then penetrate through the interconnection through holes to form interconnection with the leads of the top layer flexible copper indium gallium selenide battery and the leads of other laminated battery units.
3. The flexible copper indium gallium diselenide/crystalline silicon tandem solar cell assembly of claim 1 or 2, wherein: the intermediate connecting layer is of a composite structure and consists of a phosphorus-doped polycrystalline silicon layer arranged on the surface of the bottom-layer crystalline silicon cell and a p-type heavily-doped CIGS thin film layer.
4. A method for manufacturing a flexible copper indium gallium diselenide/crystalline silicon stacked solar cell module according to any one of claims 1 to 3, characterized in that it comprises the steps of:
(1) Preparing a semi-finished crystalline silicon cell only provided with a back electrode, and preparing a part of an intermediate connecting layer on the surface of the semi-finished crystalline silicon cell;
(2) Performing laser edge isolation on the periphery of the semi-finished product crystal silicon battery to ensure that the periphery of the edge of the semi-finished product crystal silicon battery becomes an electrical insulation property;
(3) Conducting assembly lead wire of the back electrode;
(4) Etching electrode lead through holes and interconnection through holes distributed in patterns on a flexible substrate packaging film, leading out leads of a back electrode through the electrode lead through holes on the flexible substrate packaging film, and then packaging the semi-finished crystalline silicon battery on the flexible substrate packaging film in an array structure, so that a flexible substrate packaging layer is formed on the back surface of a bottom layer semi-finished crystalline silicon battery;
(5) Growing another part of a large-area intermediate connecting layer on the front surface of the bottom semi-finished crystalline silicon cell, wherein the area of the intermediate connecting layer can completely cover all the bottom semi-finished crystalline silicon cells on the flexible substrate packaging film, and the intermediate connecting layer has the function of enabling optical coupling and electrical coupling to be formed between the bottom crystalline silicon cell and the copper indium gallium selenide cell on the top layer;
(6) Preparing a large-area top layer copper indium gallium selenide battery on the front surface of the middle connecting layer, and a front electrode on the top of the top layer copper indium gallium selenide battery;
(7) Component lead of the front electrode is carried out;
(8) Etching and cutting are carried out on the top copper indium gallium selenide battery with large area and the middle connecting layer with large area, only the flexible substrate packaging layer is reserved and not cut, the battery with large area is divided into a plurality of laminated battery units with small area which are independent in the longitudinal direction, the structure of each laminated battery unit is that the top copper indium gallium selenide battery of each 1 unit corresponds to n bottom crystal silicon batteries, and the number of the top copper indium gallium selenide battery is more than or equal to 10 and more than or equal to 2, so that the laminated battery is obtained;
(9) And (5) interconnecting and packaging the laminated battery to prepare the flexible copper indium gallium diselenide/crystalline silicon laminated solar battery.
5. The method for preparing the flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module according to claim 4, wherein the flexible substrate packaging layer is made of flexible stainless steel, flexible metal foil or flexible coated glass, or made of a polymer material, and the polymer material is any one of polyethylene terephthalate, polyimide, polyethylene naphthalate and polyvinyl alcohol.
6. The method of manufacturing a flexible copper indium gallium diselenide/crystalline silicon tandem solar cell module according to claim 5, wherein the leads in steps (3) and (7) are selected from copper-chromium alloy, copper-chromium-zirconium alloy, copper-chromium-tellurium alloy, nickel-copper-silicon alloy, copper-nickel-chromium alloy, nickel-chromium-iron alloy, or copper-platinum alloy.
7. The method for manufacturing the flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module according to claim 6, wherein the intermediate connecting layer is of a composite structure and is formed by laminating a p-type heavily doped CIGS thin film layer and phosphorus-doped polycrystalline silicon, the step (1) is completed for manufacturing the phosphorus-doped polycrystalline silicon layer, and the step (5) is completed for manufacturing the large-area p-type heavily doped CIGS thin film layer.
8. The method for manufacturing a flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module according to claim 7, wherein the step (8) is specifically: the longitudinal direction is taken as the z-axis direction, the horizontal two directions are respectively the x-axis direction and the y-axis direction, each 2 times the center line among n crystal silicon batteries which are adjacently arranged along the x-axis direction of the bottom semi-finished crystal silicon battery and the center line among 2 crystal silicon batteries which are adjacently arranged along the y-axis direction are etched and cut, and the large-area top copper indium gallium selenide battery and the large-area middle connecting layer are etched and cut into patterns with small areas, so that the top copper indium gallium selenide battery of each 1 unit is seen from the z-axis direction to correspond to the n bottom crystal silicon batteries, and n is more than or equal to 10 and more than or equal to 2.
9. The method for preparing the flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module according to claim 8, wherein the etching and cutting are selected from laser etching and cutting, plasma etching or mechanical grooving processes; when the laser etching cutting is selected, the laser scanning etching pattern is adopted to carry out twice laser etching completely the same, and partial functional layers of the copper indium gallium selenide battery are etched by the first laser etching, and the other partial functional layers and the large-area intermediate connecting layer are left to be not etched; and etching the other part of the functional layer and the large-area intermediate connecting layer by the second laser etching, and only keeping the back substrate packaging layer of the bottom-layer crystalline silicon cell from being etched.
10. The method of manufacturing a flexible copper indium gallium diselenide/crystalline silicon laminated solar cell module according to claim 9, wherein step (9) specifically includes passing a lead wire of the back electrode through an interconnection through hole, then interconnecting in different laminated cell units, and packaging the front and back surfaces of the laminated cell to form a front packaging layer and a back outermost packaging layer.
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