CN116322222A - Perovskite/crystalline silicon laminated solar cell module and preparation method thereof - Google Patents

Perovskite/crystalline silicon laminated solar cell module and preparation method thereof Download PDF

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CN116322222A
CN116322222A CN202310258452.9A CN202310258452A CN116322222A CN 116322222 A CN116322222 A CN 116322222A CN 202310258452 A CN202310258452 A CN 202310258452A CN 116322222 A CN116322222 A CN 116322222A
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perovskite
crystalline silicon
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黄海冰
虞旺
马晨
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Dazheng Jiangsu Micro Nano Technology Co ltd
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    • HELECTRICITY
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    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices

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Abstract

The invention provides a preparation method of a perovskite/crystalline silicon laminated solar cell module, which mainly comprises the following steps: firstly preparing a plurality of semi-finished crystalline silicon batteries, then carrying out back packaging to obtain a bottom crystalline silicon battery module, preparing a middle connecting layer and a top semi-finished perovskite battery on the bottom crystalline silicon battery module, etching and cutting from top to bottom to obtain a plurality of perovskite/crystalline silicon laminated batteries which are independent and separated in the longitudinal direction, and carrying out component packaging to obtain the perovskite/crystalline silicon laminated solar cell component. Furthermore, the invention also discloses a perovskite/crystalline silicon laminated solar cell module prepared by adopting the method. The invention fuses the preparation processes of the bottom layer battery, the top layer battery and the whole assembly, has simple preparation process, greatly reduces the production cost of the laminated assembly, and is suitable for industrialization.

Description

Perovskite/crystalline silicon laminated solar cell module and preparation method thereof
Technical Field
The invention belongs to the technical field of laminated solar cell modules, and particularly relates to a perovskite/crystalline silicon laminated solar cell module and a preparation method thereof.
Background
With the continuous and intensive research of human beings in the field of solar cells, the photoelectric conversion efficiency of single-junction solar cells (such as crystalline silicon cells and thin film cells of cadmium telluride, copper indium gallium selenide, perovskite and the like) is continuously improved and approaches the theoretical limit of Shockley-Queisser. By adopting the structural design of the laminated solar cell formed by materials with different optical forbidden bandwidths, the band range of the solar spectrum absorption and utilization of the cell can be comprehensively widened, so that the cell efficiency can break through the theoretical limit of the Shockley-Queisser. In recent years, with the rapid development of the industrialization of perovskite solar cells, crystalline silicon and perovskite are used as two materials with the highest cost performance for realizing high efficiency in single junction cells, and the theoretical efficiency of a laminated cell formed by the crystalline silicon and the perovskite can exceed 45%. Perovskite/crystalline silicon cells are therefore the most potential technical route for the next generation of commercial photovoltaic cells. However, the current preparation process flow of the perovskite/crystalline silicon laminated battery is still relatively complex, the preparation cost is high, the requirement of industrialized production cost still cannot be met, and the preparation process is required to be further simplified to reduce the preparation cost.
Disclosure of Invention
In order to solve the problems, the invention provides a perovskite/crystalline silicon laminated solar cell module and a preparation method thereof. The top layer of the perovskite/crystalline silicon stacked solar cell module (abbreviated as "perovskite/crystalline silicon stacked cell module") is the optical forbidden bandwidth (E g ) A broader perovskite cell, mainly using photons of high energy (short wavelength) and medium energy (medium wavelength) in the solar spectrum; the bottom layer is a crystalline silicon cell (E g =1.12 eV), photons of medium and long bands of medium and low energy of the solar spectrum are mainly utilized. Therefore, photons in short wave, medium wave and long wave wavelength ranges in solar spectrum can be utilized more comprehensively and efficiently, so that the battery efficiency breaks through the theoretical limit of Shockley-Queisser, and the power generation capacity of the component is higher.
The preparation process of the perovskite/crystalline silicon laminated cell component disclosed by the invention is to flexibly combine the preparation processes of a crystalline silicon cell, a perovskite cell and a component, and the preparation process is summarized as follows: (1) firstly, preparing a semi-finished crystalline silicon battery; then, carrying out laser edge isolation on the periphery of the semi-finished crystalline silicon battery, so that the periphery of the semi-finished crystalline silicon battery becomes an electrical insulation property; and then combining the preparation process of the crystalline silicon component, and packaging the back surface of the semi-finished crystalline silicon battery, wherein the preparation process comprises the steps of preparing electrode leads and a back surface basal layer, thereby forming a bottom crystalline silicon battery module consisting of a plurality of semi-finished crystalline silicon batteries. It will be appreciated that the periphery of the cell in the present invention includes the front edge of the cell, the back edge of the cell and the side walls. (2) Based on the prepared bottom layer crystalline silicon battery module, a large-area intermediate connecting layer and a top layer semi-finished perovskite battery are prepared, and the area of the intermediate connecting layer and the top layer semi-finished perovskite battery can completely cover the bottom layer crystalline silicon battery module. (3) Etching and cutting are carried out on the large-area top-layer semi-finished perovskite battery and the intermediate connecting layer, and each perovskite/crystal silicon laminated battery which is independent and separated and has small area is formed in the longitudinal direction. (4) And finally, interconnecting and packaging the laminated battery to finish the preparation of the perovskite/crystalline silicon laminated battery component.
It will be understood that the semi-finished crystalline silicon cell according to the present invention refers to a crystalline silicon cell in which the front surface (i.e., front) electrode is not fabricated, in other words, the cell has completed the basic structure of the crystalline silicon cell such as the charge transport layer and the back surface (i.e., back) electrode except that the front electrode is not fabricated. Likewise, the back electrode of the semi-finished perovskite cell of the present invention was not fabricated.
The perovskite/crystalline silicon laminated cell assembly provided by the invention is of a series type, and can be of a 2-terminal (2T) series type or a 3-terminal (3T) series type. For a 2T-type tandem type laminated cell, only one photo-generated carrier of electrons and holes is required to be led out of the bottom layer semi-finished crystalline silicon cell, and the other photo-generated carrier is led out of the top layer semi-finished perovskite cell. For a 3T type tandem type laminated cell, the bottom layer semi-finished product crystalline silicon cell needs to simultaneously export electrons and holes, and the top layer perovskite semi-finished product cell also simultaneously exports one of the electrons and the holes.
It will be appreciated that the process temperature for the preparation of perovskite cells may be significantly lower than for crystalline silicon cells, and therefore, the perovskite/crystalline silicon laminate cells are typically prepared by first preparing the underlying semi-finished crystalline silicon cell. Therefore, for the perovskite/crystalline silicon stacked cell assembly of the tandem type, the polarity of the front and rear surfaces of the top layer semi-finished perovskite cell (i.e., whether the photo-generated carriers extracted from the front and rear surfaces are electrons or holes) needs to be determined according to the polarity of the front and rear surfaces of the bottom layer semi-finished crystalline silicon cell, so as to form the tandem type stacked cell.
It can be appreciated that the preparation process of the intermediate connection layer and the top layer semi-finished perovskite battery and the material selection corresponding to the process are selected and determined according to the material of the prepared bottom layer crystalline silicon battery module. The specific requirement is that each part of the prepared bottom layer crystalline silicon battery module is not affected and destroyed, and the bottom layer crystalline silicon battery module mainly comprises a bottom layer semi-finished crystalline silicon battery, a metallized interconnection material and a back packaging material. The preparation process comprises high temperature heat treatment, physical bombardment and chemical reaction of a vacuum vapor deposition film, wet chemistry, laser or plasma dry etching and the like. On the basis of meeting this general principle, the material selection and the preparation process of the intermediate connection layer and the top layer semi-finished perovskite cell are not limited.
The bottom layer battery of the perovskite/crystalline silicon laminated battery component adopts a crystalline silicon battery, the forbidden bandwidth is 1.12eV, and photons of middle-low energy of solar spectrum in middle and long wave bands are mainly utilized. The silicon material substrate may be monocrystalline silicon or polycrystalline silicon, and the substrate doping type may be n-type (phosphorus doped) or p-type (boron doped or gallium doped).
The specific structure of the crystalline silicon cell is not limited, but is selected according to the entire laminate cell terminal design. For 2T series connection, an all-aluminum back field cell, PERC (passivated emitter and rear cell) cell, passivation contact TOPCon (Tunnel oxide and passivated contact) cell, silicon Heterojunction (HJT) cell, etc., may be employed, without limitation. For the 3T tandem type, a back contact (Interdigited back contact, IBC) cell may be used, or MWT (Metal Wrap Through) or EWT (Emitter Wrap Through) cells may be used.
The area size of the crystalline silicon battery is not limited, and the currently industrialized popular 156mm, 182mm or 210mm side length can be adopted, and the area size can be cut into smaller areas (which can be determined according to application scenes), such as one half piece, one third piece, … …, one n-half piece and the like.
The preparation process of the bottom layer crystalline silicon battery module mainly comprises the following process links: (1) the preparation of the charge (electron or hole) transport layer of the finished semi-finished crystalline silicon cell (2) the front surface of the crystalline silicon semi-finished cell does not need to be metallized, but the rear surface needs to be metallized, that is, only the rear electrode of the semi-finished crystalline silicon cell needs to be prepared. (3) And packaging the back surface of the plurality of semi-finished crystalline silicon batteries, wherein the back surface packaging comprises the preparation of electrode leads and a back surface basal layer.
It should be noted that in the present application, the metallized interconnection material on the back of the bottom layer crystalline silicon battery module, i.e., the electrode lead, should be able to avoid oxidation during the subsequent preparation of the intermediate connection layer and the top layer semi-finished perovskite battery, so as to ensure the interconnection performance of the perovskite/crystalline silicon stacked cell assembly. Metal alloys having high electrical conductivity and resistance to high temperature oxidation, such as copper-chromium alloys, copper-chromium-zirconium alloys, copper-chromium-tellurium alloys, nickel-copper-silicon alloys, copper-nickel-chromium alloys, or nickel-chromium-iron alloys, copper-platinum alloys, etc., which have good electrical conductivity while also having excellent resistance to high temperature oxidation, may be used herein.
The invention adopts two layers of packaging films for packaging the back surface of the bottom layer crystalline silicon battery module. The first packaging film is also called as a back substrate layer, is formed by packaging after the back crystalline silicon semi-finished battery is manufactured, and has good reliability, especially mechanical property, in material selection, and the material selection is not limited on the basis. Typically, it can be coated glass, or TPT back sheet material (TPT is a three-layer composite film of PVDF/PET/PVDF, where PVDF is polyvinylidene fluoride, and PET is polyethylene terephthalate), etc.
The substrate layer on the back is required to be etched with a certain number of through holes distributed in patterns, and the through holes are divided into two types according to the purposes of the through holes: the first holes are electrode lead through holes, the patterns of the electrode lead through holes are distributed in the edge of the longitudinal lower part of the semi-finished crystalline silicon battery, and the specific pattern distribution of the electrode lead through holes can be designed according to the electrode distribution of the back surface of the semi-finished crystalline silicon battery. The purpose of the electrode lead through holes is to pass the electrode leads on the back of the semi-finished crystalline silicon battery through the through holes; the second type of holes are interconnection through holes which are distributed in the area between two adjacent semi-finished crystalline silicon batteries and are used for interconnecting laminated batteries with different unit areas in the laminated battery assembly; it should be noted that the interconnect vias avoid as much as possible the center line and adjacent sides of the area between two adjacent semi-finished crystalline silicon cells, in order not to be damaged (etched) during the etching and dicing process performed after the top cell preparation is completed in the laminate cell preparation. The diameter ranges of the electrode lead through holes and the interconnection through holes may be typically 0.2 cm to 1 cm, and are not limited thereto. The process of etching the openings may be laser etching, plasma etching or mechanical etching.
The bottom semi-finished product crystalline silicon battery and the back substrate layer (with electrode lead through holes and interconnection through holes) are fixed together through packaging materials such as cross-linking agents and the like to form a whole. In this way, the electrode leads on the back of the bottom-layer crystalline silicon battery module penetrating through the back substrate layer are isolated outside the back substrate layer, and the electrode leads of the bottom-layer crystalline silicon battery module can be protected from being influenced by the subsequent intermediate connecting layer and the preparation process of the top-layer semi-finished perovskite battery. The crosslinking agent is usually used for packaging the battery component, and the packaging process can be conventional lamination, and is not particularly limited.
The second packaging film on the back is used as the packaging film on the outermost layer of the back of the whole perovskite/crystalline silicon laminated solar cell module, which is also called as a back packaging layer, and generally needs to have good reliability such as attenuation resistance, ageing resistance, ultraviolet resistance, mechanical load resistance, water resistance, moisture resistance, fire resistance, acid and alkali resistance and the like. The specific packaging material is not limited, and the same material as the back substrate layer can be used. And the second packaging film on the back is placed on the top battery after the preparation of the top battery is finished, and the second packaging film on the back and the front packaging film are finished together.
The intermediate connecting layer of the perovskite/crystalline silicon laminated cell assembly can ensure that the bottom crystalline silicon cell and the top perovskite cell have good optical coupling and electrical coupling in material selection, and the prepared bottom crystalline silicon cell module cannot be influenced and destroyed in preparation process. On the basis of meeting the above conditions, the specific materials and preparation process of the intermediate connection layer are not limited.
Typically, the material of the intermediate connection layer may be selected from transparent conductive oxides, such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), aluminum-doped zinc oxide (AZO), etc., and the preparation method may employ sputtering, atomic Layer Deposition (ALD), rapid plasma deposition, etc.
The top perovskite cell of the perovskite/crystalline silicon stacked cell assembly mainly uses photons with high energy (short wavelength) and medium energy (medium wavelength) in the solar spectrum, so that the forbidden bandwidth of the perovskite material is designed to achieve the point. E can be regulated by adjusting the chemical composition of the perovskite thin film g A typical range is 1.5-2.0eV, with a more optimal range being 1.6-1.8eV. Further, it is necessary to reconcile the polarity of the perovskite battery electrode with that of the underlying crystalline silicon battery to form a tandem type laminated battery assembly. On the basis of meeting the above requirements, the specific structure of the perovskite battery is not limited.
The top perovskite battery mainly comprises a perovskite absorption layer, an electron transmission layer, a hole transmission layer, an interface modification layer, an optical antireflection film, an electrode and the like, wherein the selection of materials of each functional layer and the corresponding preparation process are not particularly limited, and the top perovskite battery is briefly described as follows:
wherein, the perovskite absorbing layer material can be organic and inorganic halide perovskite or inorganic perovskite material. Typically, organic perovskite thin film materials are commonly employed, including in particular methylamine lead halide perovskite (CH 3 NH 3 PbX 3 MAPX for short), lead-halide-formamidine perovskite (nh=chnh 3 PbX 3 Abbreviated as FAPX), or formamidine methylamine mixed lead halide (formula (nh=chnh) 3 ) t (CH 3 NH 3 ) 1-t PbX 3 FA for short t MA 1-t PbX 3 ) And so on. Wherein X is halogen I, br or Cl. E of perovskite thin film g Can be adjusted according to the chemical composition thereof.
Among them, the electron transport layer may be made of an organic or inorganic material. Typical organic electron transport materials are PCBM (fullerenes and derivatives thereof), C 60 (fullerene), BCP (bromocresol purple sodium salt), liTFSI (lithium bistrifluoro methanesulfonimide), and the like, and is not limited thereto; typical inorganic electron transport materials are tin oxide (SnO 2 ) Zinc oxide (ZnO), titanium dioxide (TiO) 2 ) Zirconium oxide (ZrO) 2 ) Etc.; in addition, a double or multi-layered film stack of the above materials, such as PCBM/C, may also be used 60 、C 60 /SnO 2 、ZnO/SnO 2 Etc.
Among them, the hole transport layer may be made of an organic or inorganic material. Typical organic hole transport materials are Spiro-OMETAD (2, 2', 7' -tetrakis [ N, N-bis (4-methoxyphenyl) amino)]-9,9' -spirobifluorene), PEDOT PSS (poly 3, 4-ethylenedioxythiophene: polystyrene sulfonate), P3HT (polymer of 3-hexylthiophene), DR3TBDTT (conjugated small molecule oligothiophene derivative with benzothiophene as core, dimeric thiophene as arm and Luo Ningdan end-capped, chemical formula C 102 H 128 N 2 O 2 S 14 ) Etc. Typical inorganic hole transport materials are nickel oxide (NiO) x ) Molybdenum oxide (MoO) x ) Vanadium Oxide (VO) x ) Copper oxide (CuO, cu) 2 O), copper iodide (CuI), copper thiocyanate (CuSCN), and the like.
Among these, an interface modification layer is sometimes required between the perovskite absorption layer and the charge (electron or hole) transport layer, or between the charge transport layer and the electrode from which the charge is derived, to accelerate extraction and transport of the charge and reduce photo-generated carrier recombination.
Specific preparation processes of the materials of the functional layers of the semi-finished perovskite battery can adopt low-temperature solution methods, such as Spin-Coating (Spin-Coating), slot extrusion Coating (Slot-Die Coating), knife Coating (doctor blade Coating), printing Coating method, spray-Coating method (Spray-Coating), meniscus auxiliary solution printing (meniscus-assisted solution printing), ink jet printing (inkjet-printing) and the like; vacuum deposition methods such as sputtering, atomic layer deposition, rapid plasma deposition, and the like may also be employed. For some functional layers (such as perovskite thin films), if annealing is required, laser annealing techniques may be preferred because laser annealing is a cold working technique that does not affect and destroy the underlying semi-finished crystalline silicon module that has been fabricated.
The front surface electrode (i.e. the front electrode) of the top-layer semi-finished perovskite battery can be made of metal materials such as gold, silver, aluminum or copper, or can be made of electrodes such as graphene and carbon. The electrode is generally prepared by sputtering, screen printing and the like.
After the preparation of the large-area intermediate connecting layer and the top-layer semi-finished perovskite battery is completed, etching and cutting are needed, and the bottom-layer crystalline silicon module is kept from being etched and cut during etching and cutting, and particularly the back substrate layer cannot be damaged. Thus, the top-layer large-area semi-finished perovskite battery and the intermediate connecting layer are etched and cut into small-area perovskite battery units and intermediate connecting units, and the central lines of the top-layer perovskite battery units, the intermediate connecting units and the bottom-layer semi-finished crystal silicon battery are completely consistent in the longitudinal direction, so that independent and separated small-area perovskite/crystal silicon laminated batteries are formed in the longitudinal direction. Therefore, in actual etching cutting, it is possible to perform etching cutting along the center line between two adjacent semi-finished crystalline silicon cells in the crystalline silicon cell module as seen in the longitudinal direction, but it is also possible to allow etching cutting to be performed at an appropriate distance from the center line.
In this etching and cutting process, each functional layer film (including a charge transport layer, an interface modification layer, a perovskite absorption layer, etc.) and an intermediate connection layer material of the top perovskite battery need to be selectively etched, while the etching and cutting process does not etch and cut the back substrate layer of the bottom crystalline silicon battery. Therefore, there is a need for an etch cutting process that has a significant etch selectivity for the material to be etched and the material to be retained, while minimizing the cutting damage of the etch cutting process to the materials of the various parts of the fabricated laminate cell assembly. It is also noted here that the etch-cut process is not capable of etching and destroying the previously prepared interconnect vias. The etching and cutting process can adopt the technologies of laser etching and cutting, plasma etching or mechanical slotting and the like.
Typically, laser etching dicing techniques may be employed, with the selective etching dicing described above being achieved by selecting appropriate laser etching parameters. Nd: YVO can be generally used 4 The solid-state laser can select 355nm, 532nm or 1064nm laser wavelength, and is not limited to the above; pulse width is generally in the femtosecond, picosecond or nanosecond range, and is not limited thereto. In order to better realize the selective etching, alternatively, two times of laser etching with identical laser scanning etching patterns can be adopted, wherein the first time of laser etching is used for etching away part of the functional layer of the perovskite battery, and the other part of the functional layer and the intermediate connecting layer are left to be not etched; the second laser etching is used for etching away another part of the functional layer and the intermediate connecting layer, and the back substrate layer of the crystalline silicon component is kept from being etched. In the selection of the two laser parameters, the technological parameters of the second laser etching can realize faster etching rate of the material to be etched, and the etching capability of the back substrate layer is extremely weak.
After the preparation of the bottom semi-finished product crystalline silicon battery, the middle connecting layer and the top semi-finished product perovskite battery is completed, the laminated battery is finally required to be interconnected and packaged, and the preparation of the perovskite/crystalline silicon laminated battery component is completed. It should be noted that the packages herein may be referred to as "component packages" and generally include component front side packages and component back side packages to form front side and back side package layers. The front packaging of the component, namely the packaging of the front surface of the top-layer semi-finished perovskite battery, needs to have good optical anti-reflection performance, and good reliability such as attenuation resistance, ageing resistance, ultraviolet resistance, mechanical load performance, water resistance, moisture resistance, fire resistance, acid and alkali resistance and the like. The specific encapsulating material is not limited, and typically, a high molecular polymer such as PDMA (pyromellitic dianhydride), PDMS (polydimethylsiloxane), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), POE (polyolefin elastomer), POB (polystyrene), etc. may be used, and an inorganic encapsulating film such as coated glass, etc. may be used.
For the cross-linking agent adopted in the packaging of the top-layer semi-finished perovskite battery, the application mainly adopts organic silica gel for packaging. The organic silica gel has excellent light transmittance, electrical insulation performance, ultraviolet radiation resistance, high and low temperature resistance, chemical corrosion resistance, chemical stability, mechanical performance and reliability. The organic silica gel also has good crosslinking property and sealing property. According to the invention, the silica gel is used for replacing the traditional EVA cross-linking agent to package the solar cell module, and the solar cell module has excellent cross-linking property, sealing property, plasticity, ultraviolet radiation resistance, durability and electrical insulation property, so that the photovoltaic module is excellent in reliability and stable and efficient in working performance.
More importantly, the organic silica gel is adopted to encapsulate the photovoltaic module, and the lamination process at 140-150 ℃ is not required, but the photovoltaic module can be cured at normal temperature and normal pressure, so that the prepared perovskite battery part and the 'bottom semi-finished crystalline silicon module' are not affected and damaged. The specific method comprises the following steps: the organic silica gel is evenly paved between the packaging material on the front surface of the perovskite battery of the top-layer semi-finished product and the perovskite battery by adopting methods such as dispensing, coating, spraying or spin coating, and then deep curing is carried out at room temperature and normal pressure, and the curing process can be accelerated by improving the pressure in the curing process. Since the silicon gel has good insulation properties, the silicon gel filled between the individual perovskite/crystalline silicon stacked cells cut by the foregoing etching also functions as good electrical isolation therebetween.
For perovskite/crystalline silicon laminate cells, the leads of the front and back electrodes of each unit area laminate cell are interconnected. In particular, it is necessary to first pass the electrode leads on the back side of the laminate battery through the interconnection through-holes of the back substrate layer, and then to perform interconnection. The specific interconnection mode is not limited, and the internal series connection or parallel connection of the components can be performed according to the requirements of application scenes. And then, packaging the packaging film on the front side of the top-layer battery and the packaging film on the outermost side of the back side by adopting silica gel.
And finally, mounting a frame, sealing and mounting a junction box by adopting a conventional technical method to finally form the perovskite/crystalline silicon laminated solar cell module.
The invention has the following beneficial effects:
1) The invention combines the preparation processes of the bottom layer battery, the top layer battery and the whole assembly together, provides a new thought for preparing the laminated solar battery assembly, has simple preparation process, greatly reduces the production cost of the laminated assembly and is suitable for industrialization.
2) The perovskite/crystalline silicon laminated solar cell module is composed of a top perovskite cell with a wide forbidden band and a bottom crystalline silicon cell with a narrow forbidden band, and photons in the wavelength ranges of short waves, medium waves and long waves in solar spectrums can be utilized more comprehensively and efficiently, so that high cell conversion efficiency and module power generation capacity are realized.
3) The structure and the type of the top perovskite battery are flexible to select, the forbidden band width of the absorption layer can be designed into an optimized forbidden band width according to the requirements of application scenes, and the top perovskite battery with the forbidden band width can be realized through the component adjustment of the perovskite film material of the absorption layer, so that the top perovskite battery can be suitable for different application environments (climate, geography, environment and the like).
4) The perovskite/crystalline silicon laminated solar cell module can be flexibly prepared into a 2-terminal type or a 3-terminal type according to the requirements of application scenes, and the design is realized through the specific structure of the bottom crystalline silicon cell, so that the applicability and compatibility of the application scenes are flexibly widened.
Drawings
Fig. 1 is a schematic structural diagram of a perovskite/crystalline silicon stacked solar cell module, showing the case of using 1 crystalline silicon underlying cell as 1 unit. Wherein 1 is a back encapsulation layer, 2 is a back substrate layer, 3 is a back electrode of a bottom layer crystalline silicon cell, 4 is an electrode lead through hole, 5 is a component electrode lead of the back side of the bottom layer crystalline silicon cell, 6 is an electron (or hole) transport layer, 7 is a crystalline silicon substrate, 8 is a hole (or electron) transport layer, 9 is an intermediate connection layer, 10 is an electron (or hole) transport layer, 11 is a perovskite absorption layer, 12 is a hole (or electron) transport layer, 13 is a front encapsulation layer, 14 is a front electrode of a top layer perovskite cell, and 15 is a component electrode lead of the front side of the top layer perovskite.
Fig. 2 is a process flow diagram of the fabrication of a perovskite/crystalline silicon tandem solar cell module.
Fig. 3 is a schematic diagram before and after etching and cutting in the process of manufacturing a perovskite/crystalline silicon stacked solar cell module, wherein: FIG. 3-a is a schematic diagram before etching and dicing, wherein 1 is a bottom semi-finished crystalline silicon cell, 2 is a large area intermediate connection layer, 3 is a large area top perovskite cell, and 4 is a back substrate layer; fig. 3-b is a schematic diagram of the front side packaging of the component after etching and dicing. The semiconductor device comprises a bottom layer semi-finished product crystalline silicon battery, a middle connecting unit after etching and cutting, a top layer semi-finished product perovskite battery unit after etching and cutting, a back substrate layer, a front packaging layer, a back packaging layer, an electrode lead through hole and an interconnection through hole, wherein the bottom layer semi-finished product crystalline silicon battery is 1, the middle connecting unit after etching and cutting is 2, the top layer semi-finished product perovskite battery unit after etching and cutting is 3, the back substrate layer is 4, the front packaging layer is 5, the back packaging layer is 6, the electrode lead through hole is 7, and the interconnection through hole is 8. It should be noted that after the package of the module is completed, the space between each adjacent unit area of the stacked cells is filled with the front surface sealing material and the cross-linking agent, which have good electrical insulation properties, and thus, the insulation effect between the stacked cells of different unit areas is also equivalent.
Detailed Description
For a better understanding of the present invention, the present invention will be further described with reference to the following specific examples and drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1 to 3, example 1 shows a method for manufacturing a perovskite/crystalline silicon stacked solar cell module, wherein a bottom crystalline silicon cell is a PERC cell, and a top perovskite cell absorbs E g Is 1.75eV. The specific preparation process mainly comprises the following stages:
in the first stage, preparing a bottom PERC battery module, the specific preparation method is as follows:
step 1, selecting a p-type monocrystalline silicon piece with a crystal orientation of (100) 182mm, wherein the thickness of the p-type monocrystalline silicon piece is 170 micrometers, and the resistivity is 1 Ω & cm.
And 2, preparing a texture surface with a random pyramid morphology on the surface of the p-type silicon wafer by using an alkali texture making method. The process conditions are as follows: adopting potassium hydroxide with mass concentration of 2-3%, and making wool for 5-7min at 70-75deg.C.
Step 3, preparing uniform n-type emitter junction on the front side of the p-type silicon wafer by adopting a method of implanting phosphorus by ion and annealing by combining with a furnace tube, wherein the phosphorus implantation energy is 10keV, and the dosage is 1.10 15 cm 2 The annealing temperature of the furnace tube is 830-850 ℃, the time is 30-40min, and the nitrogen atmosphere is adopted. Phosphorus surface doping concentration is 1.10 20 cm -3 The square resistance is 90-100 Ω/≡.
And step 4, etching a small amount of phosphorus doped junctions which are diffused to the back surface of the p-type silicon wafer in the step 3 by adopting a mixed solution of nitric acid and hydrofluoric acid and combining a wet etching process of water bleaching. Through the chemical etching, the suede on the back surface of the silicon wafer is etched into an acid polished surface. In the mixed solution of nitric acid and hydrofluoric acid, the mass concentration of the nitric acid is 40%, the mass concentration of the hydrofluoric acid is 4%, the temperature of the solution is 7 ℃, and the etching time is 10-20 seconds.
And 5, preparing a passivation film on the back surface of the p-type silicon wafer. Depositing an alumina and silicon nitride laminated film by adopting a PECVD (plasma enhanced chemical vapor deposition) process, wherein the thickness of the alumina is 5nm, and the refractive index is 1.65; the silicon nitride has a thickness of about 100nm and a refractive index of 2.0.
And 6, etching the aluminum oxide/silicon nitride laminated film on the back surface of the p-type silicon wafer by adopting a laser ablation process. The laser film-opening process parameters are Nd: YVO 4 The laser has a wavelength of 532nm, a pulse width of 15ps and a pulse repetition frequency of 200-1000kHz. The pattern of the laser film is designed by grid line distribution, the line width is 25-30 μm, the distance between two adjacent grid lines (between axes) is 1.6mm, and the pattern is the pattern of the subsequent aluminum back surface field doped region.
And 7, printing aluminum paste on the back surface of the p-type silicon wafer by adopting a screen printing technology, sintering by adopting a rapid heat treatment sintering furnace to form a back surface local aluminum back surface field and metal-semiconductor ohmic contact, wherein the sintering real peak temperature is 750 ℃, the time under the peak temperature is 2 to 4 seconds, and the atmosphere is compressed air.
And 8, performing laser edge isolation on the periphery of the semi-finished PERC battery to ensure that the periphery of the battery becomes an electrical insulation property.
And 9, preparing the assembly electrode lead and the back substrate layer on the back of the bottom semi-finished PERC battery.
1) And packaging the back surface of the prepared semi-finished PERC battery, and adopting 72 battery pieces to form a 6 x 12 array standard. Firstly, welding the back aluminum electrode, wherein the component lead wire of the aluminum electrode adopts copper-chromium alloy, copper-chromium-tellurium alloy, copper-nickel-chromium alloy and the like, which have good conductivity and excellent high-temperature oxidation resistance, so that oxidation can be avoided in the subsequent preparation of the intermediate connecting layer and the top perovskite battery, and the interconnection performance of the laminated battery component is ensured.
2) The back substrate layer adopts coated glass with good mechanical properties, and needs to be subjected to the following two treatments: (1) And etching a certain number of electrode lead through holes and interconnection through holes distributed in a pattern on the coated glass by adopting a low-damage laser etching technology, wherein the diameters of the electrode lead through holes and the interconnection through holes are 0.8 cm. The pattern distribution of the electrode lead through holes is distributed in the edge below the longitudinal direction of the semi-finished product crystalline silicon battery, and the specific pattern distribution of the electrode lead through holes can be designed according to the metal electrode distribution of the back surface of the semi-finished product PERC battery; the pattern of interconnection through holes is distributed under the longitudinal direction of the area between two adjacent semi-finished PERC batteries, so that the central line and the adjacent two sides of the area between the two adjacent semi-finished PERC batteries are avoided as much as possible, and 355nm nanosecond laser technology can be adopted to complete the through hole etching. (2) After the through hole etching is finished, hydrofluoric acid cleaning treatment is carried out on the back substrate layer, namely coated glass, wherein the HF mass fraction is 5% -10%, the time is 30-60 minutes, and then the through hole is washed and dried, so that the blocking capability (not etched) of laser etching cutting in the step 15 can be further enhanced. Next, the rear electrode lead of the semi-finished PERC battery is passed through the electrode lead through hole on the rear base layer. Then, laying the bottom semi-finished PERC battery, the back substrate packaging layer and the cross-linking agent EVA (ethylene-vinyl acetate copolymer) and vacuum laminating, wherein the laminating process is carried out at the temperature of 140 ℃ and the pressure of 100Pa for 7-8 minutes, and the atmosphere is nitrogen. Thus, the bottom PERC crystal silicon module is completed.
Second stage, preparing large-area intermediate connecting layer
And 10, preparing an intermediate connecting layer of the laminated battery on the bottom PERC crystal silicon module, wherein the area of the intermediate connecting layer is the same as that of the PERC battery module (note: the preparation process of the top perovskite battery is the same as that of the top perovskite battery). Tin-doped indium oxide (ITO) is adopted to prepare the material by a magnetron sputtering technology. The target material is indium tin oxide (In 2 O 3 :SnO 2 =90:10wt%) ceramic targets with purity higher than 99.99%. The spacing between the target substrates is 70-100mm. The sputtering atmosphere is Ar, O 2 Mixed gas (purity is higher than 99.99%), background vacuum degree is 1.5.10 -4 Pa, the substrate temperature is 25 ℃. The sputtering pressure was 0.1Pa, and the sputtering power was 50W. The thickness of ITO is 150nm, the square resistance is 30-70 omega/≡and the average transmittance is 87%.
Third stage, preparing large-area top-layer semi-finished perovskite battery
Step 11. Preparing a hole transport layer of the top perovskite cell, wherein PEDOT: PSS (poly 3, 4-ethylenedioxythiophene: polystyrene sulfonate) is adopted. The PEDOT is prepared by spin coating, PSS precursor spin coating liquid adopts 4083 solution of Heraeus company, spin coating rotating speed is 6000rpm (rotation/min), after spin coating is finished, the PEDOT is placed on a heating table at 80 ℃ for annealing for 30min, atmosphere is nitrogen, and then cooling is carried out to room temperature. PEDOT PSS thickness was 30nm.
Step 12, preparing a perovskite absorption layer film, wherein methylamine lead halogen perovskite, namely CH 3 NH 3 Pb(I x Br 1-x ) 3 ,E g In the range of 1.6-1.9 eV. Prepared by spin coating method and adopting PbI 2 、PbBr 2 、CH 3 NH 3 I. Perovskite precursor composed of DMF (N, N-dimethylformamide) and DMSO (dimethyl sulfoxide)The solution was spin-coated with chlorobenzene (DMF was removed as an anti-solvent) in combination with the perovskite film at 3000rpm. After spin coating, heating on a heating table at 70-80 ℃ for 30min under nitrogen. Then annealing by laser heat treatment, and using femtosecond Nd: YVO 4 The solid-state laser has a wavelength of 800nm, a pulse width of 140fs, a repetition frequency of 80MHz, and a nitrogen atmosphere in the laser process. After laser annealing, the perovskite film completes the crystal phase transformation. It should be noted that due to the local heat treatment properties of laser "cold working", only the perovskite thin film will be subjected to laser heat treatment, while the already prepared layers of material below the perovskite absorber layer will not be affected. The prepared perovskite film CH 3 NH 3 Pb(Br 0.4 I 0.6 ) 3 E of (2) g Is 1.75eV and has a thickness of 500nm.
Step 13, preparing an electron transport layer/interface modification layer by adopting PC 61 BM/BCP. Wherein the electron transport layer PC 61 BM is composed of PCBM (fullerene and its derivative) and C 60 (fullerene) composition; BCP (bromocresol purple sodium salt, C) 21 H 15 Br 2 NaO 5 S) as an interface modification layer for electron transport. The preparation method adopts a spin coating method, and the specific process is as follows. PC is put into 61 The BM precursor solution is dissolved in chlorobenzene, stirred evenly at normal temperature and then kept stand for standby. PC is put into 61 The BM solution is spin-coated on a sample, the spin-coating rotating speed is 5000-6000rpm, and after spin-coating, annealing is carried out for 20min at a heating table of 40 ℃, and nitrogen is introduced during heating. The saturated IPA solution of BCP was then spin coated onto the sample using spin coating at 2000rpm. PC obtained by the preparation 61 BM thickness is 20nm and BCP thickness is 5nm.
And 14, metallizing the front surface of the top perovskite battery, and forming a grid line type Ag electrode by adopting magnetron sputtering metal Ag. The mask is made of graphite material by a sputtering process combined with the mask. In the sputtering process, the solid part of the mask plate blocks sputtered Ag atoms from flying to the substrate, and the hollow part of the mask plate allows sputtered Ag atoms to fly to the substrate, so that the mask plate pattern is the pattern of the Ag grid line. The purity of the silver target material is 99.99%, the substrate temperature is 25 ℃ at normal temperature, and the target materialThe distance between the sputtering gas and the substrate is 50mm, the sputtering gas is argon (purity is 99.99%), and the background vacuum degree is 5.10 -5 Pa, sputtering power 160W. The thickness of the sputtered Ag layer was 200nm, and the sheet resistance was 0.25Ω/≡. And then a tinned silver belt or a tinned copper belt is adopted to lead out the front surface metal electrode of the top-layer perovskite battery, in this example, a 2-terminal design is adopted, specifically, the electrode of the top-layer perovskite battery leads out photogenerated electrons, and the bottom-layer PERC battery leads out photogenerated holes.
And 15, carrying out laser etching cutting on the top perovskite battery with a large area and the intermediate connecting layer, selectively etching away all functional layer films (including a charge transmission layer, an interface modification layer, a perovskite absorption layer and the like) and intermediate layer materials of the top perovskite battery, and only keeping the back substrate layer of the 'bottom PERC crystal silicon module' without being etched and cut. Thus, the perovskite battery with large area on the top layer and the intermediate connection layer are etched and cut into perovskite battery units with small area and intermediate connection units, and the perovskite/crystal silicon laminated battery with small area, which are independent and separated, is formed one by one in the longitudinal direction. It is also noted that the laser etch dicing process cannot etch and destroy the previously prepared interconnect vias, which can be accomplished by a precise scanning technique of laser etching.
The specific laser etching process is as follows. The laser beam is precisely scanned and precisely etched along a large area of the stacked cell by a flexible laser beam deflection, precise focusing, and highly precisely aligned camera system. The specific laser etching cutting pattern is that etching cutting is performed along the center line between every 2 PERC cells which are adjacently arranged in the PERC cell module of the bottom layer semi-finished product in the longitudinal direction, so that the top perovskite cell with large area and the middle connecting layer are etched and cut into patterns with small areas which are approximately equal to the area of the bottom crystalline silicon cell, as shown in fig. 3-b. And cutting the pattern based on the laser etching, and adopting twice laser etching. The 1 st laser etching is used for etching away the electron transport layer/interface modification layer (PC) 61 BM/BCP), perovskite absorption layer film, hole transport layer PEDOT: PSS; 2 nd time of laser engravingThe etching is used to etch away the intermediate connection layer ITO. The two laser etching process parameters are as follows. At 1 st time, nd: YVO was used 4 The solid-state laser has the wavelength of 532nm, the pulse width of 15ns, the repetition frequency of 15-30kHz and the nitrogen atmosphere in the laser process. Nd-YVO was used for the 2 Nd time 4 The solid-state laser has the wavelength of 1064nm, the pulse width of 8ns, the repetition frequency of 10-20kHz and the nitrogen atmosphere in the laser process.
And a fourth stage, interconnecting and packaging the laminated battery to finish the preparation of the perovskite/crystalline silicon laminated battery component
And step 16, interconnecting the leads of the front and back electrodes of the laminated battery with each unit area. In specific interconnection, the electrode leads on the back of the laminated batteries are required to pass through the prepared interconnection through holes, and then interconnection is carried out in laminated batteries with different small areas, in this example, the bottom layer PERC battery module is formed by 6 x 12 arrays of 72 battery pieces, the interconnection mode is that the small laminated batteries in 12 rows are connected in series, and 6 columns are connected in parallel. And packaging the front and back of the laminated battery after interconnection, namely packaging the assembly. The front packaging film adopts PDMS (polydimethylsiloxane) and coated glass (the outermost layer of the front), the outermost packaging film of the back adopts coated glass, and the cross-linking agent adopts organic silica gel of the product series of solar cell packaging by Dow Corning company. The specific packaging technology is that the front side coated glass, the PDMS packaging film, the prepared perovskite crystal silicon laminated battery and the back side coated glass are uniformly paved, and the organic silica gel is uniformly coated between the layers by a dispensing method. And then deep curing is carried out at 25-50 ℃ for 1-2 hours, the atmosphere is nitrogen, so that the silica gel tightly adheres the components together, and the packaging film, the organic silica gel and the laminated battery are fully crosslinked, fixed and sealed. Here, a curing lamination method of slowly increasing pressure may also be employed to enhance the curing effect and accelerate the curing process. Since the silicon gel has good insulation properties, the silicon gel filled between the individual perovskite/crystalline silicon stacked cells cut by the laser etching of step 15 also plays a role of good electrical isolation therebetween.
And 17, installing a frame, sealing and installing a junction box by adopting a conventional technical method to form the final perovskite/crystal silicon laminated solar cell module.
Further, embodiment 2 discloses a perovskite/crystalline silicon stacked solar cell module, which is formed by the method described in embodiment 1, and the specific structure is not described herein.
Finally, it should be noted that although embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above-described specific embodiments and application fields, and the above-described specific embodiments are merely illustrative and instructive, and are used to help understand the method of the present invention and its core ideas, not limiting. Many alterations, modifications and equivalents will occur to those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims, and their equivalents are intended to be embraced by the specification.

Claims (10)

1. The preparation method of the perovskite/crystalline silicon laminated solar cell module is characterized by comprising the following steps of:
preparing a plurality of semi-finished crystalline silicon cells, wherein the semi-finished crystalline silicon cells only have a back electrode;
performing laser edge isolation on the periphery of the semi-finished crystalline silicon battery to electrically insulate the periphery of the semi-finished crystalline silicon battery;
performing back packaging on the semi-finished product crystalline silicon battery to obtain a bottom crystalline silicon battery module, wherein the back packaging comprises preparing a back electrode lead and a back substrate layer; the back substrate layer is provided with a plurality of electrode lead through holes positioned in the area below the semi-finished product crystalline silicon battery in the longitudinal direction, and a plurality of interconnection through holes positioned in the area between the adjacent semi-finished product crystalline silicon batteries;
preparing an intermediate connecting layer on the bottom layer crystal silicon battery module, wherein the intermediate connecting layer is used for optical coupling and electrical coupling of the semi-finished crystal silicon battery and the semi-finished perovskite battery, and the intermediate connecting layer completely covers the bottom layer crystal silicon battery module;
preparing a top-layer semi-finished perovskite battery on the intermediate connecting layer, wherein the semi-finished perovskite battery completely covers the intermediate connecting layer, the semi-finished perovskite battery only has a front electrode, and the patterns and the distribution of the front electrode are matched with the back electrode of the bottom-layer crystalline silicon battery module;
etching and cutting the semi-finished perovskite batteries and the intermediate connecting layer from top to bottom to obtain a plurality of perovskite battery units and intermediate connecting units, wherein the number of the perovskite battery units and the intermediate connecting units are consistent with that of the semi-finished crystalline silicon batteries in the bottom crystalline silicon battery module, so that a plurality of perovskite/crystalline silicon laminated batteries which are independent and separated from each other are formed in the longitudinal direction;
and carrying out component packaging on the perovskite/crystalline silicon laminated cell to obtain the perovskite/crystalline silicon laminated solar cell component, wherein the component packaging comprises preparing a front electrode lead, a front packaging layer and a back packaging layer.
2. The method of manufacturing as claimed in claim 1, wherein the back electrode lead of the semi-finished crystalline silicon cell is any one of copper-chromium alloy, copper-chromium-zirconium alloy, copper-chromium-tellurium alloy, nickel-copper-silicon alloy, copper-nickel-chromium alloy, nickel-chromium-iron alloy, copper-platinum alloy.
3. The method of manufacturing according to claim 1, wherein the back substrate layer is coated glass or a TPT backsheet.
4. The method of claim 1, wherein the intermediate connection layer is made of any one of tin-doped indium oxide, indium-doped zinc oxide, and aluminum-doped zinc oxide; the intermediate connecting layer is prepared by adopting sputtering, atomic layer deposition or rapid plasma deposition technology.
5. The method of manufacturing according to claim 1, wherein the semi-finished perovskite cell manufacturing process includes an annealing treatment, the annealing treatment being a laser annealing process.
6. The method of manufacturing according to claim 1, wherein when etching and cutting are performed on the semi-finished perovskite cell and the intermediate connection layer from top to bottom, etching and cutting are performed along the center line of the adjacent semi-finished crystalline silicon cell in the bottom crystalline silicon cell module; the interconnection through hole is positioned in a region avoiding the central line, and the diameter of the interconnection through hole is 0.2 cm-1 cm.
7. The method of claim 1, wherein the etching and cutting process is any one of laser etching and cutting, plasma etching, and mechanical grooving.
8. The method of claim 7, wherein the etching and cutting process uses laser etching and cutting; the laser etching and cutting adopts a Nd: YVO4 solid-state laser; the laser etching cutting is completed in two times, wherein partial functional layers of the semi-finished perovskite battery are cut off in the first etching, and the rest functional layers and the intermediate connecting layers of the semi-finished perovskite battery are cut off in the second etching.
9. The method of claim 1, wherein the front side encapsulation layer is fixedly connected to the semi-finished perovskite battery through an organic silica gel, and the organic silica gel is cured at normal temperature and normal pressure.
10. A perovskite/crystalline silicon stacked solar cell module prepared by the preparation method according to any one of claims 1 to 9; the perovskite/crystalline silicon laminated solar cell module is a 2-terminal series type or a 3-terminal series type module.
CN202310258452.9A 2023-03-17 2023-03-17 Perovskite/crystalline silicon laminated solar cell module and preparation method thereof Pending CN116322222A (en)

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