CN116449904A - Slow start circuit applied to LDO and LDO circuit - Google Patents

Abstract

The invention provides a slow start circuit and an LDO circuit applied to LDO, which belong to the technical field of integrated circuits and comprise: an energy storage element; the feedback branch is connected between the bias power supply and the first node, and the control end of the feedback branch is connected with the first node; the bias power supply and the grounding end are provided with: the control end of the charging branch is connected with the first node; the control end of the buffer stage branch is connected with the output of the amplifying stage branch, and the output end of the buffer stage branch is connected with the grid electrode of a power adjusting tube; the switch control circuit includes: the switch branch is connected between the second node and the grounding end, and the second node is connected with the control end of the amplifying stage branch; and the control branch is connected between the bias power supply and the second node, and the control end of the control branch is connected with the first node. The beneficial effects are that: the invention can effectively solve the problem of instantaneous overshoot of the LDO voltage when the LDO is powered on while realizing the rapid power-on of the LDO.

Description

Slow start circuit applied to LDO and LDO circuit

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a slow start circuit and an LDO circuit for LDO.

Background

With the continuous development of electronic technology, especially the flash field of 5G technology and artificial intelligence technology, portable intelligent products such as mobile phones, palm computers, automobile electronics and the like have to meet the speed requirement, and the power supply plays an important role in the portable electronic products and has also been changed and improved in the aspects of performance, volume, cost and the like. Therefore, this makes the power management IC more demanding in terms of strong functional modules, high speed, high stability, and intelligence.

A low dropout linear regulator (low dropout regulator, LDO) uses a transistor or Field Effect Transistor (FET) operating in its saturation region to subtract excess voltage from the applied input voltage to produce a regulated output voltage. LDO is widely applied to portable electronic products because of the advantages of low noise, low power consumption, simple structure and the like.

In order to meet different load demands, new problems are continuously emerging in the existing LDO. For example, in order to meet some load response speed requirements, the LDO power supply needs to be powered up quickly, however, during the quick power-up process, a problem of power-up transient current overshoot may occur, and the power-up transient function judgment of the load may be affected by the overshoot current, and even the chip may be disabled. Therefore, in order to solve the above-mentioned problems, the present invention provides a slow start circuit and an LDO circuit for LDO to meet the practical application requirements.

Disclosure of Invention

In order to solve the technical problems, the invention provides a slow start circuit and an LDO circuit applied to an LDO, which can realize rapid power-up of the LDO and avoid the overshoot problem.

The technical problems solved by the invention can be realized by adopting the following technical scheme: a slow start circuit for LDO, comprising: the source electrode and the drain electrode of the power adjusting tube are connected between an input end and an output end; the energy storage element is connected between a first node and the grounding end; the control end of the feedback branch is connected with the first node to form a positive feedback loop; the bias power supply and the grounding end are provided with: the control end of the charging branch is connected with the first node and used for controlling the charging branch to charge the energy storage element; the control end of the buffer stage branch is connected with the output of the amplifier stage branch, and the output end of the buffer stage branch is connected with the grid electrode of a power adjusting tube; a switch control circuit, comprising: the switch branch is connected between a second node and the grounding end, and the second node is connected with the control end of the amplifying stage branch and used for controlling the opening or closing of the amplifying stage branch; and the control branch is connected between the bias power supply and the second node, and the control end of the control branch is connected with the first node and is used for controlling the on-off of the control branch according to the voltage of the first node so as to control the voltage of the second node.

Preferably, the feedback branch includes: the source electrode of the first PMOS tube (PM 1) is connected with the bias power supply, the grid electrode of the first PMOS tube (PM 1) is connected with the first node, and the drain electrode of the first PMOS tube (PM 1) is connected with the input end of a first inverter (INV 1); the source electrode of the second PMOS tube (PM 2) is connected with the bias power supply, the grid electrode of the second PMOS tube (PM 2) is connected with the output end of a second inverter (INV 2), the input end of the second inverter (INV 2) is connected with the output end of the first inverter (INV 1), and the drain electrode of the second PMOS tube (PM 2) is connected with the first node; the current comparison circuit is used for comparing the current flowing through the first PMOS tube (PM 1) with the reference current generated by the current mirror circuit and outputting the comparison result to the input end of the first inverter (INV 1).

Preferably, the current mirror circuit includes: a first NMOS tube (NM 1), wherein the grid electrode of the first NMOS tube (NM 1) is connected with a first bias voltage, and the drain electrode of the first NMOS tube (NM 1) is connected with the drain electrode of the first PMOS tube (PM 1); the grid electrode of the second NMOS tube (NM 2) is connected with a second bias voltage, the drain electrode of the second NMOS tube (NM 2) is connected with the source electrode of the first NMOS tube (NM 1), and the source electrode of the second NMOS tube (NM 2) is grounded.

Preferably, the charging branch includes: a first transistor (Q1), a base of the first transistor (Q1) is connected to the first node, and a collector of the first transistor (Q1) is grounded; the source electrode of the third PMOS tube (PM 3) is connected with the bias power supply, the grid electrode of the third PMOS tube (PM 3) is connected with a third bias voltage, and the drain electrode of the third PMOS tube (PM 3) is connected with the emitter electrode of the first transistor (Q1).

Preferably, the third PMOS transistor (PM 3) includes one or more than one third PMOS transistor, and the one or more than one third PMOS transistor is connected between the bias power supply and the emitter of the first transistor in an on-off manner.

Preferably, the switch control circuit includes: a third NMOS (NM 3), wherein a gate of the third NMOS (NM 3) is connected to an enable signal, a drain of the third NMOS (NM 3) is connected to the second node, and a source of the third NMOS (NM 3) is grounded; a fifth PMOS tube (PM 5), wherein the grid electrode of the fifth PMOS tube (PM 5) is connected with the first node, and the drain electrode of the fifth PMOS tube (PM 5) is connected with the second node; the grid electrode of the fourth PMOS tube (PM 4) is connected with a fourth bias voltage, the source electrode of the fourth PMOS tube (PM 4) is connected with the bias power supply, and the drain electrode of the fourth PMOS tube (PM 4) is connected with the source electrode of the fifth PMOS tube (PM 5).

Preferably, the amplifying stage branch comprises: a fourth NMOS (NM 4), wherein a gate of the fourth NMOS (NM 4) is connected to an output voltage ea_out of the error amplifier and a drain of the fifth PMOS (PM 5), respectively, and a source of the fourth NMOS (NM 4) is grounded; the grid electrode of the sixth PMOS tube (PM 6) is connected with the fourth bias voltage, the source electrode of the sixth PMOS tube (PM 6) is connected with the bias power supply, and the drain electrode of the sixth PMOS tube (PM 6) is connected with the drain electrode of the fourth NMOS tube (NM 4) to provide driving current for the fourth NMOS tube (NM 4).

Preferably, the buffer stage branch comprises: a seventh PMOS transistor (PM 7), wherein the gate of the seventh PMOS transistor (PM 7) is connected to the drain of the sixth PMOS transistor (PM 6), the drain of the seventh PMOS transistor (PM 7) is connected to the ground terminal through a first resistor, and the source of the seventh PMOS transistor (PM 7) is connected to the gate of the power regulator; the grid electrode of the eighth PMOS tube (PM 8) is connected with a fifth bias voltage, the source electrode of the eighth PMOS tube (PM 8) is connected with the bias power supply, and the drain electrode of the eighth PMOS tube (PM 8) is connected with the source electrode of the seventh PMOS tube (PM 7).

Preferably, the energy storage element is a capacitor.

The invention also provides an LDO circuit, which comprises the slow start circuit.

The technical scheme of the invention has the advantages that: according to the invention, the charging branch is used for charging the energy storage element, the first node is at a low potential before the LDO circuit is started, the energy storage element starts to charge, and meanwhile, the slow starting circuit starts to work, so that the starting of the LDO feedback loop is inhibited; with the slow start of the LDO, the energy storage element is fully charged, the first node becomes high potential, the slow start circuit is closed, the control action of the slow start circuit on the feedback loop is automatically cut off, the normal work of the feedback loop is not influenced, and the problem of instant overshoot of the power-on of the LDO voltage can be effectively solved while the rapid power-on of the LDO is realized; and the circuit has simple structure, small occupied area of the chip and lower cost.

Drawings

FIG. 1 is a schematic diagram of a slow start circuit applied to an LDO according to a preferred embodiment of the present invention;

FIG. 2 is a schematic diagram of an LDO circuit according to a preferred embodiment of the present invention.

Detailed Description

The invention will now be described in detail with reference to the drawings and specific examples. The present invention is not limited to the embodiment, and other embodiments may fall within the scope of the present invention as long as they conform to the gist of the present invention.

In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a slow start circuit and an LDO circuit for LDO are provided, which belong to the technical field of integrated circuits, as shown in fig. 1, and include: the source electrode and the drain electrode of the power adjusting tube are connected between an input end VIN and an output end VOUT; the energy storage element is connected between a first node A and the grounding end; the control end of the feedback branch is connected with the first node A to form a positive feedback loop for accelerating the voltage increase of the first node A; the bias power supply and the grounding end are provided with: the control end of the charging branch is connected with the first node A and used for controlling the charging branch to charge the energy storage element; the control end of the buffer stage branch is connected with the output of the amplifier stage branch, and the output end of the buffer stage branch is connected with the grid electrode of a power adjusting tube so as to inhibit the power adjusting tube from being opened quickly; a switch control circuit, comprising: the switch branch is connected between a second node B and the grounding end, and the second node B is connected with the control end of the amplifying stage branch and used for controlling the opening or closing of the amplifying stage branch; a control branch connected between the bias power supply and the second node B, a control end of the control branch connected with the first node A, the voltage control circuit is used for controlling the on-off of the branch circuit according to the voltage of the first node A so as to control the voltage of the second node B.

Specifically, in this embodiment, the charging branch is used to charge the energy storage element, before the LDO circuit is started, the first node a is at a low potential, the energy storage element starts to charge, and the slow start circuit starts to work at the same time, so as to inhibit the start of the LDO feedback loop; along with the slow start of the LDO, the energy storage element is fully charged, the first node A becomes high potential, the slow start circuit is closed, the control action of the slow start circuit on the feedback loop is automatically cut off, the normal work of the feedback loop is not influenced, and the problem of instantaneous overshoot of the power-on of the LDO voltage can be effectively solved while the rapid power-on of the LDO is realized.

As a preferred embodiment, wherein the feedback branch comprises: the source electrode of the first PMOS tube PM1 is connected with the bias power supply, the grid electrode of the first PMOS tube PM1 is connected with the first node A, and the drain electrode of the first PMOS tube PM1 is connected with the input end of a first inverter INV 1; the source electrode of the second PMOS tube PM2 is connected with a bias power supply, the grid electrode of the second PMOS tube PM2 is connected with the output end of a second inverter INV2, the input end of the second inverter INV2 is connected with the output end of the first inverter INV1, and the drain electrode of the second PMOS tube PM2 is connected with the first node A; the current comparison circuit is used for comparing the current flowing through the first PMOS tube PM1 with the reference current generated by the current mirror circuit and outputting the comparison result to the input end of the first inverter INV 1.

As a preferred embodiment, wherein the current mirror circuit comprises: a first NMOS transistor NM1, wherein the grid electrode of the first NMOS transistor NM1 is connected with a first bias voltage, the drain electrode of the first NMOS tube NM1 is connected with the drain electrode of the first PMOS tube PM 1; the gate of the second NMOS tube NM2 is connected with a second bias voltage, the drain of the second NMOS tube NM2 is connected with the source of the first NMOS tube NM1, and the source of the second NMOS tube NM2 is grounded.

Specifically, in this embodiment, the first NMOS transistor NM1 and the second NMOS transistor NM2 form a Cascode current mirror, which is used to generate an accurate current as a reference current, so as to compare the current flowing through the first PMOS transistor PM1 with the reference current, and further determine the level of the input end of the first inverter INV1, and then finally control the on and off of the slow start circuit through the second PMOS transistor PM2 and the fifth PMOS transistor PM 5.

As a preferred embodiment, wherein the charging branch comprises: a first transistor Q1, wherein a base electrode of the first transistor Q1 is connected to the first node a, and a collector electrode of the first transistor Q1 is grounded; the source electrode of the third PMOS tube PM3 is connected with a bias power supply, the grid electrode of the third PMOS tube PM3 is connected with a third bias voltage, and the drain electrode of the third PMOS tube PM3 is connected with the emitter electrode of the first transistor Q1.

As a preferred embodiment, the third PMOS transistor PM3 includes one or more than one third PMOS transistor, where one or more than one third PMOS transistor is connected on-off between the bias power supply and the emitter of the first transistor.

Specifically, the number of the third PMOS tubes PM3 is adjusted to adjust the charging duration of the charging branch to the energy storage element, so as to control the starting duration of the LDO.

In this embodiment, one or more third PMOS tubes PM3 may be provided, and a plurality of third PMOS tubes PM3 may be connected in series or in parallel. According to the embodiment of the invention, the quantity of the third PMOS tubes PM3 is adjusted to adjust the charging current when the base electrode of the first transistor Q1 charges the first capacitor C1, so that the adjustment of the capacitor charging time length is realized, and the LDO starting time length is controlled to match LDO circuits with different starting time lengths.

Further, when the third PMOS tubes PM3 are connected in series, the current flowing through the plurality of third PMOS transistors PM3 decreases, therefore, the number of the third PMOS tubes PM3 is increased, and the increase of the starting time of the LDO can be realized; the number of the third PMOS tubes PM3 is reduced, and the corresponding LDO starting time length is reduced.

Further, when the third PMOS tubes PM3 are arranged in parallel, the current flowing through the third PMOS tubes PM3 is increased, and the reduction of the LDO starting time is realized by increasing the number of the third PMOS tubes PM 3; by reducing the number of the third PMOS tubes PM3, the LDO starting time length is increased.

As a preferred embodiment, wherein the switch control circuit includes: the grid electrode of the third NMOS tube NM3 is connected with an enable signal EN_L, the drain electrode of the third NMOS tube NM3 is connected with the second node B, and the source electrode of the third NMOS tube NM3 is grounded; the grid electrode of the fifth PMOS tube PM5 is connected with the first node A, and the drain electrode of the fifth PMOS tube PM5 is connected with the second node B; the grid electrode of the fourth PMOS tube PM4 is connected with a fourth bias voltage, the source electrode of the fourth PMOS tube PM4 is connected with a bias power supply, and the drain electrode of the fourth PMOS tube PM4 is connected with the source electrode of the fifth PMOS tube PM 5.

As a preferred embodiment, wherein the amplifying stage branch comprises: the grid electrode of the fourth NMOS tube NM4 is respectively connected with the output voltage of an error amplifier and the drain electrode of the fifth PMOS tube PM5, and the source electrode of the fourth NMOS tube NM4 is grounded; the gate of the sixth PMOS tube PM6 is connected to the fourth bias voltage, the source of the sixth PMOS tube PM6 is connected to the bias power supply, and the drain of the sixth PMOS tube PM6 is connected to the drain of the fourth NMOS tube NM4, so as to provide the fourth NMOS tube NM4 with the driving current.

As a preferred embodiment, wherein the buffer stage branch comprises: a seventh PMOS tube PM7, wherein the grid electrode of the seventh PMOS tube PM7 is connected with the drain electrode of the sixth PMOS tube PM6, the drain electrode of the seventh PMOS tube PM7 is connected with the grounding end through a first resistor R1, and the source electrode of the seventh PMOS tube PM7 is connected with the grid electrode of the power adjustment tube; the grid electrode of the eighth PMOS tube PM8 is connected with a fifth bias voltage, the source electrode of the eighth PMOS tube PM8 is connected with a bias power supply, and the drain electrode of the eighth PMOS tube PM8 is connected with the source electrode of the seventh PMOS tube PM 7.

Further, the third PMOS transistor PM4, the fourth PMOS transistor PM4, the sixth PMOS transistor PM6, and the eighth PMOS transistor PM8 are respectively used as current sources of the respective branches to provide driving currents.

In the preferred embodiment, the bias power supply is an external input voltage source for providing a bias voltage VBIAS, which varies within a certain voltage range, for providing a static voltage for the circuit operation; further, the external input voltage source generates fixed bias voltages through the bias circuit, namely, the first bias voltage vbais_1, the second bias voltage vbais_2, the third bias voltage vbais_3, the fourth bias voltage vbais_4 and the fifth bias voltage vbais_5, and the voltage values of the 5 bias voltages are different and are fixed.

In a preferred embodiment, the energy storage element is a first capacitor C1.

In the preferred embodiment, the power adjustment tube is a fifth NMOS tube NM5, the gate of the fifth NMOS tube NM5 is connected to the source of the seventh PMOS tube PM7, the drain of the fifth NMOS tube NM5 is connected to the input terminal VIN, and the source of the fifth NMOS tube NM5 is connected to the output terminal VOUT.

Further, the working principle of the slow start circuit in the technical scheme of the invention is as follows: firstly, before the LDO circuit is not started, the voltage of each node is low; when the LDO circuit is started, the bias voltage VBAIS is at a high potential, the first bias voltage vbais_1, the second bias voltage vbais_2, the third bias voltage vbais_3, the fourth bias voltage vbais_4, and the fifth bias voltage vbais_5 are started to be established, and the corresponding first NMOS transistor NM1, second NMOS transistor NM2, third PMOS transistor PM3, fourth PMOS transistor PM4, sixth PMOS transistor PM6, and eighth PMOS transistor PM8 are opened.

At this time, since the base of the first transistor Q1 is at a low potential and the emitter is at a high potential, the first transistor Q1 is in a conductive state, the base current starts to charge the first capacitor C1, and after a period of time, the first capacitor C1 is fully charged, the base potential of the first transistor Q1 becomes high, i.e. the voltage at the first node a gradually increases from the low potential; the first PMOS tube PM1, the first inverter INV1, the second inverter INV2, and the second PMOS tube PM2 together form a positive feedback loop, the first PMOS tube PM1 is also in a conductive state, the input end of the first inverter INV1 becomes high potential, the high level is output to the gate of the second PMOS tube PM2 after passing through the first inverter INV1 and the second inverter INV2, the second PMOS tube PM2 is turned off, and the acceleration effect is provided for the base potential of the first transistor Q1 to become high.

Further, after the voltage at the first node a becomes high level, the fifth PMOS PM5 is turned off due to the high gate voltage, which cuts off the influence on the LDO loop control.

After the fifth PMOS tube PM5 is turned on, the gate potential of the fourth NMOS tube NM4 is suppressed from becoming low, so that the gate potential of the fourth NMOS tube NM4 is pulled high, the drain potential of the fourth NMOS tube NM4 becomes low, and then the output potential of the buffer stage is output to the gate of the fifth NMOS tube NM5 through the buffer stage circuit, that is, the gate potential of the fifth NMOS tube NM5 becomes low, thus VOUT becomes low, the current flowing through the fifth NMOS tube NM5 becomes low, the instant overshoot current at the output end becomes small, the buffer effect of reducing the current is finally achieved, the rapid turn-on of the fourth NMOS tube NM4 is suppressed, and the problem of the instant overshoot of the LDO voltage is solved.

After the LDO is started, the slow start circuit is in a closed state.

Further, when the enable signal en_l is at a low level, the third NMOS transistor NM3 is enabled, and after the third NMOS transistor NM3 is turned on, the gate potential of the fourth NMOS transistor NM4 is pulled down, so that the fourth NMOS transistor NM4 is turned off, and the LDO circuit control loop does not operate, thereby reducing the quiescent current. The on and off of the amplifier NM4 can be effectively controlled by the third NMOS transistor NM 3.

In summary, in the embodiment of the present invention, the base current of the first transistor Q1 is used to charge the first capacitor C1, and before the LDO circuit is started, the base potential is low, and the first capacitor C1 starts to be charged. Meanwhile, the slow start circuit starts to work, and the starting of the LDO feedback loop is restrained. Along with the slow start of the LDO, the first capacitor C1 is fully charged, the base potential of the first transistor Q1 becomes high level, the slow start circuit is closed, the control action of the slow start circuit on the feedback loop is automatically cut off, and the normal operation of the feedback loop is not influenced.

The invention also provides an LDO circuit, which comprises the slow start circuit.

Specifically, as shown in fig. 2, the LDO circuit includes 6 ports, specifically including an input terminal, an output terminal, a bias voltage terminal, an enable terminal, a feedback terminal, and a ground port; wherein the input terminal is connected with an input voltage VIN and passes through an input capacitorThe grounding end is connected; the enabling end is connected with an enabling signal and used for enabling control; the bias voltage terminal is connected with a bias power supply and is provided with a bias capacitor +.>The bias power supply is connected with the grounding end and used for providing bias voltage VBIAS for the LDO; the grounding port is grounded; the output terminal is used for outputting an output voltage VOUT and is provided with an output capacitor>The grounding end is connected; the feedback end is used for receiving a feedback signal from the voltage dividing circuit, the voltage dividing circuit is connected between the output end and the grounding end and specifically comprises a second resistor R2 and a third resistor R3, and the feedback end is connected with the connecting position of the second resistor R2 and the third resistor R3.

The technical scheme has the following advantages or beneficial effects: according to the invention, the charging branch is used for charging the energy storage element, the first node is at a low potential before the LDO circuit is started, the energy storage element starts to charge, and meanwhile, the slow starting circuit starts to work, so that the starting of the LDO feedback loop is inhibited; with the slow start of the LDO, the energy storage element is fully charged, the first node becomes high potential, the slow start circuit is closed, the control action of the slow start circuit on the feedback loop is automatically cut off, the normal work of the feedback loop is not influenced, and the problem of instant overshoot of the power-on of the LDO voltage can be effectively solved while the rapid power-on of the LDO is realized; and the circuit has simple structure, small occupied area of the chip and lower cost.

The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and drawings, and are intended to be included within the scope of the present invention.

Claims (10)

1. A slow start circuit for an LDO, comprising: the source electrode and the drain electrode of the power adjusting tube are connected between an input end and an output end; the energy storage element is connected between a first node and the grounding end; the control end of the feedback branch is connected with the first node to form a positive feedback loop; the bias power supply and the grounding end are provided with: the control end of the charging branch is connected with the first node and used for controlling the charging branch to charge the energy storage element; the control end of the buffer stage branch is connected with the output of the amplifier stage branch, and the output end of the buffer stage branch is connected with the grid electrode of a power adjusting tube; a switch control circuit, comprising: the switch branch is connected between a second node and the grounding end, and the second node is connected with the control end of the amplifying stage branch and used for controlling the opening or closing of the amplifying stage branch; and the control branch is connected between the bias power supply and the second node, and the control end of the control branch is connected with the first node and is used for controlling the on-off of the control branch according to the voltage of the first node so as to control the voltage of the second node.

2. The slow start circuit of claim 1, wherein the feedback branch comprises: the source electrode of the first PMOS tube is connected with the bias power supply, the grid electrode of the first PMOS tube is connected with the first node, and the drain electrode of the first PMOS tube is connected with the input end of a first inverter; the source electrode of the second PMOS tube is connected with the bias power supply, the grid electrode of the second PMOS tube is connected with the output end of a second inverter, the input end of the second inverter is connected with the output end of the first inverter, and the drain electrode of the second PMOS tube is connected with the first node; and the current comparison circuit is used for comparing the current flowing through the first PMOS tube with the reference current generated by the current mirror circuit and outputting the comparison result to the input end of the first inverter.

3. The slow start circuit of claim 2, wherein the current mirror circuit comprises: the grid electrode of the first NMOS tube is connected with a first bias voltage, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube; the grid electrode of the second NMOS tube is connected with a second bias voltage, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.

4. The slow start circuit of claim 1, wherein the charging branch comprises: the base electrode of the first transistor is connected with the first node, and the collector electrode of the first transistor is grounded; the source electrode of the third PMOS tube is connected with the bias power supply, the grid electrode of the third PMOS tube is connected with a third bias voltage, and the drain electrode of the third PMOS tube is connected with the emitter electrode of the first transistor.

5. The slow start circuit of claim 4, wherein the third PMOS transistor comprises one or more than one of the third PMOS transistors, the one or more than one of the third PMOS transistors being on-off connectable between the bias power supply and an emitter of the first transistor.

6. The slow start circuit of claim 1, wherein the switch control circuit comprises: the grid electrode of the third NMOS tube is connected with an enabling signal, the drain electrode of the third NMOS tube is connected with the second node, and the source electrode of the third NMOS tube is grounded; a fifth PMOS tube, wherein the grid electrode of the fifth PMOS tube is connected with the first node, and the drain electrode of the fifth PMOS tube is connected with the second node; the grid electrode of the fourth PMOS tube is connected with a fourth bias voltage, the source electrode of the fourth PMOS tube is connected with the bias power supply, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube.

7. The slow start circuit of claim 6, wherein the amplifier stage branch comprises: the grid electrode of the fourth NMOS tube is respectively connected with the output voltage of the error amplifier and the drain electrode of the fifth PMOS tube, and the source electrode of the fourth NMOS tube is grounded; the grid electrode of the sixth PMOS tube is connected with the fourth bias voltage, the source electrode of the sixth PMOS tube is connected with the bias power supply, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth NMOS tube and is used for providing driving current for the fourth NMOS tube.

8. The slow start circuit of claim 7, wherein the buffer stage branch comprises: a seventh PMOS transistor, wherein the gate of the seventh PMOS transistor is connected to the drain of the sixth PMOS transistor, the drain of the seventh PMOS transistor is connected to the ground terminal through a first resistor, and the source of the seventh PMOS transistor is connected to the gate of the power regulator; the grid electrode of the eighth PMOS tube is connected with a fifth bias voltage, the source electrode of the eighth PMOS tube is connected with the bias power supply, and the drain electrode of the eighth PMOS tube is connected with the source electrode of the seventh PMOS tube.

9. The slow start circuit of claim 1, wherein the energy storage element is a capacitor.

10. An LDO circuit comprising a soft start circuit as claimed in any of claims 1 to 9.