CN115202429B - Circuit for switching fixed version and adjustable version in low dropout linear voltage regulator - Google Patents
Circuit for switching fixed version and adjustable version in low dropout linear voltage regulator Download PDFInfo
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- CN115202429B CN115202429B CN202210720611.8A CN202210720611A CN115202429B CN 115202429 B CN115202429 B CN 115202429B CN 202210720611 A CN202210720611 A CN 202210720611A CN 115202429 B CN115202429 B CN 115202429B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
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Abstract
The invention provides a circuit for switching fixed and adjustable versions in a low dropout linear voltage regulator, which belongs to the technical field of integrated circuits and comprises: the logic level circuit is controllably connected between the bias port and the ground terminal and is provided with a first node for outputting a control signal; the first control circuit is controllably connected between the adjustable port and the feedback port of the low dropout linear regulator under the action of a control signal; the second control circuit is controllably connected between the feedback port and a voltage division node under the action of an inverted signal of the control signal; the voltage dividing circuit is connected to the adjustable port and is provided with a voltage dividing node; the third control circuit is controllably connected between the voltage dividing circuit and the grounding terminal under the action of the inverted signal of the control signal. The beneficial effects are that: the circuit has simple structure, small occupied area of the chip and stable performance, and can consider the area and the performance.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a circuit for switching fixed and adjustable versions in a low dropout linear voltage regulator.
Background
In recent years, with the continuous development of electronic technology, especially the flash field of 5G technology, and the popularization of artificial intelligence technology, intelligent products such as mobile phones, palm computers, automobile electronics, etc. have stepped into a new step. Low dropout linear regulators (low dropout regulator, LDOs) have been widely used in portable electronic products due to their low noise, low power consumption, and simple structure. With the continuous decrease in the size of integrated circuits and the rapid development of semiconductor manufacturing processes, the contradiction between chip area and performance is thus evident, and new problems are also emerging. For example, LDOs require that the same chip be compatible with both fixed and tunable versions to meet different load requirements, which tends to increase chip area.
Disclosure of Invention
In order to solve the technical problems, the invention provides a circuit for switching fixed and adjustable versions in a low dropout linear voltage regulator.
The technical problems solved by the invention can be realized by adopting the following technical scheme:
a circuit for fixed and adjustable version switching in a low dropout linear voltage regulator, comprising:
the logic level circuit is controllably connected between a bias port and a ground terminal and is provided with a first node for outputting a control signal;
the first control circuit is controllably connected between the adjustable port and the feedback port of the low dropout linear regulator under the action of the control signal;
the second control circuit is controllably connected between the feedback port and a voltage division node under the action of an inverted signal of the control signal;
the voltage dividing circuit is connected to the adjustable port and is provided with the voltage dividing node;
the third control circuit is controllably connected between the voltage dividing circuit and the grounding end under the action of the reverse phase signal of the control signal.
Preferably, the logic level circuit includes:
the grid electrode of the first PMOS tube is connected with a first bias voltage, and the source electrode of the first PMOS tube is connected with the bias port;
a first drain, a gate and a source of the first drain being connected to the ground terminal, and a drain of the first drain being connected to the first node;
and the first fuse is connected between the drain electrode of the first PMOS tube and the first node.
Preferably, the first control circuit includes:
the grid electrode of the first NMOS tube is connected with the first node, the drain electrode of the first NMOS tube is connected with the adjustable port, and the source electrode of the first NMOS tube is connected with the feedback port.
Preferably, the second control circuit includes:
the grid electrode of the second NMOS tube is connected with the first node through a first inverter, the source electrode of the second NMOS tube is connected with the feedback port, and the drain electrode of the second NMOS tube is connected with the voltage division node.
Preferably, the voltage dividing circuit includes:
the first resistor is connected between the adjustable port and the voltage dividing node;
and the second resistor is connected between the voltage division node and the third control circuit.
Preferably, the third control circuit includes:
the input end of the first NOR gate is respectively connected with the first node and the grounding end;
and the grid electrode of the third NMOS tube is connected with the output end of the first NOR gate, the drain electrode of the third NMOS tube is connected with the voltage dividing circuit, and the source electrode of the third NMOS tube is connected with the grounding end.
Preferably, when the low dropout linear voltage regulator works normally, the first node is at a high level, the first control circuit is turned on, the second control circuit and the third control circuit are turned off, the adjustable port is connected with the feedback port, and the low dropout linear voltage regulator is in an adjustable version.
Preferably, when the first node is at a low level, the first control circuit is turned off, the second control circuit and the third control circuit are turned on, the adjustable port is disconnected from the feedback port, and the low dropout linear regulator is in a fixed version.
Preferably, the adjustable port is connected to the output port of the low dropout linear regulator by a bonding wire when packaged.
The technical scheme of the invention has the advantages that:
the invention provides a circuit for switching fixed and adjustable versions, which is applied to a low-dropout linear voltage regulator, and has the advantages of simple structure, small occupied area of a chip, stable performance and capability of considering the area and the performance.
Drawings
FIG. 1 is a schematic diagram of a circuit for switching between fixed and adjustable versions in a LDO according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a LDO with a fixed version according to the preferred embodiment of the present invention;
FIG. 3 is a schematic diagram of an LDO with an adjustable version according to a preferred embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
The fixed version in the low dropout linear regulator of the embodiments of the present invention, i.e., having a fixed output voltage; an adjustable version, i.e. with an adjustable output voltage.
In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a circuit for switching between fixed and adjustable versions in a low dropout linear regulator is provided, which belongs to the technical field of integrated circuits, as shown in fig. 1, and includes:
the logic level circuit is controllably connected between a bias port VBIAS and a ground end GND, and is provided with a first node VC for outputting a control signal;
the first control circuit is controllably connected between the adjustable port ADJ/NC and the feedback port FB of the low dropout linear regulator under the action of a control signal;
the second control circuit is controllably connected between the feedback port FB and a voltage division node under the action of an inverted signal of the control signal;
the voltage dividing circuit is connected to the adjustable port ADJ/NC and is provided with a voltage dividing node;
the third control circuit is controllably connected between the voltage dividing circuit and the grounding terminal under the action of the inverted signal of the control signal.
Specifically, the circuit of the embodiment of the invention comprises a logic level circuit for generating a control signal, and a switching circuit of a fixed version and an adjustable version of an LDO (low dropout regulator) formed by a first control circuit, a second control circuit, a voltage dividing circuit and a third control circuit which are controlled by the control signal, so that the low dropout linear voltage regulator works in the fixed version mode or the adjustable version mode.
As a preferred embodiment, wherein the logic level circuit comprises:
the grid electrode of the first PMOS tube M1 is connected with a first bias voltage VBIAS_1, and the source electrode of the first PMOS tube M1 is connected with a bias port VBIAS;
the drain electrode of the first depletion tube DVTN1 is connected with a first node VC;
the first FUSE is connected between the drain of the first PMOS transistor M1 and the first node VC.
Specifically, in this embodiment, the logic level circuit is configured to generate a high-level control signal or a low-level control signal, so as to control the on-off states of the first control circuit, the second control circuit, and the third control circuit of the subsequent stage, and further control the low dropout linear voltage regulator to operate in a fixed version mode or an adjustable version mode. The generation of the high and low levels of the logic level circuit is achieved by using two states before and after the first fuse is blown.
Further, before the first FUSE blows, the control signal is at a high level, the first control circuit is turned on, the second control circuit and the third control circuit are turned off, and the LDO operates in an adjustable version mode.
As a preferred embodiment, wherein the first control circuit includes:
the first NMOS tube NM1, the grid of the first NMOS tube NM1 is connected with a first node VC, the drain electrode of the first NMOS tube NM1 is connected with an adjustable port ADJ/NC, and the source electrode of the first NMOS tube NM1 is connected with a feedback port FB.
As a preferred embodiment, wherein the second control circuit includes:
the gate of the second NMOS tube NM2 is connected with the first node VC through a first inverter INV1, the source of the second NMOS tube NM2 is connected with the feedback port FB, and the drain of the second NMOS tube NM2 is connected with the voltage division node.
As a preferred embodiment, wherein the voltage dividing circuit includes:
the first resistor R1 is connected between the adjustable port ADJ/NC and the voltage dividing node;
and the second resistor R2 is connected between the voltage division node and the third control circuit.
Specifically, in this embodiment, when the low dropout linear regulator is of a fixed version, the third control circuit is turned on, and at this time, the first resistor R1 and the second resistor R2 are voltage dividing resistors of the fixed version.
As a preferred embodiment, wherein the third control circuit includes:
the input end of the first NOR gate NOR1 is respectively connected with the first node and the grounding end;
the gate of the third NMOS tube NM3 is connected with the output end of the first NOR gate NOR1, the drain of the third NMOS tube NM3 is connected with the voltage dividing circuit, and the source of the third NMOS tube NM3 is connected with the grounding end.
As a preferred embodiment, when the low dropout linear regulator works normally, the first node is at a high level, the first control circuit is turned on, the second control circuit and the third control circuit are turned off, the adjustable port is connected with the feedback port, and the low dropout linear regulator is in an adjustable version.
In a preferred embodiment, when the first node is at a low level, the first control circuit is turned off, the second control circuit and the third control circuit are turned on, the adjustable port is disconnected from the feedback port, and the low dropout linear regulator is in a fixed version.
As a preferred embodiment, the adjustable port ADJ/NC is connected to the output port VOUT of the low dropout linear regulator by a bonding wire at the time of packaging.
In the preferred embodiment, the LDO comprises 6 ports, i.e., an input port VIN, an enable control port EN, a bias port VBIAS, an output port VOUT, an adjustable port ADJ/NC, and a ground port GND. The input port VIN is for receiving an input signal; the enable control port EN is used for receiving an enable control signal; the bias port VBIAS is used to provide a static bias voltage for the low dropout linear regulator.
Further comprises: input capacitance C IN Is connected between the input port VIN and the ground terminal; the output capacitor is connected between the output port VOUT and the grounding end; bias capacitor C B Connected between the bias port VBIAS and ground.
As shown in fig. 2, when the low dropout linear regulator is in a fixed version, the adjustable port ADJ/NC is connected to the output port VOUT.
As shown in fig. 3, when the low dropout linear regulator is an adjustable version, an external adjustable resistor is connected, that is, the low dropout linear regulator further includes: the third resistor R3 and the fourth resistor R3 are connected in series between the output port VOUT and the grounding end, and the junction of the third resistor R3 and the fourth resistor R3 is connected with the adjustable port ADJ/NC.
In the preferred embodiment, the first PMOS transistor M1, the first FUSE and the first depletion transistor DVTN1 constitute a logic level circuit for controlling the fixed and adjustable version switching; the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, the first inverter INV1, and the first NOR gate NOR1 constitute a fixed and adjustable version switching circuit.
When the LDO circuit works normally, the first FUSE is not fused, the bias voltage VBAIS is high, the first bias voltage VBIAS_1 starts to be established, the first PMOS tube M1 is conducted, the control signal at the first node VC is at a logic high level, the first NMOS tube NM1 is conducted, the feedback port FB of the LDO is connected with the adjustable port ADJ/NC, namely, the LDO feedback port FB is output to the adjustable port ADJ/NC. Meanwhile, the first inverter INV1 outputs a low level, the first NOR gate NOR1 outputs a logic low level, the third NMOS transistor NM3 is turned off, and the second NMOS transistor NM2 is turned off. At this time, the LDO is an adjustable version, and the output voltage VOUT can be adjusted by external adjustable resistors R3 and R4.
After the first FUSE is melted, a control signal at a first node VC is at a logic low level, a first NMOS tube NM1 is cut off, a feedback port FB of the LDO is disconnected from an adjustable port ADJ/NC, a first inverter INV1 outputs a high level, a second NMOS tube NM2 is conducted, and the feedback port FB is connected between a first resistor R1 and a second resistor R2; meanwhile, the first NOR gate NOR1 outputs a logic high level, the third NMOS tube NM3 is conducted, the adjustable port ADJ/NC is connected to the VOUT end of the LDO through a bonding wire during packaging, the output port VOUT is adjusted through the first resistor R1 and the second resistor R2, and the LDO is in a fixed version.
In the scheme, the switching between the adjustable version and the fixed version of the LDO is realized by whether the first FUSE is blown or not.
The technical scheme has the following advantages or beneficial effects: the invention provides a circuit for switching fixed and adjustable versions, which is applied to a low-dropout linear voltage regulator, and has the advantages of simple structure, small occupied area of a chip, stable performance and capability of considering the area and the performance.
The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and drawings, and are intended to be included within the scope of the present invention.
Claims (7)
1. A circuit for fixed and adjustable version switching in a low dropout linear voltage regulator, comprising:
the logic level circuit is controllably connected between a bias port and a ground terminal and is provided with a first node for outputting a control signal;
the first control circuit is controllably connected between the adjustable port and the feedback port of the low dropout linear regulator under the action of the control signal;
the second control circuit is controllably connected between the feedback port and a voltage division node under the action of an inverted signal of the control signal;
the voltage dividing circuit is connected to the adjustable port and is provided with the voltage dividing node;
the third control circuit is controllably connected between the voltage dividing circuit and the grounding end under the action of an inverted signal of the control signal;
when the low dropout linear voltage regulator works normally, the first node is in a high level, the first control circuit is conducted, the second control circuit and the third control circuit are cut off, the adjustable port is connected with the feedback port, and the low dropout linear voltage regulator is in an adjustable version;
when the first node is at a low level, the first control circuit is cut off, the second control circuit and the third control circuit are conducted, the adjustable port is disconnected with the feedback port, and the low-dropout linear voltage regulator is of a fixed version.
2. The circuit of claim 1 for use in fixed and adjustable version switching in a low dropout linear regulator, wherein said logic level circuit comprises:
the grid electrode of the first PMOS tube is connected with a first bias voltage, and the source electrode of the first PMOS tube is connected with the bias port;
a first drain, a gate and a source of the first drain being connected to the ground terminal, and a drain of the first drain being connected to the first node;
and the first fuse is connected between the drain electrode of the first PMOS tube and the first node.
3. The circuit for fixed and adjustable version switching in a low dropout linear regulator according to claim 1, wherein said first control circuit comprises:
the grid electrode of the first NMOS tube is connected with the first node, the drain electrode of the first NMOS tube is connected with the adjustable port, and the source electrode of the first NMOS tube is connected with the feedback port.
4. The circuit for fixed and adjustable version switching in a low dropout linear regulator according to claim 1, wherein said second control circuit comprises:
the grid electrode of the second NMOS tube is connected with the first node through a first inverter, the source electrode of the second NMOS tube is connected with the feedback port, and the drain electrode of the second NMOS tube is connected with the voltage division node.
5. The circuit for fixed and adjustable version switching in a low dropout linear regulator according to claim 1, wherein said voltage divider circuit comprises:
the first resistor is connected between the adjustable port and the voltage dividing node;
and the second resistor is connected between the voltage division node and the third control circuit.
6. The circuit for fixed and adjustable version switching in a low dropout linear regulator according to claim 1, wherein said third control circuit comprises:
the input end of the first NOR gate is respectively connected with the first node and the grounding end;
and the grid electrode of the third NMOS tube is connected with the output end of the first NOR gate, the drain electrode of the third NMOS tube is connected with the voltage dividing circuit, and the source electrode of the third NMOS tube is connected with the grounding end.
7. The circuit of claim 1, wherein the adjustable port is connected to the output port of the low dropout linear regulator by a bonding wire when packaged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210720611.8A CN115202429B (en) | 2022-06-23 | 2022-06-23 | Circuit for switching fixed version and adjustable version in low dropout linear voltage regulator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210720611.8A CN115202429B (en) | 2022-06-23 | 2022-06-23 | Circuit for switching fixed version and adjustable version in low dropout linear voltage regulator |
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| CN115202429A CN115202429A (en) | 2022-10-18 |
| CN115202429B true CN115202429B (en) | 2024-04-05 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1716738A (en) * | 2004-06-14 | 2006-01-04 | 惠普开发有限公司 | Protection circuits for a DC-to-DC converter |
| CN101154116A (en) * | 2006-09-28 | 2008-04-02 | 华润矽威科技（上海）有限公司 | Ultramicro power consumption reference source circuit with low temperature coefficient |
| CN110488905A (en) * | 2019-07-17 | 2019-11-22 | 南开大学深圳研究院 | Low pressure difference linear voltage regulator overload protecting circuit |
| CN111552341A (en) * | 2020-05-15 | 2020-08-18 | 电子科技大学 | Margin-adjustable output voltage margin generation circuit |
| CN114253382A (en) * | 2020-09-21 | 2022-03-29 | 英特尔公司 | Unified reservation and wake-up clamp apparatus and method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8427122B2 (en) * | 2010-02-11 | 2013-04-23 | Mediatek Singapore Pte. Ltd. | Enhancement of power supply rejection for operational amplifiers and voltage regulators |
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- 2022-06-23 CN CN202210720611.8A patent/CN115202429B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716738A (en) * | 2004-06-14 | 2006-01-04 | 惠普开发有限公司 | Protection circuits for a DC-to-DC converter |
| CN101154116A (en) * | 2006-09-28 | 2008-04-02 | 华润矽威科技（上海）有限公司 | Ultramicro power consumption reference source circuit with low temperature coefficient |
| CN110488905A (en) * | 2019-07-17 | 2019-11-22 | 南开大学深圳研究院 | Low pressure difference linear voltage regulator overload protecting circuit |
| CN111552341A (en) * | 2020-05-15 | 2020-08-18 | 电子科技大学 | Margin-adjustable output voltage margin generation circuit |
| CN114253382A (en) * | 2020-09-21 | 2022-03-29 | 英特尔公司 | Unified reservation and wake-up clamp apparatus and method |
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