CN116418324B - Phase interpolator and phase interpolation method - Google Patents
Phase interpolator and phase interpolation method Download PDFInfo
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Abstract
The invention provides a phase interpolator and a phase interpolation method, which utilize a first waveform slope adjustment circuit and a second waveform slope adjustment circuit to respectively carry out slope adjustment on waveforms of a first clock signal of a first phase and a second clock signal of a second phase, judge the degree to which the first waveform slope adjustment circuit specifically adjusts the slope of the first clock signal by combining a slope feedback circuit, and particularly judge whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit meets a preset condition or not based on the slope feedback circuit, and synchronously adjust circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit under the condition that the preset condition is not met, so that the waveform slopes of the clock signals output by the first waveform slope adjustment circuit and the second waveform slope adjustment circuit meet the preset condition, thereby ensuring that the linearity of the phase interpolator can meet the preset linearity requirement under the condition that the process angle or the temperature is changed.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a phase interpolator and a phase interpolation method.
Background
Phase interpolator (Phase Interpolator, PI) circuits play an important role in high-speed digital-to-analog hybrid circuits such as phase locked loop (PLL, phase Locked Loop) circuits, clock data recovery (CDR, clock Data Recovery) circuits, serial link transceivers, and the like. Wherein the phase interpolator is a circuit having two periodic input signals, which signals typically have the same oscillation period and are derived from the same source. These two input signals are generally referred to herein as 0 ° and 45 ° or 0 ° and 90 ° of the clock signal.
When a clock signal at a certain phase between the phases of an input signal is acquired by a phase interpolator, the phase interpolation is usually realized by controlling the intensity of an output driver (driver) through an overlap region (overlap) between waveforms of the input phase0 and phase90 (or phase0 and phase45, etc.). In this way, the phase interpolator can achieve relatively good linearity at a single process angle and temperature. However, as the process angle and/or temperature changes, the overlap between the input signals phase0 and phase90 may change to different extents, which may result in a poor linearity of the phase of the clock signal output by the phase interpolator.
Disclosure of Invention
The invention provides a phase interpolator and a phase interpolation method, which are used for solving the defect that the linearity of the phase of a clock signal output by the phase interpolator in the prior art is affected by a process angle and temperature to cause the linearity to be poor.
The invention provides a phase interpolator, comprising:
a first waveform slope adjustment circuit and a slope feedback circuit for a first clock signal of a first phase, a second waveform slope adjustment circuit for a second clock signal of a second phase, and a phase interpolation circuit comprising a plurality of parallel multiplexers;
the output ends of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit for adjusting the waveform slope of the input clock signal are connected with the input end of each multiplexer in the phase interpolation circuit, and the phase interpolation circuit is used for outputting a third clock signal of a third phase; the output end of the first waveform slope adjustment circuit is connected with the input end of the corresponding slope feedback circuit, the slope feedback circuit is used for judging whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit meets the preset condition, and the judging result is used for adjusting the circuit parameters of the first waveform slope adjustment circuit; the first waveform slope adjustment circuit and the second waveform slope adjustment circuit have the same structure and circuit parameters.
According to the phase interpolator provided by the invention, the first waveform slope adjustment circuit or the second waveform slope adjustment circuit specifically comprises: a driver and a digital-to-analog converter connected in series; the digital-to-analog converter is constructed based on an RC low-pass filter, and a judgment result obtained by judging whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit meets a preset condition is used for adjusting the circuit parameters of the digital-to-analog converter.
According to the phase interpolator provided by the invention, the slope feedback circuit judges whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit meets the preset condition or not, and the judgment result obtained by the slope feedback circuit is used for adjusting the resistance value or the capacitance value of the digital-to-analog converter.
According to the invention, the driver comprises a PMOS transistor and an NMOS transistor which are connected in series.
According to the phase interpolator provided by the invention, the slope feedback circuit comprises a comparator, wherein the comparator is used for comparing the current output clock signal waveform of the first waveform slope adjustment circuit with a preset fixed threshold value and outputting the current comparison result; and when the result of sampling the current comparison result based on the second clock signal of the second phase is 0, the waveform slope of the clock signal output by the first waveform slope adjustment circuit is indicated to meet a preset condition.
The invention also provides a phase interpolation method based on the phase interpolator, which comprises the following steps:
after receiving corresponding clock signals, a first waveform slope adjustment circuit aiming at a first clock signal of a first phase and a second waveform slope adjustment circuit aiming at a second clock signal of a second phase carry out slope adjustment on waveforms of the corresponding clock signals based on current circuit parameters of the first waveform slope adjustment circuit and current circuit parameters of the second waveform slope adjustment circuit, so as to obtain a fourth clock signal output by the first waveform slope adjustment circuit and a fifth clock signal output by the second waveform slope adjustment circuit;
after receiving the fourth clock signal and the fifth clock signal, a plurality of parallel multiplexers in the phase interpolation circuit perform signal selection based on the multiplexers, and synthesize a third clock signal of a third phase based on a signal selection result;
and after receiving a fourth clock signal output by the first waveform slope adjustment circuit, the slope feedback circuit for the first clock signal of the first phase judges whether the waveform slope of the fourth clock signal meets a preset condition or not, and adjusts circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit based on a judging result of the slope feedback circuit.
According to the phase interpolation method provided by the invention, after the slope feedback circuit of the first clock signal aiming at the first phase receives the fourth clock signal output by the first waveform slope adjustment circuit, judging whether the waveform slope of the fourth clock signal meets the preset condition or not, specifically comprising:
comparing the waveform of the fourth clock signal currently output by the first waveform slope adjustment circuit with a preset fixed threshold value based on a comparator in the slope feedback circuit, and outputting a current comparison result;
if the result of sampling the current comparison result output by the comparator based on the second clock signal of the second phase is 0, determining that the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit meets a preset condition;
otherwise, determining that the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit does not meet a preset condition.
According to the phase interpolation method provided by the invention, the circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit are adjusted based on the judging result of the slope feedback circuit, and the method specifically comprises the following steps:
and when the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit is determined not to meet the preset condition, adjusting the resistance value or the capacitance value of the digital-to-analog converter in the first waveform slope adjustment circuit and the second waveform slope adjustment circuit.
According to the phase interpolation method provided by the invention, the adjusting the resistance value or the capacitance value of the digital-to-analog converter in the first waveform slope adjusting circuit and the second waveform slope adjusting circuit specifically comprises:
and increasing or decreasing the resistance value or the capacitance value of the digital-to-analog converter in the first waveform slope adjustment circuit and the second waveform slope adjustment circuit based on a preset step length.
According to the phase interpolation method provided by the invention, the preset step length is determined based on the linearity error threshold value of the phase interpolator, and the smaller the linearity error threshold value of the phase interpolator is, the smaller the preset step length is.
The invention provides a phase interpolator and a phase interpolation method, which utilize a first waveform slope adjustment circuit and a second waveform slope adjustment circuit to respectively carry out slope adjustment on waveforms of a first clock signal of a first phase and a second clock signal of a second phase, judge the degree to which the first waveform slope adjustment circuit specifically adjusts the slope of the first clock signal by combining a slope feedback circuit, and judge whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit meets a preset condition or not specifically based on the slope feedback circuit, and synchronously adjust circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit under the condition that the preset condition is not met, so that the waveform slopes of the clock signals output by the first waveform slope adjustment circuit and the second waveform slope adjustment circuit meet the preset condition, thereby ensuring that the linearity of the phase interpolator meets the preset linearity requirement; in addition, even if the process angle or the temperature changes, the slope feedback circuit can capture the change of the waveform slope of the clock signal output by the first waveform slope adjustment circuit caused by the process angle or the temperature change, so that the circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit are adjusted in real time, the waveform slopes of the fourth clock signal and the fifth clock signal respectively output by the first waveform slope adjustment circuit and the second waveform slope adjustment circuit can meet the preset condition again, and the linearity of the phase interpolator is ensured not to be damaged by the influence of the process angle or the temperature change.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a phase interpolator according to the present invention;
FIG. 2 is a schematic diagram of a circuit structure of a first or a second waveform slope adjustment circuit according to the present invention;
FIG. 3 is a schematic flow chart of a phase interpolation method according to the present invention;
FIG. 4 is a flow chart of a waveform slope determination method according to the present invention;
reference numerals:
110: a first waveform slope adjustment circuit; 120: a slope feedback circuit;
130: a second waveform slope adjustment circuit; 140: a phase interpolation circuit;
150: a multiplexer; 210: a driver; 220: a digital-to-analog converter.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
When a clock signal at a certain phase between the phases of an input signal is acquired by a phase interpolator, the phase interpolation is usually implemented by controlling the intensity of an output driver by an overlap between input waveforms of phase0 and phase90 (or phase0 and phase45, etc.). In this way, the phase interpolator can achieve relatively good linearity at a single process angle and temperature. However, as the process angle and/or temperature changes, the overlap between the input signals phase0 and phase90 may change to different extents, which may result in a poor linearity of the phase of the clock signal output by the phase interpolator.
In this regard, the present invention provides a phase interpolator. Fig. 1 is a schematic circuit diagram of a phase interpolator according to the present invention, as shown in fig. 1, where the phase interpolator includes: a first waveform slope adjustment circuit 110 and a slope feedback circuit 120 for a first clock signal of a first phase, a second waveform slope adjustment circuit 130 for a second clock signal of a second phase, and a phase interpolation circuit 140 comprising a plurality of parallel multiplexers 150.
Wherein the first phase and the second phase are different, in some embodiments the first phase may be 0 ° and the second phase may be 90 °. The circuit structures and circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 remain the same, and both of the waveform slope adjustment circuits are used to adjust the waveform slope of the input clock signal, i.e., the slew rate of the input clock signal. Specifically, the first waveform slope adjustment circuit 110 is configured to adjust a waveform slope of the first clock signal, and the second waveform slope adjustment circuit 130 is configured to adjust a waveform slope of the second clock signal. Here, since the circuit configuration and circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 remain the same, the clock signals adjusted by the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are identical in waveform slope except for the phase difference.
The output terminals of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are connected to the input terminal of each of the multiplexers 150 in the phase interpolation circuit 140, so that the respective multiplexers 150 in the phase interpolation circuit 140 can perform signal selection, and a third clock signal of a third phase can be generated by synthesizing according to the clock signals selected by the respective multiplexers 150, wherein the third phase is between the first phase and the second phase (including the first phase and the second phase). When the fourth clock signal of the first phase output by the first waveform slope adjustment circuit 110 and the fifth clock signal of the second phase output by the second waveform slope adjustment circuit 130 are input to the multiplexers 150, each multiplexer 150 selects from the fourth clock signal and the fifth clock signal according to the control signal, and different selection results of the multiplexers 150 can generate clock signals of different phases. Here, in order to ensure the performance of the external circuit, it is necessary to ensure that the linearity of the phase interpolator meets the preset requirement, and the linearity of the phase interpolator is determined by the waveform slopes of the fourth clock signal and the fifth clock signal, if the preset linearity requirement needs to be met, the waveform slopes of the first clock signal and the second clock signal may be adjusted so that the slopes of the fourth clock signal and the fifth clock signal obtained after the adjustment meet the preset condition.
Therefore, the slope feedback circuit 120 may be used to assist in adjusting the slope of the first clock signal, and the first waveform slope adjustment circuit 110 may determine the slope feedback circuit 120 to which extent the slope of the first clock signal is specifically adjusted. The output end of the first waveform slope adjustment circuit 110 is connected to the input end of the corresponding slope feedback circuit 120, the slope feedback circuit 120 can determine whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit 110 meets a preset condition, and the determination result can be used to adjust the circuit parameters of the first waveform slope adjustment circuit 110.
In some embodiments, the slope feedback circuit 120 includes a comparator for comparing the current output clock signal waveform of the first waveform slope adjustment circuit 110 with a preset fixed threshold (e.g. 0.9 times the power supply), and outputting the current comparison result. The fixed threshold can be obtained through pre-experiments under the conditions of a single process angle and temperature based on the preset linearity, and if the rising edge of any clock signal waveform can reach the fixed threshold in a fixed time, the slope of the clock signal waveform meets the preset condition. Therefore, in order to confirm whether the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit 110 meets the preset condition, the waveform corresponding to the current comparison result may be sampled (sample) by using the second clock signal (for example, the clock signal of phase 90) of the second phase based on the current comparison result output by the comparator, and whether the waveform slope of the fourth clock signal meets the preset condition may be determined according to the sampling result. Here, if the sampling result is 0, it indicates that the waveform slope of the fourth clock signal output by the first waveform slope adjustment circuit 110 meets the preset condition; otherwise, it indicates that the waveform slope of the fourth clock signal output by the first waveform slope adjustment circuit 110 does not meet the preset condition and needs to be adjusted again. Therefore, based on the above-mentioned determination result of the slope feedback circuit 120, the circuit parameters of the first waveform slope adjustment circuit 110 may be adjusted, so that the waveform slope of the fourth clock signal output by the adjusted first waveform slope adjustment circuit 110 satisfies the preset condition.
In other embodiments, as shown in fig. 2, the first waveform slope adjustment circuit 110 or the second waveform slope adjustment circuit 130 specifically includes: a driver 210 and a digital-to-analog converter 220 in series; the dac 220 is configured based on an RC low-pass filter, and the determination result obtained by the slope feedback circuit 120 determining whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit 110 meets the preset condition is used to adjust the circuit parameters of the dac 220, and specifically may be used to adjust the resistance value or the capacitance value of the dac 220. The driver 210 includes a PMOS transistor and an NMOS transistor connected in series, and its driving capability is determined by its load (i.e., digital-to-analog converter), so that the driver 210 and the digital-to-analog converter 220 connected in series can adjust the waveform slope of the input clock signal to different degrees.
It should be noted that, the circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 may be adjusted synchronously, so as to ensure that the circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are the same, so that the waveform slopes of the fourth clock signal and the fifth clock signal respectively output by the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are the same and all satisfy the preset condition.
It can be seen that, through the feedback adjustment, even if the current circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 cannot enable the waveform slopes of the fourth clock signal and the fifth clock signal output by the current circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 to meet the preset conditions, the slope feedback circuit 120 can capture the variation of the waveform slopes of the fourth clock signal caused by the process angle or the temperature variation, so as to adjust the circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 in real time, so that the waveform slopes of the fourth clock signal and the fifth clock signal respectively output by the current circuit parameters can meet the preset conditions again, and the linearity of the phase interpolator is ensured not to be damaged due to the influence of the process angle or the temperature variation.
In summary, in the phase interpolator provided by the embodiment of the present invention, the first waveform slope adjustment circuit and the second waveform slope adjustment circuit are used to respectively perform slope adjustment on waveforms of the first clock signal of the first phase and the second clock signal of the second phase, and the slope feedback circuit is combined to determine to what extent the first waveform slope adjustment circuit specifically adjusts the slope of the first clock signal, and the slope feedback circuit is specifically based on whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit meets a preset condition, and circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit are synchronously adjusted under the condition that the preset condition is not met, so that the waveform slopes of the clock signals output by the first waveform slope adjustment circuit and the second waveform slope adjustment circuit meet the preset condition, thereby ensuring that the linearity of the phase interpolator meets the preset linearity requirement; in addition, even if the process angle or the temperature changes, the slope feedback circuit can capture the change of the waveform slope of the clock signal output by the first waveform slope adjustment circuit caused by the process angle or the temperature change, so that the circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit are adjusted in real time, the waveform slopes of the fourth clock signal and the fifth clock signal respectively output by the first waveform slope adjustment circuit and the second waveform slope adjustment circuit can meet the preset condition again, and the linearity of the phase interpolator is ensured not to be damaged by the influence of the process angle or the temperature change.
The phase interpolation method provided by the invention is described below, and the phase interpolation method described below and the phase interpolation circuit described above can be referred to correspondingly to each other.
Based on any of the above embodiments, fig. 3 is a schematic flow chart of a phase interpolation method according to the present invention, where the phase interpolation method is based on the phase interpolator according to the above embodiment. As shown in fig. 3, the method includes:
step 310, after receiving the corresponding clock signals, a first waveform slope adjustment circuit for a first clock signal of a first phase and a second waveform slope adjustment circuit for a second clock signal of a second phase, performing slope adjustment on waveforms of the corresponding clock signals based on current circuit parameters of the first waveform slope adjustment circuit and current circuit parameters of the second waveform slope adjustment circuit, so as to obtain a fourth clock signal output by the first waveform slope adjustment circuit and a fifth clock signal output by the second waveform slope adjustment circuit;
step 320, after receiving the fourth clock signal and the fifth clock signal, a plurality of parallel multiplexers in the phase interpolation circuit perform signal selection based on the multiplexers, and synthesize a third clock signal of a third phase based on a signal selection result;
step 330, after receiving the fourth clock signal output by the first waveform slope adjustment circuit, the slope feedback circuit for the first clock signal of the first phase determines whether the waveform slope of the fourth clock signal meets a preset condition, and adjusts the circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit based on the determination result of the slope feedback circuit.
Specifically, after the first waveform slope adjustment circuit 110 for the first clock signal of the first phase receives the first clock signal and the second waveform slope adjustment circuit 130 for the second clock signal of the second phase receives the second clock signal, the waveforms of the corresponding clock signals are slope-adjusted based on the current circuit parameters of the first waveform slope adjustment circuit 110 and the current circuit parameters of the second waveform slope adjustment circuit 130, so as to obtain the fourth clock signal output by the first waveform slope adjustment circuit 110 and the fifth clock signal output by the second waveform slope adjustment circuit 130. The circuit structures of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are the same as the current circuit parameters, so that the fourth clock signal and the fifth clock signal adjusted by the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 have the same waveform slope except for different phases.
After receiving the fourth clock signal and the fifth clock signal, the plurality of parallel multiplexers 150 in the phase interpolation circuit 140 perform signal selection based on the respective multiplexers 150, and synthesize a third clock signal of a third phase based on the signal selection result. Wherein the third phase is between (including) the first phase and the second phase. Specifically, when the fourth clock signal of the first phase output by the first waveform slope adjustment circuit 110 and the fifth clock signal of the second phase output by the second waveform slope adjustment circuit 130 are input to the multiplexers 150, each multiplexer 150 selects from the fourth clock signal and the fifth clock signal according to the control signal, and different selection results of the multiplexers 150 may generate clock signals of different phases. Here, in order to ensure the performance of the external circuit, it is necessary to ensure that the linearity of the phase interpolator meets the preset requirement, and the linearity of the phase interpolator is determined by the waveform slopes of the fourth clock signal and the fifth clock signal, if the preset linearity requirement needs to be met, the waveform slopes of the first clock signal and the second clock signal may be adjusted so that the slopes of the fourth clock signal and the fifth clock signal obtained after the adjustment meet the preset condition.
Therefore, the slope feedback circuit 120 can assist in adjusting the slope of the first clock signal, so as to determine to what extent the slope of the first clock signal is adjusted by the first waveform slope adjustment circuit 110. After the slope feedback circuit 120 for the first clock signal of the first phase receives the fourth clock signal output by the first waveform slope adjustment circuit 110, it determines whether the waveform slope of the fourth clock signal meets the preset condition, and based on the determination result of the slope feedback circuit 120, the circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 can be appropriately adjusted.
In some embodiments, as shown in fig. 4, after receiving a fourth clock signal output by the first waveform slope adjustment circuit, the slope feedback circuit for the first clock signal of the first phase determines whether the waveform slope of the fourth clock signal meets a preset condition, which specifically includes:
step 410, comparing the waveform of the fourth clock signal currently output by the first waveform slope adjustment circuit with a preset fixed threshold value based on a comparator in the slope feedback circuit, and outputting a current comparison result;
step 420, if the result of sampling the current comparison result output by the comparator based on the second clock signal of the second phase is 0, determining that the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit meets a preset condition;
step 430, otherwise, determining that the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit does not meet the preset condition.
Specifically, the waveform of the fourth clock signal currently output by the first waveform slope adjustment circuit 110 is compared with a preset fixed threshold (e.g., 0.9 times the power supply) based on a comparator in the slope feedback circuit 120, and the current comparison result is output. The fixed threshold can be obtained through pre-experiments under the conditions of a single process angle and temperature based on the preset linearity, and if the rising edge of any clock signal waveform can reach the fixed threshold in a fixed time, the slope of the clock signal waveform meets the preset condition. Therefore, in order to confirm whether the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit 110 meets the preset condition, the waveform corresponding to the current comparison result may be sampled (sample) by using the second clock signal (for example, the clock signal of phase 90) of the second phase based on the current comparison result output by the comparator, and whether the waveform slope of the fourth clock signal meets the preset condition may be determined according to the sampling result. Here, if the sampling result is 0, it indicates that the waveform slope of the fourth clock signal output by the first waveform slope adjustment circuit 110 meets the preset condition; otherwise, it indicates that the waveform slope of the fourth clock signal output by the first waveform slope adjustment circuit 110 does not meet the preset condition and needs to be adjusted again.
Therefore, based on the above-mentioned determination result of the slope feedback circuit 120, the circuit parameters of the first waveform slope adjustment circuit 110 may be adjusted, so that the waveform slope of the fourth clock signal output by the adjusted first waveform slope adjustment circuit 110 satisfies the preset condition. After the above adjustment, when the result of sampling the current comparison result output by the comparator based on the second clock signal of the second phase is switched from non-0 to 0, that is, the circuit parameters representing the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are adjusted, the waveform slope of the output clock signal meets the preset condition.
In other embodiments, when it is determined that the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit does not meet the preset condition, the adjustment of the circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 can be achieved by adjusting the resistance value or the capacitance value of the digital-to-analog converter 220 in the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130, so as to achieve the adjustment of the waveform slopes of the output clock signals. Specifically, when the resistance value or the capacitance value of the digital-to-analog converter 220 in the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are adjusted, the resistance value or the capacitance value of the digital-to-analog converter 220 in the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 can be gradually increased or decreased based on a preset step. The magnitude of the preset step represents the adjustment amplitude of the resistance value or the capacitance value in the digital-to-analog converter 220, and the larger the preset step is, the larger the adjustment amplitude is, and the more obvious the change of the waveform slope of the input clock signal is.
When determining whether the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are adjusted, a result of sampling the current comparison result output by the comparator based on the second clock signal of the second phase is switched from non-0 to 0 as a flag. When the result of sampling the current comparison result output by the comparator based on the second clock signal of the second phase is switched from non-0 to 0, there may be a plurality of parameters capable of satisfying that the result of sampling the current comparison result output by the comparator based on the second clock signal of the second phase is 0 between the two resistance values/capacitance values before and after the adjustment, and the most accurate resistance value/capacitance value switched from non-0 to 0 is among the parameters. That is, the maximum error of the resistance value/capacitance value determined at this time is a preset step. Thus, when determining the preset step size, the preset step size may be determined based on a linearity error threshold value set for the phase interpolator, the smaller the linearity error threshold value of the phase interpolator, which indicates that the higher the accuracy requirement for linearity, the smaller the preset step size is set.
It should be noted that, the circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 may be adjusted synchronously, so as to ensure that the circuit parameters of the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are the same, so that the waveform slopes of the fourth clock signal and the fifth clock signal respectively output by the first waveform slope adjustment circuit 110 and the second waveform slope adjustment circuit 130 are the same and all satisfy the preset condition.
Therefore, in the phase interpolation method provided by the embodiment of the invention, the first waveform slope adjustment circuit and the second waveform slope adjustment circuit are utilized to respectively carry out slope adjustment on the waveforms of the first clock signal of the first phase and the second clock signal of the second phase, the slope feedback circuit is combined to judge to what degree the first waveform slope adjustment circuit specifically adjusts the slope of the first clock signal, and the slope feedback circuit is particularly used for judging whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit meets the preset condition or not, and the circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit are synchronously adjusted under the condition that the preset condition is not met, so that the waveform slopes of the clock signals output by the first waveform slope adjustment circuit and the second waveform slope adjustment circuit meet the preset condition, and the linearity of the phase interpolator is ensured to meet the preset linearity requirement; in addition, even if the process angle or the temperature changes, the slope feedback circuit can capture the change of the waveform slope of the clock signal output by the first waveform slope adjustment circuit caused by the process angle or the temperature change, so that the circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit are adjusted in real time, the waveform slopes of the fourth clock signal and the fifth clock signal respectively output by the first waveform slope adjustment circuit and the second waveform slope adjustment circuit can meet the preset condition again, and the linearity of the phase interpolator is ensured not to be damaged by the influence of the process angle or the temperature change.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A phase interpolator, comprising:
a first waveform slope adjustment circuit and a slope feedback circuit for a first clock signal of a first phase, a second waveform slope adjustment circuit for a second clock signal of a second phase, and a phase interpolation circuit comprising a plurality of parallel multiplexers;
the output ends of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit for adjusting the waveform slope of the input clock signal are connected with the input end of each multiplexer in the phase interpolation circuit, and the phase interpolation circuit is used for outputting a third clock signal of a third phase; the output end of the first waveform slope adjustment circuit is connected with the input end of the corresponding slope feedback circuit, the slope feedback circuit is used for judging whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit meets the preset condition, and the judging result is used for adjusting the circuit parameters of the first waveform slope adjustment circuit; the first waveform slope adjustment circuit and the second waveform slope adjustment circuit have the same structure and circuit parameters.
2. The phase interpolator of claim 1, wherein the first waveform slope adjustment circuit or the second waveform slope adjustment circuit specifically comprises: a driver and a digital-to-analog converter connected in series; the digital-to-analog converter is constructed based on an RC low-pass filter, and a judgment result obtained by judging whether the waveform slope of the clock signal output by the first waveform slope adjustment circuit meets a preset condition is used for adjusting the circuit parameters of the digital-to-analog converter.
3. The phase interpolator according to claim 2, wherein the slope feedback circuit determines whether the waveform slope of the clock signal output from the first waveform slope adjustment circuit satisfies a predetermined condition, and the determined result is used to adjust the resistance value or the capacitance value of the digital-to-analog converter.
4. The phase interpolator of claim 2, wherein the driver comprises one PMOS transistor and one NMOS transistor in series.
5. The phase interpolator of claim 1, wherein the slope feedback circuit comprises a comparator for comparing a current output clock signal waveform of the first waveform slope adjustment circuit with a predetermined fixed threshold and outputting a current comparison result; and when the result of sampling the current comparison result based on the second clock signal of the second phase is 0, the waveform slope of the clock signal output by the first waveform slope adjustment circuit is indicated to meet a preset condition.
6. A phase interpolation method based on a phase interpolator according to any of claims 1 to 5, comprising:
after receiving corresponding clock signals, a first waveform slope adjustment circuit aiming at a first clock signal of a first phase and a second waveform slope adjustment circuit aiming at a second clock signal of a second phase carry out slope adjustment on waveforms of the corresponding clock signals based on current circuit parameters of the first waveform slope adjustment circuit and current circuit parameters of the second waveform slope adjustment circuit, so as to obtain a fourth clock signal output by the first waveform slope adjustment circuit and a fifth clock signal output by the second waveform slope adjustment circuit;
after receiving the fourth clock signal and the fifth clock signal, a plurality of parallel multiplexers in the phase interpolation circuit perform signal selection based on the multiplexers, and synthesize a third clock signal of a third phase based on a signal selection result;
and after receiving a fourth clock signal output by the first waveform slope adjustment circuit, the slope feedback circuit for the first clock signal of the first phase judges whether the waveform slope of the fourth clock signal meets a preset condition or not, and adjusts circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit based on a judging result of the slope feedback circuit.
7. The method of phase interpolation according to claim 6, wherein the determining, by the slope feedback circuit for the first clock signal of the first phase, whether the waveform slope of the fourth clock signal satisfies a preset condition after receiving the fourth clock signal output by the first waveform slope adjustment circuit, includes:
comparing the waveform of the fourth clock signal currently output by the first waveform slope adjustment circuit with a preset fixed threshold value based on a comparator in the slope feedback circuit, and outputting a current comparison result;
if the result of sampling the current comparison result output by the comparator based on the second clock signal of the second phase is 0, determining that the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit meets a preset condition;
otherwise, determining that the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit does not meet a preset condition.
8. The method according to claim 6, wherein the adjusting circuit parameters of the first waveform slope adjustment circuit and the second waveform slope adjustment circuit based on the determination result of the slope feedback circuit specifically includes:
and when the waveform slope of the fourth clock signal currently output by the first waveform slope adjustment circuit is determined not to meet the preset condition, adjusting the resistance value or the capacitance value of the digital-to-analog converter in the first waveform slope adjustment circuit and the second waveform slope adjustment circuit.
9. The method of phase interpolation according to claim 8, wherein the adjusting the resistance or capacitance of the digital-to-analog converter in the first and second waveform slope adjustment circuits comprises:
and increasing or decreasing the resistance value or the capacitance value of the digital-to-analog converter in the first waveform slope adjustment circuit and the second waveform slope adjustment circuit based on a preset step length.
10. The phase interpolation method of claim 9, wherein the preset step size is determined based on a linearity error threshold of the phase interpolator, the smaller the preset step size.
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| JP2013201693A (en) * | 2012-03-26 | 2013-10-03 | Toshiba Corp | Phase interpolator and phase interpolation method |
| CN105247789A (en) * | 2013-06-28 | 2016-01-13 | 英特尔公司 | Pulse width modular for voltage regulator |
| CN112202426A (en) * | 2020-10-16 | 2021-01-08 | 中国科学院微电子研究所 | Phase interpolator applied to multi-rate high linearity and circuit adopting same |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
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| US7205811B2 (en) * | 2005-03-31 | 2007-04-17 | Agere Systems Inc. | Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias |
| CN103036537B (en) * | 2011-10-09 | 2016-02-17 | 瑞昱半导体股份有限公司 | The production method of phase interpolator, leggy interpolation device and interior interpolated clock |
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| JP2013201693A (en) * | 2012-03-26 | 2013-10-03 | Toshiba Corp | Phase interpolator and phase interpolation method |
| CN105247789A (en) * | 2013-06-28 | 2016-01-13 | 英特尔公司 | Pulse width modular for voltage regulator |
| CN112202426A (en) * | 2020-10-16 | 2021-01-08 | 中国科学院微电子研究所 | Phase interpolator applied to multi-rate high linearity and circuit adopting same |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
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