JP2013201693A - Phase interpolator and phase interpolation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate such a phase interpolation signal as changes in phase linearly with a value of code data.SOLUTION: A phase interpolator 1 includes: a first current signal generation section 2 for generating a plurality of first current signals corresponding to values of multi-bit code data; a code data regulation section 3 for incrementing/decrementing the value of the code data by a predetermined value in accordance with the value of the code data; a second current signal generation section 4 for generating a plurality of second current signals corresponding to the values of the code data incremented/decremented by the code data regulation section; and a mixer section 5 for combining a first composite signal combining clock signals resulting from adjusting respective amplitudes of a plurality of first clock signals out of phase on the basis of corresponding first current signals and a second composite signal combining clock signals resulting from adjusting respective amplitudes of a plurality of second clock signals out of phase with each other and out of phase with the plurality of clock signals on the basis of corresponding second current signals to generate a phase interpolation signal.

Description

  Embodiments described herein relate generally to a phase interpolator and a phase interpolation method for generating a phase interpolation signal.

  As miniaturization of semiconductor integrated circuits progresses, the amount of data transmitted and received between semiconductor integrated circuits tends to increase year by year, and a technique for transmitting data at high speed is required. In order to process externally input data in the semiconductor integrated circuit, it is necessary to synchronize with a clock signal. The faster the data, the more difficult it is to synchronize with the clock signal.

  For this reason, a clock recovery circuit has been proposed in which a phase interpolator is used to generate a plurality of clock signals with different phases, and any one of these clock signals can be selected to reliably capture data. ing.

  This type of conventional phase interpolator generates an intermediate phase clock signal from four phase clock signals having different phases, and weights these intermediate phase clock signals to generate a new phase clock signal. As a result, a clock signal having a phase corresponding to code data composed of a plurality of bits can be generated.

  However, the relationship between the code data of the clock signal generated by the conventional phase interpolator and the phase change amount is not necessarily linear, and the phase change amount varies depending on the value of the code data. For this reason, when the phase interpolator is incorporated in the clock restoration circuit described above, the amount of phase change of the phase interpolation signal generated by the phase interpolator is not constant, so that there is a possibility that data may not be captured correctly depending on circumstances.

US Patent Publication No. 7,307,560

  The present invention provides a phase interpolator and a phase interpolation method capable of generating a phase interpolation signal whose phase changes linearly according to the value of code data.

According to this embodiment, a first current signal generation unit that generates a plurality of first current signals according to the value of code data consisting of a plurality of bits,
A code data adjustment unit that increases or decreases the value of the code data by a predetermined value in accordance with the value of the code data;
A second current signal generation unit that generates a plurality of second current signals according to the value of the code data after increase / decrease in the code data adjustment unit;
A first synthesized signal obtained by synthesizing clock signals obtained by adjusting amplitudes of a plurality of first clock signals having different phases based on the corresponding first current signals, and a plurality of first clock signals having different phases, respectively. A mixer unit that generates a phase interpolation signal by synthesizing a second synthesized signal obtained by synthesizing clock signals adjusted based on the second current signals corresponding to the amplitudes of a plurality of second clock signals having different phases. A phase interpolator is provided.

1 is a block diagram showing a schematic configuration of a phase interpolator 1 according to the present embodiment. The figure explaining operation | movement of the phase interpolator 1 which concerns on this embodiment. The figure which shows the phase range of the clock signal used when the mixer part 5 produces | generates a phase interpolation signal with a phase of 0-90 degree | times. The figure which shows the conceptual operation | movement of the phase interpolator 1 of FIG. 1 within the range whose phase of a phase interpolation signal is 0-90 degree | times. The figure which shows the kind of clock signal which the mixer part 5 uses for a synthesis | combination about a total of 8 area | regions which divided 0-360 degree | times into 45 degree | times. FIG. 2 is a circuit diagram showing an example of a detailed configuration of a mixer unit 5 in the block diagram of FIG. 1. (A) is a figure which shows the waveform of the electric currents Ideg0, Ideg45, Ideg90, Ideg135, Ideg315 which flow through the current sources IS4, IS8, IS3, IS7 and IS5 within the range of the phase 0 to 90 degrees, and (a) is the phase 0 to The figure which shows the waveform of the electric currents Ideg0, Ideg45, Ideg90, Ideg135, Ideg315 which flow through the current sources IS4, IS8, IS3, IS7, IS5 within the range of 90 degrees. The figure which displayed by overlapping the signal waveform of the various phase interpolation signals from which a phase differs in the range of 0-90 degree | times of phases. The figure which shows the signal waveform of the phase interpolation signal output from the mixer part 5 which does not perform the synthetic | combination process by the 1st and 2nd current signal generation parts 2 and 4. FIG. The figure which shows the kind of electric current signal which the 1st and 2nd electric current signal production | generation parts 2 and 4 produce | generate for every 45 degree phase range. The figure which shows the change of the signal waveform of a phase interpolation signal at the time of changing a frequency. The conceptual diagram of the phase interpolator 1 which produces | generates a phase interpolation signal using a three-phase clock signal. The figure which compared the linearity of the phase interpolation signal when not performing with the case where a linearization process is performed. The conceptual diagram of the phase interpolator 1 which produces | generates a phase interpolation signal using an N-phase clock signal. The conceptual diagram in the case of performing the linearization process of a phase interpolation signal in the range of 0-2 (pi) / N of the phase of a phase interpolation signal using the phase interpolator 1 of FIG.

  Hereinafter, the phase interpolator according to the present embodiment will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a phase interpolator 1 according to the present embodiment. The phase interpolator 1 shown in FIG. 1 generates an intermediate phase phase interpolated signal from four phase clock signals having different phases. More specifically, for each 90-degree phase range, two clock signals are selected from four-phase clock signals, and a total of 20 phase interpolation signals are generated using these two clock signals. Accordingly, in the 360 degree phase range, a total of 20 × 4 = 80 phase interpolation signals are generated. Which of these 80 phase interpolation signals is generated is determined by the value of code data input from the outside. That is, the phase interpolator 1 in FIG. 1 generates a phase interpolation signal having a phase corresponding to the value of the code data.

  The number of phase interpolation signals to be provided depends on the type of code data and may be arbitrarily changed.

  The phase interpolator 1 in FIG. 1 is characterized in that the relationship between the value of the code data and the phase of the phase interpolation signal is as linear as possible. Hereinafter, this feature will be described in detail.

  The phase interpolator 1 in FIG. 1 includes a first current signal generation unit 2, a code data adjustment unit 3, a second current signal generation unit 4, and a mixer unit 5.

  The first current signal generator 2 generates a plurality of first current signals according to the value of the code data composed of a plurality of bits. In the example of FIG. 1, the first current signal generator 2 generates four types of current signals Ideg0, Ideg90, Ideg180, and Ideg270 according to the value of the code data. Two of these current signals are zero, and the other two current values change linearly according to the value of the code data. As described above, the first current signal generation unit 2 is a D / A converter (DAC) that converts digital code data into an analog current signal. Since the current signal I is generated, it is also called IDAC.

  The code data adjustment unit 3 increases or decreases the value of the code data by a predetermined value according to the value of the code data. The role of the code data adjustment unit 3 will be described later. For example, the value of the code data is increased or decreased by 10 for each phase range of 45 degrees.

  The second current signal generation unit 4 generates a plurality of second current signals according to the value of the code data after increase / decrease by the code data adjustment unit 3. In the example of FIG. 1, the second current signal generator 4 generates four types of current signals Ideg45, Ideg135, Ideg225, and Ideg315 according to the value of the code data. Two of these current signals are zero, and the other two current values change linearly according to the value of the code data. As described above, the second current signal generation unit 4 is a D / A converter that converts digital code data into an analog current signal in the same manner as the first current signal generation unit 2 described above.

  As will be described later, the second current signal generation unit 4 is used to linearize the phase interpolation signal, and generates a current signal different from the first current signal generation unit 2 and supplies the current signal to the mixer unit 5.

  The mixer unit 5 includes a first synthesized signal obtained by synthesizing clock signals obtained by adjusting amplitudes of a plurality of first clock signals having different phases based on corresponding first current signals, and a plurality of first clock signals. A phase interpolation signal is generated by synthesizing a second synthesized signal obtained by synthesizing clock signals in which the amplitudes of the plurality of second clock signals having different phases are adjusted based on the corresponding second current signal.

  The mixer unit 5 generates a linearized phase interpolation signal by synthesizing the first synthesized signal and the second synthesized signal for each predetermined phase range (for example, 45 degrees) of the phase interpolation signal.

  As will be described later, the mixer unit 5 switches the type of the clock signal used for synthesizing the first synthesized signal every 90 degrees, and switches the type of the clock signal used for synthesizing the second synthesized signal every 45 degrees. Since the mixer unit 5 synthesizes the first synthesized signal and the second synthesized signal to generate a phase interpolation signal, the mixer unit 5 performs a method of linearizing the phase interpolation signal for each phase range of 45 degrees. Will be switched.

  FIG. 2 is a diagram for explaining the operation of the phase interpolator 1 according to this embodiment. In FIG. 2, the horizontal axis represents the value of the code data, and the vertical axis represents the phase α of the phase interpolation signal. A solid curve cb1 in FIG. 2 represents the relationship between the phase α and the code data value of the phase interpolation signal generated by synthesizing the clock signal having the phase 0 degree and the clock signal having the phase 90 degrees. The solid line curve cb1 represents a phase interpolation signal when the phase interpolator 1 is configured by only the first current signal generation unit 2 and the mixer unit 5 without providing the code data adjustment unit 3 and the second current signal generation unit 4. Represents.

  As apparent from the solid curve cb1 in FIG. 2, when the phase interpolation signal is generated only by the first current signal generation unit 2 and the mixer unit 5, the phase interpolation signal becomes nonlinear. When this solid line curve cb1 is observed in detail, the code data is between 0 and 10 (phase range of 0 to 45 degrees) is a downward convex curve, and the code data is between 10 and 20 (45 to 90 degrees). It can be seen that the (phase range) is an upwardly convex curve.

  The mixer unit 5 corrects the solid curve cb1 of FIG. 2 by dividing it into a downwardly convex curve region and an upwardly convex curve region, and as a result, the relationship between the code data of the phase interpolation signal and the phase is shown in FIG. The linearization process as shown by the solid line cb2 is performed.

  A broken line curve cb3 in FIG. 2 is a signal waveform of a phase interpolation signal generated by synthesizing a clock signal having a phase of 315 degrees and a clock signal having a phase of 45 degrees, and a one-dot chain curve cb4 in FIG. It is a signal waveform of a phase interpolation signal generated by synthesizing a clock signal and a clock signal having a phase of 135 degrees. Each of the curves cb3 and cb4 includes a downwardly convex curved area and an upwardly convex curved area.

  The convex curve region (code data 0 to 10) below the solid curve cb1 in FIG. 2 is symmetrical to the curve region (code data 10 to 20) convex above the broken curve cb3 in FIG. 2 and the solid line cb2. Similarly, the convex curve area (code data 10 to 20) above the solid curve cb1 is the same as the curve area (code data 0 to 10) convex below the one-dot chain curve cb4 and the solid line cb2. Is symmetrical with respect to

  Accordingly, the mixer unit 5 combines the convex curve region above the broken line curve cb3 with the convex curve region below the solid line curve cb1 (symbol data 0 to 10), and approximates it to the solid line cb2. In the curve area (code data 10 to 20) that is convex above the solid line curve cb1, it is combined with the curve area that is convex below the alternate long and short dash line curve cb4 and approximated to the solid line cb2. As a result, the relationship between the code data of the phase interpolation signal and the phase can be approximated to the solid line cb2 for all regions of the code data 0 to 20 corresponding to the phase range of phase 0 to 90 degrees.

  The current signals Ideg315 and Ideg45 corresponding to the dashed curve cb3 in FIG. 2 and the current signals Ideg45 and Ideg135 corresponding to the one-dot chain curve cb4 are generated by the second current signal generator 4 in FIG. The mixer unit 5 includes the current signals Ideg0 and Ideg90 corresponding to the solid line curve cb1 of FIG. 2 generated by the first current signal generation unit 2, the broken line curve cb3 of FIG. The phase interpolation signal is linearized using the current signals Ideg315, Ideg45, and Ideg135 corresponding to the curve cb4.

  FIG. 3 is a diagram illustrating a phase range of a clock signal used when the mixer unit 5 generates a phase interpolation signal having a phase of 0 to 90 degrees.

  As shown in FIG. 3, the phase interpolated signals within the phase range of 0 to 45 degrees are obtained by converting current signals Ideg0 and Ideg90 corresponding to clock signals CK0 and CK90 to current signals Ideg315 and Ideg45 corresponding to clock signals CK315 and CK45, respectively. The phase interpolation signal generated by combining and having a phase within the range of 45 to 90 degrees is obtained by converting current signals Ideg0 and Ideg90 corresponding to clock signals CK0 and CK90 to current signals Ideg45 and Ideg135 corresponding to clock signals CK45 and CK135. Generated by synthesis.

  As described above, in the present embodiment, the phase interpolation signal phase range of 0 to 90 degrees is divided into two areas of 45 degrees, and each area is combined with a separate current signal to generate code data. And the phase relationship is linear.

FIG. 4 is a diagram showing a conceptual operation of the phase interpolator 1 of FIG. 1 when the phase of the phase interpolation signal is in the range of 0 to 90 degrees. As shown in FIG. 4, the phase interpolator 1 performs processes S1 to S3. The process S1 is an original phase interpolation process, and the two types of coefficients X and Y of the clock signals sin θ and cos θ whose phases are different by 90 degrees are switched according to the value of the code data. Process S1 is represented by the following equation (1).
Xsin θ + Y cos θ (1)

This equation (1) can be transformed into the following equation (2).

Α in the above formula (2) is represented by the following formula (3).

  The coefficients X and Y in the above equations (1) to (3) are values that vary according to the value of the code data, and X + Y is always a constant value. The coefficient X corresponds to the current signal Ideg0 in FIG. 3, and the coefficient Y corresponds to the current signal Ideg90.

  The process S2 of FIG. 4 is a phase interpolation process performed using the clock signals CK315 and CK45 within a range of phase 0 to 45 degrees, and is expressed by the following equation (4).

Asin (θ−π / 4) + Bcos (θ−π / 4) (4)
The coefficients A and B in the above equation (4) are values that vary according to the value of the code data. The coefficient A corresponds to the current signal Ideg315 in FIG. 3, and the coefficient B corresponds to the current signal Ideg45.

  The process S3 of FIG. 4 is a phase interpolation process performed using the clock signals CK45 and CK135 within a phase range of 45 to 90 degrees, and is expressed by the following equation (5).

A′sin (θ + π / 4) + B′cos (θ + π / 4) (5)
The coefficients A ′ and B ′ in the above equation (5) are values that vary according to the value of the code data, the coefficient A ′ corresponds to the current signal Ideg45 of FIG. 3, and the coefficient B ′ corresponds to the current signal Ideg135. To do.

The phase interpolator 1 according to the present embodiment combines the signal of the expression (1) obtained in the process S1 and the signal of the expression (4) obtained in the process S2 within the range of 0 to 45 degrees. Generate a signal. This phase interpolation signal (first synthesized signal) is expressed by the following equation (6).

In the above formula (6), α is represented by formula (7), A is represented by formula (8), and B is represented by formula (9).

  In the above formulas (6) to (9), X + Y = A + B = constant value.

In addition, the phase interpolator 1 according to the present embodiment combines the signal of the expression (1) obtained in the process S1 and the signal of the expression (5) obtained in the process S3 within the range of 45 to 90 degrees. A phase interpolation signal is generated. This phase interpolation signal (second synthesized signal) is expressed by the following equation (10).

In the above formula (10), α is represented by formula (11), A ′ is represented by formula (12), and B ′ is represented by formula (13).

  In the above expressions (10) to (13), X + Y = A ′ + B ′ = constant value.

  2 to 4, the phase is described in the range of 0 to 90 degrees, but the same applies to the phase in the range of 90 to 180 degrees, in the range of 180 to 270 degrees, and in the range of 270 to 360 degrees. Each 90 degree angle range is divided into two areas of 45 degrees, and each area is combined with a separate current signal. That is, the mixer unit 5 uses the two current signals generated by the second current signal generation unit 4 for each angle range whose phase is 45 degrees, and the two current signals generated by the first current signal generation unit 2 and Synthesize.

  FIG. 5 is a diagram showing the types of clock signals used by the mixer unit 5 for synthesis in a total of eight regions obtained by dividing 0 to 360 degrees into 45 degrees. For the original phase interpolation, the mixer unit 5 uses the clock signals CK0 and CK90 at 0 to 45 degrees and 45 to 90 degrees, and uses the clock signals CK90 and CK180 at 90 to 135 degrees and 135 to 180 degrees, Clock signals CK180 and CK270 are used at 180 to 225 degrees and 225 to 270 degrees, and clock signals CK270 and CK0 are used at 270 to 315 degrees and 315 to 360 degrees. The mixer unit 5 uses clock signals CK315 and CK45 at 0 to 45 degrees and 315 to 360 degrees as clock signals used for synthesis for linearization, and clock signals at 45 to 90 degrees and 90 to 135 degrees. CK45 and CK135 are used, clock signals CK135 and CK225 are used at 135 to 180 degrees and 180 to 225 degrees, and clock signals CK225 and CK315 are used at 225 to 270 degrees and 270 to 315 degrees.

  FIG. 6 is a circuit diagram showing an example of a detailed configuration of the mixer unit 5 in the block diagram of FIG. In the mixer unit 5 of FIG. 6, the output signal of the first current signal generation unit 2 is equivalently represented by four current sources IS1 to IS4, and the output signal of the second current signal generation unit 4 is equivalent to four current sources. Expressed in IS5 to IS8.

  The mixer unit 5 in FIG. 6 includes two transistors Q1a, Q1b to Q8a, Q8b connected to each of the current sources IS1 to IS8, and a corresponding clock signal or its inverted signal is connected to the gates of these transistors. ing. More specifically, the clock signals CK270, CK180, CK90, CK0 or their inverted signals are input to the gates of the transistors Q1a, Q1b-Q4a, Q4b connected to the current sources IS1-IS4, respectively. Similarly, clock signals CK315, CK225, CK135, CK45 or their inverted signals are input to the gates of the transistors Q5a, Q5b-Q8a, Q8b connected to the current sources IS5-IS8, respectively.

  The differential output signals OUT0 and OUT180 of the mixer unit 5 in FIG. 6 are finally obtained phase interpolation signals. In the mixer unit 5 of FIG. 6, the current sources IS1 to IS4 and the transistors Q1a, Q1b to Q4a, Q4b connected thereto are used to generate the original phase interpolation signal. The current sources IS5 to IS8 and the transistors Q5a, Q5b to Q8a, Q8b connected thereto are used for linearizing the original phase interpolation signal.

  The currents flowing through the current sources IS1 to IS4 are switched for each 90 degree angle range of the phase interpolation signal from 0 to 90 degrees, 90 to 180 degrees, 180 to 270 degrees, and 270 to 360 degrees. Within each 90 degree angle range, current flows through only two of the current sources IS1 to IS4, and the value of the flowing current changes linearly according to the phase.

  FIG. 7A is a diagram showing waveforms of currents Ideg0, Ideg45, Ideg90, Ideg135, and Ideg315 flowing through the current sources IS4, IS8, IS3, IS7, and IS5 within a phase range of 0 to 90 degrees. The value of the code data, the vertical axis is the current value. The value of the code data is related to the phase amount. The larger the value of the code data, the larger the phase amount. The left end of the horizontal axis in FIG. 7 corresponds to the phase 0 degree, and the right end corresponds to the phase 90 degrees. .

  As shown in FIG. 7A, the current Ideg0 linearly decreases as the value of the code data increases. The current Ideg90 increases linearly as the value of the code data increases. The current Ideg45 increases linearly within the range of phase 0 to 45 degrees, and decreases linearly within the range of phase 45 to 90 degrees. The current Ideg 315 decreases linearly in the range of phase 0 to 45 degrees and is zero in the range of phase 45 to 90 degrees. The current Ideg135 is zero in the range of phase 0 to 45 degrees, and increases linearly in the range of phase 45 to 90 degrees.

  FIG. 7B is a diagram showing an operation simulation result of the mixer unit 5 in FIG. 6 within a phase range of 0 to 90 degrees, and shows a signal waveform of a phase interpolation signal output from the mixer unit 5. In FIG. 7B, the horizontal axis indicates the value of the code data, and the vertical axis indicates the phase amount.

  A solid line curve cb7 in FIG. 7B is a signal waveform of the final phase interpolation signal obtained by the operation simulation of the present embodiment, and a solid line curve cb5 is a signal interpolation when the second current signal generation unit 4 is not provided. A broken line curve cb6 is a signal waveform of a signal that is combined with the signal of the solid curve cb5 by the second current signal generation unit 2 and the mixer unit 5.

  Thus, the final phase interpolation signal cb7 can be made to have a substantially linear characteristic by synthesizing the signal of the solid curve cb5 and the signal of the broken curve cb6.

  FIG. 8 is a diagram in which signal waveforms of various phase interpolation signals having different phases within a phase range of 0 to 90 degrees are superimposed and displayed, with the horizontal axis representing time and the vertical axis representing voltage level. As shown in the figure, the maximum amplitude values of all the signal waveforms are almost the same, and the signal waveform does not drop near the maximum amplitude.

  On the other hand, FIG. 9 is a diagram illustrating a signal waveform of the phase interpolation signal output from the mixer unit 5 that does not perform the synthesis process by the first and second current signal generation units 2 and 4. In the case of FIG. 9, the maximum amplitude varies depending on the phase, and phase interpolation processing with high accuracy cannot be performed.

  As described above, in the present embodiment, the type of the current signal generated by the second current signal generation unit 4 is switched for each phase range of 45 degrees, and these current signals are generated by the first current signal generation unit 2. A phase interpolation signal is generated by combining with the current signal.

  FIG. 10 is a diagram showing the types of current signals generated by the first and second current signal generators 2 and 4 for each phase range of 45 degrees. The first and second current signal generators 2 and 4 generate current signals with white circles in FIG. 10 in the corresponding phase range. As shown in FIG. 10, in any phase range in units of 45 degrees, four current signals are used for the synthesis process, and a combination of current signals through which current flows is different for each phase range.

  FIG. 11 is a diagram showing changes in the signal waveform of the phase interpolation signal when the frequency is varied. FIG. 11 shows signal waveforms of phase interpolation signals of 4 GHz, 2 GHz, 1 GHz, 0.5 Hz, 0.2 Hz, and 0.1 Hz. FIG. 11 also shows signal waveforms of the solid curve cb5, the broken curve cb6 used for the linearization process, and the final phase interpolation signal cb7, as in FIG. 7B.

  As can be seen from FIG. 11, the lower the frequency, the worse the linearity of the phase-interpolated signal. However, even at low frequencies, the linearity is superior to the conventional one.

  Thus, in this embodiment, when generating a phase interpolation signal using a four-phase clock signal, a phase range of 45 degrees is used in addition to the original two types of current signals used to generate the phase interpolation signal. Since each current signal is synthesized by the mixer unit 5 using two different types of current signals every time, the nonlinearity of the phase interpolation signal can be corrected for each 45 degree phase range, and as a result, the linearity is excellent. A phase interpolation signal can be generated.

  In the above-described embodiment, when the phase interpolation signal is generated using the four-phase clock signal, the linearity of the phase interpolation signal is corrected by using a total of four types of current signals for each 45-degree phase range. As described above, the present embodiment can be widely applied to the case where a phase interpolation signal is generated using clock signals of three or more phases.

ここで、（１４）式のαは（１５）式で表され、Ｘ＋Ｙは一定値である。

FIG. 12 is a conceptual diagram of the phase interpolator 1 that generates a phase interpolation signal using a three-phase clock signal. The phases of the three-phase clock signal are phase 0, 120 degrees, and 240 degrees. Of these three clock signals, the original phase interpolation processing is performed by switching the coefficients X and Y of the two types of clock signals sin θ and sin (θ + 2π / 3) whose phases are different by 120 degrees in accordance with the value of the code data. Is done. The formula in this case is expressed by the following formula (14).

Here, α in the equation (14) is expressed by the equation (15), and X + Y is a constant value.

  In order to linearize the phase interpolation signal generated by the three-phase clock signal, a method similar to the above-described equations (6) to (13) is used by using three clock signals having phases of 60 degrees, 180 degrees, and 300 degrees. Thus, the synthesis process may be performed by switching the clock signal every 60 degrees.

  As a result, as shown in FIG. 13, the linearity of the phase interpolation signal can be improved as compared with the case where the linearization process is not performed.

  The present embodiment is applicable to the phase interpolator 1 that generates a phase interpolation signal using an N-phase clock signal having three or more phases.

ここで、（１６）式のαは（１７）式で表され、Ｘ＋Ｙは一定値である。

FIG. 14 is a conceptual diagram of the phase interpolator 1 that generates a phase interpolation signal using an N-phase (N is an integer of 3 or more) clock signal. The phase of the N-phase clock signal is shifted by 2π / N. Of these N-phase clock signals, the two phases of the clock signals sin θ and θ (θ + 2π / N) having different phases by 2π / N are switched according to the value of the code data to switch the original phase. Interpolation processing is performed. The formula in this case is expressed by formula (16).

Here, α in the equation (16) is expressed by the equation (17), and X + Y is a constant value.

  FIG. 15 is a conceptual diagram when the phase interpolation signal is linearized within the range of 0 to 2π / N using the phase interpolator 1 of FIG. 14. As shown in FIG. 15, the phase interpolator 1 performs processes S11 to S13. The process S11 is an original phase interpolation process shown by the above-described equation (16).

  The process S12 is a phase interpolation process performed using the clock signals sin (θ−π / N) and sin (θ + π / N) within the range of phase 0 to π / N, and is expressed by the following equation (18). Is done.

Asin (θ−π / N) + Bsin (θ + π / N) (18)
The coefficients A and B in the equation (18) are values that vary according to the value of the code data, and are expressed by the following equation (19).

A = X [code (+ π / N)], B = Y [code (+ π / N)] (19)
The process S13 is a phase interpolation process performed using the clock signals sin (θ + π / N) and sin (θ + 3π / N) within the range of phase π / N to 2π / N, and is expressed by the following equation (20). Is done.

A′sin (θ−π / N) + B′sin (θ + π / N) (20)
The coefficients A and B in the above equation (20) are values that vary according to the value of the code data, and are expressed by the following equation (21).

ここで、（２２）式のαは（２３）式で表され、係数Ａ，Ｂは上述した（１９）式で表される。

A ′ = X [code (−π / N)], B ′ = Y [code (−π / N)] (21)
The phase interpolator 1 in FIG. 15 generates a linearized phase interpolation signal by combining the above-described equations (16) and (18) within the range of phase 0 to π / N. This phase interpolation signal is expressed by the following equation (22).

Here, α in equation (22) is expressed by equation (23), and coefficients A and B are expressed by equation (19) described above.

ここで、（２４）式のαは（２５）式で表され、係数Ａ’，Ｂ’は上述した（２１）式で表される。

Further, the phase interpolator 1 in FIG. 15 generates a linearized phase interpolation signal by combining the above-described equations (16) and (19) within the range of phase π / N to 2π / N. To do. This phase interpolation signal is expressed by the following equation (24).

Here, α in equation (24) is expressed by equation (25), and coefficients A ′ and B ′ are expressed by equation (21) described above.

  At least a part of the phase interpolator described in the above-described embodiment may be configured by hardware or software. When configured by software, a program for realizing at least a part of the functions of the phase interpolator may be stored in a recording medium such as a flexible disk or a CD-ROM, and read and executed by a computer. The recording medium is not limited to a removable medium such as a magnetic disk or an optical disk, but may be a fixed recording medium such as a hard disk device or a memory.

  Further, a program for realizing at least a part of the functions of the phase interpolator may be distributed via a communication line (including wireless communication) such as the Internet. Further, the program may be distributed in a state where the program is encrypted, modulated or compressed, and stored in a recording medium via a wired line such as the Internet or a wireless line.

  Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention. Accordingly, aspects of the present invention are not limited to the individual embodiments described above. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

  1 phase interpolator, 2 first current signal generation unit, 3 code data adjustment unit, 4 second current signal generation unit, 5 mixer unit

Claims (6)

A first current signal generator for generating a plurality of first current signals according to the value of code data consisting of a plurality of bits;
A code data adjustment unit that increases or decreases the value of the code data by a predetermined value in accordance with the value of the code data;
A second current signal generation unit that generates a plurality of second current signals according to the value of the code data after increase / decrease in the code data adjustment unit;
A first synthesized signal obtained by synthesizing clock signals obtained by adjusting the amplitudes of the plurality of first clock signals having different phases based on the corresponding first current signals, and the plurality of first clock signals have different phases. A mixer that generates a phase interpolation signal by synthesizing a second synthesized signal obtained by synthesizing clock signals in which amplitudes of the plurality of second clock signals are adjusted based on the corresponding second current signals; Prepared,
The mixer unit is configured to switch phases of the plurality of second clock signals used for generating the second synthesized signal for each predetermined phase range of the phase interpolation signal.
The mixer unit switches a phase of the plurality of first clock signals used for generating the first synthesized signal for each first phase range of the phase interpolation signal, and moreover than the first phase range. For each narrow second phase range, switch the phases of the plurality of second clock signals used to generate the second composite signal;
The first current signal generation unit determines and selects a current value of the first current signal selected from the plurality of first current signals for each of the first phase ranges according to the value of the code data. The current value of the first current signal that was not
The second current signal generation unit determines a current value of a second current signal selected from the plurality of second current signals for each of the second phase ranges according to the value of the code data, and selects the second current signal. The current value of the second current signal that was not
The first phase range is an integer multiple of the second phase range;
The mixer unit performs a process of switching the second current signal for each second phase range and linearizing the relationship between the value of the code data and the phase of the phase interpolation signal,
The first current signal generator generates four types of the first current signals,
The second current signal generator generates four types of the second current signals,
The mixer unit includes a first synthesized signal obtained by synthesizing clock signals adjusted based on the first current signals corresponding to the two types of the first clock signals having different phases for each phase range of 45 degrees; The phase interpolated signal is generated by synthesizing the second synthesized signal obtained by synthesizing the clock signals adjusted based on the second current signals corresponding to the two types of the second clock signals having different phases. A phase interpolator characterized by that. A first current signal generator for generating a plurality of first current signals according to the value of code data consisting of a plurality of bits;
A code data adjustment unit that increases or decreases the value of the code data by a predetermined value in accordance with the value of the code data;
A second current signal generation unit that generates a plurality of second current signals according to the value of the code data after increase / decrease in the code data adjustment unit;
A first synthesized signal obtained by synthesizing clock signals obtained by adjusting amplitudes of a plurality of first clock signals having different phases based on the corresponding first current signals, and a plurality of first clock signals having different phases, respectively. A mixer unit that generates a phase interpolation signal by synthesizing a second synthesized signal obtained by synthesizing clock signals adjusted based on the second current signals corresponding to the amplitudes of a plurality of second clock signals having different phases. And a phase interpolator comprising:   The said mixer part switches the phase of these several 2nd clock signals used for producing | generating a said 2nd synthetic | combination signal for every predetermined phase range of the said phase interpolation signal. Phase interpolator. The mixer unit switches a phase of the plurality of first clock signals used for generating the first synthesized signal for each first phase range of the phase interpolation signal, and moreover than the first phase range. For each narrow second phase range, switch the phases of the plurality of second clock signals used to generate the second composite signal;
The first current signal generation unit determines and selects a current value of the first current signal selected from the plurality of first current signals for each of the first phase ranges according to the value of the code data. The current value of the first current signal that was not
The second current signal generation unit determines a current value of a second current signal selected from the plurality of second current signals for each of the second phase ranges according to the value of the code data, and selects the second current signal. 4. The phase interpolator according to claim 2, wherein the current value of the second current signal that has not been set is set to zero. The first phase range is an integer multiple of the second phase range;
The mixer unit performs a process of switching the second current signal for each second phase range and linearizing a relationship between a value of the code data and a phase of the phase interpolation signal. The phase interpolator according to claim 4. Generating a plurality of first current signals according to the value of code data consisting of a plurality of bits;
Increasing or decreasing the value of the code data by a predetermined value according to the value of the code data;
Generating a plurality of second current signals according to the value of the code data after increase / decrease in the code data adjustment unit;
A first synthesized signal obtained by synthesizing clock signals obtained by adjusting the amplitudes of the plurality of first clock signals having different phases based on the corresponding first current signals, and the plurality of first clock signals have different phases. Synthesizing a second synthesized signal obtained by synthesizing clock signals obtained by adjusting the amplitudes of the plurality of second clock signals based on the corresponding second current signals, and generating a phase interpolation signal. A phase interpolation method characterized by the above.

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