CN1164127A - Lead frame and semiconductor device using the lead frame and method of manufacturing the same - Google Patents

Lead frame and semiconductor device using the lead frame and method of manufacturing the same Download PDF

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Publication number
CN1164127A
CN1164127A CN97103312A CN97103312A CN1164127A CN 1164127 A CN1164127 A CN 1164127A CN 97103312 A CN97103312 A CN 97103312A CN 97103312 A CN97103312 A CN 97103312A CN 1164127 A CN1164127 A CN 1164127A
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China
Prior art keywords
lead
semiconductor chip
supporter
spacing
fixed
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Granted
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CN97103312A
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Chinese (zh)
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CN1156910C (en
Inventor
田中茂树
藤泽敦
长野宗一
平野次彦
太田亮一
今野贵史
建部坚一
冈本敏昭
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Hitachi Renesas Semiconductor Inc
Hitachi Ltd
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Hitachi Renesas Semiconductor Inc
Hitachi Ltd
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Publication of CN1164127A publication Critical patent/CN1164127A/en
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Publication of CN1156910C publication Critical patent/CN1156910C/en
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Abstract

There is provided a semiconductor chip mounting area for mounting a semiconductor chip, and the points of the inner leads are made to come closer to the semiconductor chip mounting area by arranging the points of the inner leads at equal intervals over the whole periphery of the semiconductor chip mounting area. The points of the inner leads are arranged along the whole periphery of the semiconductor chip mounting area, and the lead pitch at the points of the inner leads corresponding to a corner portion of the semiconductor chip mounting area is made wider than the lead pitch of the other inner lead points.

Description

Lead frame, the semiconductor device that uses this lead frame and manufacture method thereof
The present invention relates to lead frame and semiconductor device, more particularly, relate to the technology of the lead frame that can effectively be applied to comprise a plurality of lead-in wires and use the semiconductor device of this lead frame.
Along with the improvement of integrated level, more complicated circuit has been installed in the semiconductor device such as LSI (large scale integrated circuit), its function also greatly improves.Owing to reach high like this function, semiconductor device becomes needs more outside terminal, like this, and the pressure welding area electrode that on semiconductor chip, is provided with and itself be that the number of lead-in wire of the outside terminal of semiconductor device also correspondingly increases.For example, in the logical type semiconductor device, the number of outside terminal even reach hundreds of.As a kind of like this multilead semiconductor device, known have quad flat package (QFP) N-type semiconductor N device.Since in the QFP N-type semiconductor N device respectively four sides to the seal of sealing semiconductor chips be provided with a plurality of lead-in wires, so this device is suitable for forming multilead, and have following advantage, promptly when semiconductor device encapsulates, can effectively utilize semiconductor device spacing on every side on base plate for packaging.
The the 155th to 164 page of " VLSL encapsulation technology (VLSI Packaging Technique) (first volume) " that the lead frame that is used for assembling this QFP N-type semiconductor N device has been published on May 31st, 1993 provides, particularly shows in the 157th to 159 page and understand concrete figure.
In addition, because above-mentioned improvement increases the component number that forms on the semiconductor chip, these elements are to work under higher speed simultaneously, so the heat that produces from semiconductor chip also increases.As making the improved semiconductor device of heat dispersion, for example in " VLSL encapsulation technology (concluding volume) " the 200th to 203 page, a kind of semiconductor device that has radiator has been described in order to address the above problem.In this semiconductor device, its heat dispersion is improved by radiator is installed on semiconductor chip.
In order to solve the problem of above-mentioned multilead in forming, need in lead frame, reduce lead spacing, promptly the interval in the lead-in wire reduces the width dimensions that goes between simultaneously.
In addition, be similar to top describedly, owing to will realize described high function, on semiconductor chip, be provided with a plurality of pressure welding area electrodes, and with the pressure welding area spacing, promptly the interval in the pressure welding area electrode form also forr a short time.In general, there is the multiple electrode spacing of semiconductor chip pressure welding area, but wishes that chip size is little, so that be increased in available core number on each wafer, therefore just demonstrate a kind of like this trend, promptly also be provided with the spacing in each pressure welding area electrode littler.
There is such problem: when using welding wire such as gold,, contact with each other the short circuit that causes with regard to the welding wire that is easy to produce because of contiguous owing to become less at interval with a plurality of lead-in wires and the mutual bonding of each pressure welding area electrode.Particularly because at the place, bight of semiconductor chip, along the tilted direction with respect to semiconductor chip, the welding wire that is bonded to the pressure welding area electrode elongates, so even when the pressure welding area spacing is identical, the interval between welding wire also diminishes, therefore aforementioned trend shows more obviously.
Have such problem in addition: carrying out behind the welding wire bonding under the resin moulded situation, produce sometimes because of the mechanical strength of each welding wire and descend because moulding resin mobile makes the welding wire distortion cause welding wire and move, or welding wire minimizing at interval, and the short circuit that produces welding wire because of this distortion.
Have again, can become narrow more when the configuring area that in QFP, goes between, the approaching more semiconductor chip that is installed in the center.Consequently, when lead spacing because the restriction of machining accuracy of lead-in wire can not attenuate fully with respect to the pressure welding area spacing of semiconductor chip the time, just can not make the end of lead-in wire approach semiconductor chip.Thereby, be used to make the welding wire of pressure welding area electrode and the mutual bonding of lead-in wire to have to extend.When welding wire extended by this way, the possibility that above-mentioned short circuit or welding wire move generation became bigger.
Also because this attenuating of lead-in wire reduced the mechanical strength of each lead-in wire, making lead-in wire become Yi Yinxiao power and be deformed, and also produce short circuit because of this distortion.
An object of the present invention is to provide a kind of technology that can in having the semiconductor device of multilead, prevent short circuit or go between and move and make bonding become stable.
Another object of the present invention provides a kind of technology that can improve heat dissipation characteristics in having the semiconductor device of multilead.
By the description and the accompanying drawing of this specification, above-mentioned research object and the feature with other of the present invention will become apparent.
In the invention disclosed, representational summary of the invention will be summarized as follows in the application's book.
In semiconductor chip being installed on the supporter and lead being fixed to semiconductor device on this supporter by insulator, the end of lead is fixed to the whole periphery of semiconductor chip installing zone with the whole lip-deep adhesion layer that is arranged on above-mentioned supporter.
For the lead spacing of each lead end, maximum lead spacing is arranged to less than minimum lead spacing one times.
Make corresponding to the lead spacing ratio of place, semiconductor chip bight lead end wide in the lead spacing at other lead terminal places.
In lead, the illusory lead-in wire of not drawing outside the seal is set corresponding to the bight of semiconductor chip.
Make the pressure welding area spacing of other pressure welding area electrodes of pressure welding area gap ratio that are positioned at place, semiconductor bight pressure welding area electrode wide.
According to above-mentioned way,, can make the lead end more approach the semiconductor chip installing zone by the lead end being fixed to the whole periphery of semiconductor chip installing zone.Thereby, can reduce short circuit that contiguous welding wire contacts with each other or be deformed the welding wire that produces and move because of moulding resin mobile causes welding wire.
Have again, owing to can make lead spacing corresponding to semiconductor chip bight place lead end, so can reduce contiguous welding wire because of contacting with each other short circuit or being deformed the welding wire that produces and moving owing to moulding resin mobile causes welding wire than wide in the lead spacing at other lead terminal places.
Again owing to make and in resin flow, be difficult to produce turbulent flow by dummy electrode is set, can reduce because of the cavity cause resin inject insufficient.
Also because do not hang the lead-in wire of fin, so can easily intersect bonding.
In addition, fix lead, can make the manufacture process of the lead frame that has supporter simplify and reduce production cost by on the whole surface of supporter, forming adhesion layer in advance.
Further, by semiconductor chip is installed on supporter, the heat that produces in semiconductor chip just can be dispersed into the outside by supporter, can improve the heat dissipation characteristics of semiconductor chip like this.
Fig. 1 is the plane graph that shows the lead frame of bright one embodiment of the invention;
Fig. 2 is the longitudinal section of lead frame shown in Fig. 1;
Fig. 3 is the longitdinal cross-section diagram that shows the lead frame manufacture method of bright one embodiment of the invention;
Fig. 4 is the longitudinal section that shows the semiconductor device of bright one embodiment of the invention;
Fig. 5 is the plane graph that shows used semiconductor chip in the semiconductor device of bright an alternative embodiment of the invention;
Fig. 6 is the plane graph of Fig. 5 of showing that bright part has been amplified;
Fig. 7 is the plane graph that shows used lead frame in the QFP N-type semiconductor N device of bright another embodiment of the present invention partly;
Fig. 8 is the sectional view that shows the lead frame of bright another embodiment of the present invention;
Fig. 9 is the longitudinal section that shows the semiconductor device of the manufacturing of lead frame shown in bright use Fig. 8;
Figure 10 is the sectional view that shows the lead frame of bright another embodiment of the present invention;
Figure 11 is the longitudinal section that shows the semiconductor device of the manufacturing of lead frame shown in bright use Figure 10;
Figure 12 is the sectional view that shows the lead frame of bright another embodiment of the present invention;
Figure 13 is the longitudinal section that shows the semiconductor device of the manufacturing of lead frame shown in bright use Figure 12;
Figure 14 is the plane graph that shows the supporter 8 of the bright lead frame that is used for another embodiment of the present invention;
Figure 15 shows the plane graph that the state of semiconductor chip 10 is installed on the supporter 8 shown in bright Figure 14;
Figure 16 is the plane graph that shows the semiconductor device of bright another embodiment of the present invention partly;
Figure 17 is the plane graph that shows the semiconductor device of bright further embodiment of this invention partly;
Figure 18 is the plane graph of the semiconductor device that shows that partly the bright inventor studied in prior to the stage of the present invention;
And
Figure 19 is the plane graph that shows semiconductor device in bright another embodiment of the present invention partly.
Below embodiment of the present invention will be described.In addition, in the accompanying drawing of be useful on explanation embodiment, give parts with identical label, and omit the description of its repetition with identical function.
Embodiment 1
Fig. 1 is the plane graph of used lead frame in the QFP N-type semiconductor N device of one embodiment of the present of invention, and Fig. 2 is the longitudinal section of lead frame shown in Fig. 1.Lead frame 1 is by for example Fe-Ni alloy composition, disposes the end of the lead 4 of a plurality of lead-in wires 3 on the whole periphery of semiconductor chip (being shown in broken lines) installing zone 2 of the semiconductor chip of center.In addition, lead frame 1 can be by the Cu alloy composition.
Each lead-in wire 3 usefulness become the closed bar 6 of lead frame framework or connecting rod 19 form as a whole, the inside and outside lead 4 and the outer lead 5 of being used separately as of each closed bar 6 of 3 of going between.
This lead-in wire configuration forms by well-known lithographic technique or stamping technology etc., in common QFP N-type semiconductor N device, disposes tens to hundreds of bar lead-in wire 3, has disposed 104 lead-in wires 3 in the present embodiment.The end of each lead-in wire lead 4 of 3 is fixed on the surface of supporter 8 by the insulation adhesive linkage 7 that forms on the whole surface of supporter.
In lead frame 1 of the present invention, semiconductor chip is fixed on the semiconductor chip installing zone 2 of supporter 8, lead 4 is fixed in this supporter 8.Therefore, just be not provided for supporting the suspension fin lead-in wire of the fin (die base) that semiconductor chip is installed, but the zone that has been configured to fin suspension lead-in wire then is used for disposing lead 4.
Consequently, also dispose lead 4 being used to be provided with the place, bight that fin hangs lead-in wire so far, and with respect to lead spacing, promptly at the interval of the end of each lead, maximum lead spacing is less than along a times of the minimum lead spacing of the whole periphery that comprises the bight, and the leeway that does not dispose other lead-in wires in each lead 4.In brief, the lead frame of present embodiment is such formation, and the relation in maximum lead-in wire interval (L), minimum lead interval (W1) and the prior minimum lead width of being determined by the machining accuracy or the design load of lead frame (W2) that allow in the terminal place of adjacent lead satisfies following formula 1.
(L)＜2 * (W1)+(W2) ... (formula 1)
So, in the present embodiment, even,, also can make the end of lead 4 more approach semiconductor chip installing zone 2 with identical lead spacing configuration lead for by being provided with on the whole periphery of semiconductor chip installing zone of position that fin hangs lead-in wire comprising with same intervals.Therefore, can shorten welding wire length when after semiconductor chip is being installed, carrying out the welding wire bonding, so just can when resin-sealed, reduce welding wire and move and reduce short circuit in the welding wire.
Here, the material that has high heat conductance by for example Cu or Al material etc. is used as supporter 8, can improve the thermal diffusivity of semiconductor device.
In addition, owing to be fixed to the mechanical strength of having improved each lead-in wire 3 on the supporter 8, so even doing the lead spacing of lead 4 very little, also be difficult to take place the distortion of the lead that causes because of external force by lead 4 with a plurality of lead-in wires 3.As a result, can prevent to produce short circuit in the bonding welding wire.
Moreover though the existing in the prior art no fin device that adopts radiator, this radiator only is used as the heat radiation object so far.According to the present invention, this device is used to solve the lead spacing problem reliably, so that improve the stability of bonding.
With reference to Fig. 2, Fig. 3 and Fig. 4, the method that the semiconductor device of this lead frame is used in lead frame shown in Fig. 1 and Fig. 2 and manufacturing is described below.
At first, shown in Fig. 3 (a), by coating on the whole surface that has been stained with in advance lead 4 of supporter 8 is formed adhesive linkage 7.As adhesive linkage, for example can use thermosetting resin, as epoxy resin and phenolic resin; Or the use thermoplastic resin, as polyvinyl resin and vinyl chloride resin.Supporter 8 can apply adhesive linkage 7 but can or be coated with afterwards in this first being processed by sheet metal etc. is carried out die-cut obtaining.Adhesive linkage is coated to above-mentioned whole lip-deep during, can make the manufacturing cost that mask etc. and minimizing have the lead frame of supporter 8 during adhesive linkage in coating.Have, adhesive linkage 7 also can be membranaceous polyimide resin again.In this case, after membranaceous polyimides being adhered on the parent metal plate that becomes supporter 8, only need just can by Punching Technology.
Secondly, shown in Fig. 3 (b), each lead 4 that forms configuration in the lead frame 1 is adhered on the supporter 8 that has adhesive linkage 7.This state is shown in Figure 2.Under the situation of present embodiment, before bonding, adhesive linkage 7 is solidified with about 300 ℃ heat treatment.
Shown in Fig. 3 (c), semiconductor chip 10 is adhered on the semiconductor chip installing zone 2 then with silver-colored paste 12.Adopted so far adhesive linkage 7 to be coated on the lead 4 and lead 4 is adhered to method on the supporter 8, but existed in the method because lead distortion and produce the problem of waste product when the coating adhesive linkage.But in the present invention, bonding by making lead 4 in advance with the adhesive linkage 7 that is coated on the supporter 8, can address the above problem.
By bonding welding wires 13 such as gold pressure welding area electrode 11 and lead 4 with semiconductor chip 10 be connected to each other thereafter.Because lead 4 is fixed in supporter 8, so can fix lead 4 by means of the pull of vacuum at the back of supporter 8 in the present embodiment and carry out the welding wire bonding, therefore there is no need as conventional lead frame, use window formula clamper to fix lead with pressuring method.
After the welding wire bonding is finished, by means of the seal of forming by for example epoxy resin 14 semiconductor chip 10, supporter 8, bonding welding wire 13 and lead 4 are sealed, and closed bar 6 and connecting rod 19 are cut, thus each lead-in wire electricity is separated.Afterwards, in Fig. 4, will form gull wing shape, so just finish semiconductor device 9 from the outer lead 5 that seal 14 extends as an example.
Embodiment 2
Below with reference to Fig. 5 and Fig. 6 semiconductor device as another embodiment of the present invention is described.Fig. 5 is the plane graph of configuration that is used to illustrate the pressure welding area electrode 11 of semiconductor chip 10; Fig. 6 is the local amplification view that is used to illustrate place, semiconductor chip 10 bights bonding state.
In semiconductor device of the present invention, semiconductor chip 10 is fixed on the semiconductor chip installing zone of supporter 8, lead 4 is fixed on this supporter 8.Therefore, just be not provided for supporting the suspension fin lead-in wire of the fin (die base) that semiconductor chip is installed, then be used for disposing lead 4 but be used to be provided with the zone that fin hangs lead-in wire.
The result, also dispose lead 4 being used to be provided with the place, bight that fin hangs lead-in wire so far, and, with respect to demonstrating lead spacing at interval in the end of each lead along the whole periphery that comprises the bight, lead is configured with much at one spacing on whole periphery, even and under the situation of identical lead spacing, also can make the end of lead 4 more approach semiconductor chip 10.Have, the lead spacing P in the end of each lead 4 is set to about 180 microns to 220 microns again.
Be set to a plurality of pressure welding area electrodes 11 of the outside terminal of semiconductor chip 10 along the marginal portion of semiconductor chip 10, but in the present embodiment, the pressure welding area spacing broadens more near the bight of semiconductor chip the time more.
In the embodiment shown in Fig. 6, when the pressure welding area spacing of supposing semiconductor chip 10 pressure welding area electrodes 11 inner rim part centers is P1, be that the mode with P2=1.1P1, P3=1.2P1 and P4=1.3P1 makes the pressure welding area spacing respectively widen 0.1P1 in moving closer to the process in bight.Have, at the semiconductor chip 10 of the semiconductor device that is used for high integration, the spacing of pressure welding area electrode 11 then is set to 80 microns to 100 microns again.
Carried out connecting the bonding of pressure welding area electrode 11, but in the configuration in pressure welding area electrode 11,, just more the pressure welding area spacing has been broadened the closer to the bight to the end of lead 4 with welding wire 13.Therefore, even wait to produce distortion because of welding wire moves when welding wire 13, can prevent that also welding wire 13 in the bight from contacting with the welding wire 13 that is close to and produce short circuit.Having, is that diameter is about 25 microns to 35 microns golden filament etc. as bonding welding wire 13 again.
In addition, in semiconductor chip 10, make the pressure welding area electrode 11 at place, peripheral part outer end and the pressure welding area electrode of locating in another outer end of peripheral part 11, promptly be adjacent to pressure welding area electrode 11 and the bight of semiconductor chip is placed therebetween pressure welding area electrode, between pressure welding area spacing P5 wideer than other pressure welding area spacings, and make it than wide at this lead spacing P6 around towing point part of welding wire 13.
Have again, owing under the welding wire bonding situation of present embodiment, be that lead 4 is fixed on the supporter 8, so can be from the back of supporter 8 carry out welding wire bonding with lead 4 by means of pull of vacuum.Therefore, there is no need as conventional lead frame, use window formula clamper to fix lead with pressuring method.
After the welding wire bonding is finished, by means of the seal of forming by for example epoxy resin 14 semiconductor chip 10, supporter 8, bonding welding wire 13 and lead 4 are sealed, and closed bar 6 and connecting rod 19 are cut, thus each lead-in wire electricity is separated., as an example, among Fig. 4 will from outer lead 5 that seal 14 extend form gull wing shape, so just finish semiconductor device 9 thereafter.
In this embodiment of semiconductor device, can reduce approximately half substandard products that produce owing to welding wire moves with comparing in the past.
Have again,,, also can implement the present invention by the method for expanding the bight partly except expanding equably the method for pressure welding area spacing from the center of above-mentioned peripheral part as for the above-mentioned pressure welding area spacing of expansion.
Embodiment 3
Secondly, with reference to Fig. 7 and Figure 16 semiconductor device as another embodiment of the present invention is described.
Fig. 7 is the plane graph that shows the lead frame of the bright QFP N-type semiconductor N device that is used for another embodiment of the present invention partly, and Figure 16 is the plane graph that shows bright semiconductor device partly.
Lead frame 1 is for example by Fe-Ni alloy or Cu alloy composition, and the end of the lead 4 of a plurality of lead-in wires 3 is configured on the whole periphery of semiconductor chip (being shown in broken lines) installing zone 2 of center.
The lead 4 usefulness insulating binders of each lead-in wire 3 are fixed on the surface of supporter 8.As adhesive, for example can use thermosetting resin, as epoxy resin and phenolic resin, or use thermoplastic resin, as polyvinyl resin and vinyl chloride resin.
In semiconductor device of the present invention, semiconductor chip 10 is fixed on the semiconductor chip installing zone of supporter 8, lead 4 is fixed in this supporter 8.Therefore, just be not provided for supporting the suspension fin lead-in wire of the fin (die base) that semiconductor chip is installed, then be used for disposing lead 4 but be used for being provided with the zone that fin hangs lead-in wire.
Like this, in the present embodiment, can be along the end of the whole circumferential arrangement lead 4 of semiconductor chip installing zone 2, and make corresponding to the lead spacing of the end of the lead 4 in the bight of semiconductor chip installing zone 2 than wide in the lead spacing at other lead 4 places.Like this, when carrying out the welding wire bonding after semiconductor chip is being installed, the interval of welding wire 13 between mutually broadens the short circuit minimizing in the welding wire 13.
Here, by using the material that has high heat conductance as Cu or Al material etc., can improve the thermal diffusivity of semiconductor device.
In addition, owing to be fixed to the mechanical strength that supporter 8 has improved each lead-in wire 3 by the lead 4 with a plurality of lead-in wires 3, even when doing the lead spacing of lead 4 very little, the lead that also is difficult to take place to cause because of external force is out of shape.Therefore can prevent to produce the short circuit in the bonding welding wire 13.
Marginal portion along semiconductor chip 10 is provided with a plurality of pressure welding area electrodes 11, but in the present embodiment, and the pressure welding area spacing broadens more near the bight of semiconductor chip the time more.Have, at the semiconductor chip 10 of the semiconductor device that is used for high integration, the spacing of pressure welding area electrode 11 is set to 80 microns to 100 microns again.
Carried out being connected to each other the bonding of pressure welding area electrode 11 to the end of lead 4 with welding wire 13, even but when welding wire 13 is out of shape because of generations such as welding wire move, because in pressure welding area electrode 11, be provided with widely more the closer to bight pressure welding area spacing, so also can prevent to contact with contiguous welding wire 13 and produce short circuit at the welding wire 13 in bight.Having, is that diameter is about 25 microns to 35 microns golden filament etc. as bonding welding wire 13 again.
In addition, in semiconductor chip 10, make other pressure welding area spacing of pressure welding area gap ratio between the pressure welding area electrode 11 at outer end, marginal portion place and pressure welding area electrode 11 wide at another place, outer end of marginal portion, so that versatility is provided to a certain extent, and make it also wideer than lead spacing sometimes.In this case, also can enlarge the pressure welding area spacing by making above-mentioned pressure welding area electrode 11 more close bights in the outer end.
Also have, owing under the welding wire bonding situation of present embodiment, be that lead 4 is fixed on the supporter 8, so can be from the back of supporter 8 carry out welding wire bonding with lead 4 by means of pull of vacuum.Therefore, there is no need as conventional lead frame, use window formula clamper to fix lead with pressuring method.
After the welding wire bonding is finished, by means of the seal of forming by for example epoxy resin 14 semiconductor chip 10, supporter 8, bonding welding wire 13 and lead 4 are sealed, and closed bar 6 and connecting rod 19 are cut, thus each lead-in wire electricity is separated and formed from the outer lead 5 of seal 14 extensions, so just finished semiconductor device 9.
In this semiconductor device of present embodiment, and compare in the past, can reduce half substandard products that produce owing to welding wire moves approximately.
Have, the method as the above-mentioned pressure welding area spacing of expansion except expanding equably the method for pressure welding area spacing from the center of above-mentioned marginal portion, also can wait by the method for expanding the bight partly and implement the present invention again.
Embodiment 4
Secondly the lead frame of another embodiment of the present invention is described with reference to Figure 17.Figure 17 is the local amplification view that is used to illustrate lead frame.
In the lead frame 1 of present embodiment, semiconductor chip (being shown in broken lines) is fixed on the semiconductor chip installing zone 2 of supporter 8, lead 4 is fixed in this supporter 8.As a result, can not be provided for supporting the suspension fin lead-in wire of the fin (die base) that semiconductor chip 10 is installed, then be used for disposing lead 4 but be used to be provided with the zone that fin hangs lead-in wire.
As in the configuration of this lead 4 when the bight place configuration outer lead 5, be the bight that outer lead is configured to leave a little seal 14, so that the safety of protection outer lead 5 or protection resin injection channel.Thereby, can produce an interval that does not dispose lead at the place, bight of seal 14 by chance sometimes.
When a kind of like this interval produces, when injecting, resin will produce turbulent flow in the resin flow that is injected into this part.Therefore, produce cavity and that resin is injected is insufficient sometimes.
In order to address this is that, according to present embodiment, an illusory lead-in wire 20 is set in that the place, bight that hangs the fin lead-in wire is set so far, this illusory lead-in wire is an illusory lead that is not drawn out to after lead frame cuts outside the seal.The width of this illusory lead-in wire 20 is wideer than the width of other leads 4, and its end is arranged on outside the end of lead 4, and the end of lead 4 is configured on the whole periphery of semiconductor chip installing zone 2.
In the present embodiment, can prevent from resin flow, to produce turbulent flow by this illusory lead-in wire 20.Therefore, in the semiconductor device of present embodiment, can reduce because of the cavity causes resin and inject the generation of inadequate goods.
In addition, by four bights, can support this supporting bracket 8 more firmly with illusory lead-in wire 20 fixed support plates 8.
Have again, under the state of lead frame, in technology, transport in the process of lead frame, can before cutting lead frame, assign to transport, can prevent the distortion of outer lead 5 by clamping and transport outer lead 5 by the seal lead division of clamping illusory lead-in wire 20.
Embodiment 5
Secondly with reference to Figure 18 and Figure 19 semiconductor device as another embodiment of the present invention is described.Figure 18 is a local amplification view of describing the semiconductor device that the inventor studied in prior to the stage of the present invention, and Figure 19 is the local amplification view that is used to describe semiconductor device of the present invention.
In the semiconductor device shown in Figure 18, lead is connected to each other with the pressure welding area electrode that is provided with on the side of the semiconductor chip relative with these leads.
But, when being necessary with the identical semiconductor chip of dissimilar seal sealing, sometimes need to intersect bonding, be about to be connected to, along the pressure welding area electrode of the semiconductor chip that is provided with on the another side of a side that is adjacent to the semiconductor chip relative with those leads corresponding to the end of the lead in the bight of semiconductor chip.
In this case, routine as shown in Figure 8, semiconductor chip 10 be fixed to fin 21 and support in the semiconductor device of these fins 21 by the lead-in wire 22 that hangs fin, bonding welding wire 13 intersects with the lead-in wire 22 of suspension fin.Therefore, owing to contact the unfavorable condition that causes between bonding welding wire 13 and the lead-in wire 22 that hangs fin, in this bonding, just made various restriction, so just made bonding become difficult in order to prevent to produce.
In the semiconductor device of present embodiment, semiconductor chip 10 is fixed on the supporter 8, and this support 8 is fixed on the lead 4.Therefore, be not provided for installing the fin 21 (die base) of semiconductor chip 10 and be used to support the suspension fin lead-in wire 22 of this fin, then be used for disposing lead 4 but be provided the zone that fin hangs lead-in wire 22.
By the configuration of this lead 4, even in that to carry out above-mentioned cross key fashionable, also can eliminate owing to contact the generation unfavorable condition between bonding welding wire 13 and the lead-in wire 22 that hangs fin, can improve the reliability of goods like this.
Have again, carry out above-mentioned intersection bonding easily, can improve the degree of freedom of bonding like this.
Embodiment 6
Fig. 8 shows the sectional view of bright another embodiment according to lead frame of the present invention, and Fig. 9 shows the longitudinal section of the semiconductor device that this lead frame of bright use is made.
Lead frame 1 according to present embodiment is characterised in that, is provided with welding wire support section 15 between the end of the semiconductor chip installing zone 2 of supporter 8 and lead 4.
This welding wire support section 15 is configured in supporter 8 installing zone 2 around, when the assembled semiconductor device, this support section 15 can be supported in a circle welding wire that is bonded between the pressure welding area electrode of semiconductor chip and each lead-in wire on the fixing height.This welding wire support section 15 can form by following manner: with fixing insulating material such as polyimide resin and epoxy resin such as adhesive, or supporter 8 carried out partial operation so that to being that the part that contacts with welding wire is carried out insulation processing at least.
According to this lead frame 1 of present embodiment,, be steady state value so can guarantee the bending height of welding wire because be provided with the welding wire support section 15 that is used to support this bonding welding wire.Therefore, can obtain reducing the effect of mutual short circuit in the welding wire.
Embodiment 7
Figure 10 is the sectional view that shows bright another embodiment according to lead frame of the present invention, and Figure 11 is the longitudinal section of the semiconductor device that shows that this lead frame of bright use is made.
Lead frame 1 according to present embodiment is characterised in that: except the lead frame structure with the embodiment that had described already, also have the slit 17 that welding wire support section 15 is stretched out that is provided with in the anchor clamps 16 of the supporter 8 between the end of the semiconductor chip installing zone 2 of clamping supporter 8 and lead 4.
When lead frame 1 was clamped for anchor clamps 16, the welding wire support section 15 that is provided with in anchor clamps 16 just stretched out from this slit 17.Because welding wire support section 15 is taken away after the welding wire bonding is finished, so whether it exists insulating properties it doesn't matter.
According to present embodiment, insert in the slit 17 of lead frame 1 by the welding wire support section 15 that will be arranged in the anchor clamps 16, can obtain stablizing the effect of bonding.
Embodiment 8
Figure 12 shows the sectional view of bright another embodiment according to lead frame of the present invention, and Figure 13 shows the longitudinal section of the semiconductor device that this lead frame of bright use is made.
Lead frame 1 according to present embodiment is characterised in that: except the structure of lead frame with the embodiment that had described already, allow semiconductor chip installing zone 2 skew of supporter 8, make the surface of the pressure welding area electrode 11 of institute's mounted semiconductor chip 10 and lead 4 demonstrate height much at one.By using well-known stamping technology etc. easily to process this off-set construction.Make the height and position H2 on surface of the height and position H1 on lead surface and institute's mounted semiconductor chip 10 almost equal through this processing, under the situation of the pressure welding area electrode 11 of semiconductor chip 10 and the welding wire bonding between each lead 4, can increase the stability of a circle welding wire 13 that is bonded.Owing to make circulus become fixing by the stability that increases wire spool 13, so the welding wire that can reduce when resin moulded moves.
Embodiment 9
Figure 14 is the plane graph that shows the supporter 8 that uses in the lead frame of bright an alternative embodiment of the invention, and Figure 15 shows the bright plane graph that the state of semiconductor chip 10 is installed on this supporter 8.
Lead frame 1 according to present embodiment is characterised in that: except the structure of lead frame 1 with the embodiment that had described already, also be provided with the mark 18 of a plurality of sizes corresponding to dissimilar institute's mounted semiconductor chip 10 on the surface of supporter 8.By technology such as printing, punching presses this mark 18 can be set easily.
Corresponding to the mark 18 of semiconductor chip size to be installed semiconductor chip is installed by being provided with, is easy to be identified for installing the exact position of semiconductor chip, thereby can improves the efficient of the chip bonding work of semiconductor chip.
Have again,,, so just can stably keep the ring-type of bonding welding wire so welding wire length can be remained constantly because the positional precision of semiconductor chip improves.Owing to make circulus become fixing by the stability that increases the welding wire ring-type, so the welding wire that can reduce when resin moulded moves.
Based on the foregoing description, described the invention that the present inventor makes particularly, but the invention is not restricted to the foregoing description certainly, but can in the scope that does not depart from its main points, revise at different aspect.
For example, illustrated square supporter in the above-described embodiments, but also the supporter of circle can be used as supporter as the supporter of fixing each lead-in wire.When using the supporter of this circle, owing to resin flow becomes when resin moulded steadily, so can obtain reducing the effect that the cavity produces.
In addition, by being used for that the bonding region that purpose is the ground connection bonding is set on the supporter of the foregoing description, can obtain purposes widely with regard to can be used as the lead frame that to finish the ground connection bonding.
Have, mounted semiconductor chip is not limited to a slice on supporter again, but the multi-disc semiconductor chip can be installed, and therefore, the present invention can be applicable to the multi-disc semiconductor device.
Described such a case, i.e. the present invention who is mainly made by the inventor is applicable to the semiconductor device as the field of the invention, and this field has become background of the present invention.But the invention is not restricted to this, but can be widely applicable for the device that those encapsulate with the electronic component that uses lead frame.
The available effect of the disclosed typical case's invention of the application is below described briefly.
(1) according to the present invention, there is following effect: by installing at semiconductor chip with same intervals The end of configuration lead can make the lead end closer to semiconductor chip on the whole periphery in district Installing zone.
(2) according to the present invention, there is following effect: because the effect of describing in above-mentioned (1) item, The length of bonding welding wire can shorten.
(3) according to the present invention, have following effect: the whole periphery along the semiconductor chip installing zone is joined Put the end of lead, make drawing corresponding to the end of the lead in the bight of semiconductor chip installing zone The distance between centers of tracks ratio is wide in the lead spacing of the end of other leads.
(4) according to the present invention, there is following effect: by means of the effect of in above-mentioned (3) item, describing Really, the space in the bonding welding wire is widened at the place, bight.
(5) according to the present invention, there is following effect: by means of in above-mentioned (2) and (4) item The effect of describing can reduce contiguous welding wire and contact with each other the short circuit that causes or welding wire because of moulding resin The welding wire that flows and be out of shape moves.
(6) according to the present invention, there is following effect: by mounting semiconductor chip on supporter, The heat that produces in semiconductor chip can outwards distribute via supporter, therefore can improve semiconductor core The heat dissipation characteristics of sheet.
(7) according to the present invention, there is following effect:, can prevent because injecting by illusory lead-in wire is set The generation in the cavity that the disturbance of resin flow causes.
(8) according to the present invention, there is following effect: by removing the lead-in wire that hangs fin, can be easy Finish the intersection bonding.

Claims (22)

1. semiconductor device, it comprises:
Semiconductor chip;
The supporter of semiconductor chip is installed on it;
Be fixed to lead on the supporter via insulator;
Wherein, by the lead end being fixed on the whole periphery of semiconductor chip installing zone at the adhesive linkage that is provided with on the whole surface of described supporter.
2. semiconductor device, it comprises:
Semiconductor chip;
The supporter of semiconductor chip is installed on it;
Be fixed to lead on the supporter via insulator;
Wherein, by the lead end being fixed on the whole periphery of semiconductor chip installing zone at the adhesive linkage that is provided with on the whole surface of described supporter, with regard to the lead spacing of each lead end, make the twice of maximum lead spacing less than minimum lead spacing.
3. semiconductor device, it comprises:
Semiconductor chip;
The supporter of semiconductor chip is installed on it;
Be fixed to lead on the supporter via insulator;
Wherein, by the lead end being fixed on the whole periphery of semiconductor chip installing zone, make corresponding to the lead spacing of the end of the lead in the bight of semiconductor chip wideer than lead spacing at the end of other leads at the adhesive linkage that is provided with on the whole surface of described supporter.
4. semiconductor device, it comprises:
Semiconductor chip;
The supporter of semiconductor chip is installed on it;
Be fixed to lead on the supporter via insulator;
Wherein, by the lead end being fixed on the whole periphery of semiconductor chip installing zone at the adhesive linkage that is provided with on the whole surface of described supporter, with regard to the lead spacing of each lead end, make the twice of maximum lead spacing, and make corresponding to the lead spacing of the end of the lead in the bight of semiconductor chip wideer than lead spacing at the end of other leads less than minimum lead spacing.
5. according to claim 3 or the described semiconductor device of claim 4, wherein, make corresponding to the lead spacing of the end of the lead in the bight of described semiconductor chip wide more more near the bight of semiconductor chip the time.
6. semiconductor device, it comprises:
Semiconductor chip;
The supporter of semiconductor chip is installed on it;
Be fixed to lead on the supporter via insulator;
Wherein, by the lead end being fixed on the whole periphery of semiconductor chip installing zone at the adhesive linkage that is provided with on the whole surface of described supporter, and
The illusory lead-in wire of not drawing from seal is set in corresponding to the lead in the bight of described semiconductor chip.
7. semiconductor device, it comprises:
Semiconductor chip;
The supporter of semiconductor chip is installed on it;
Be fixed to lead on the supporter via insulator;
Wherein, by the lead end being fixed on the whole periphery of semiconductor chip installing zone at the adhesive linkage that is provided with on the whole surface of described supporter, with regard to the lead spacing of each lead end, make the twice of maximum lead spacing less than minimum lead spacing, and
The illusory lead-in wire of not drawing from seal is set in corresponding to the lead in the bight of described semiconductor chip.
8. according to claim 6 or the described semiconductor device of claim 7, wherein, the end of described illusory lead-in wire is positioned at outside the end of described lead.
9. semiconductor device, it comprises:
Semiconductor chip;
The supporter of semiconductor chip is installed on it;
Be fixed to lead on the supporter via insulator;
Wherein, by the lead end being fixed on the whole periphery of semiconductor chip installing zone, and make the pressure welding area spacing of other pressure welding area electrodes of pressure welding area gap ratio of pressure welding area electrode at the place, bight that is positioned at described semiconductor chip wide at the adhesive linkage that is provided with on the whole surface of described supporter.
10. semiconductor device, it comprises:
Semiconductor chip;
The supporter of semiconductor chip is installed on it;
Be fixed to lead on the supporter via insulator;
Wherein, by the lead end being fixed on the whole periphery of semiconductor chip installing zone at the adhesive linkage that is provided with on the whole surface of described supporter, with regard to the lead spacing of each lead end, make the twice of maximum lead spacing, and make the pressure welding area spacing of other pressure welding area electrodes of pressure welding area gap ratio of pressure welding area electrode at the bight place that is positioned at described semiconductor chip wide less than minimum lead spacing.
11., wherein, make the pressure welding area spacing of a plurality of pressure welding area electrodes of described semiconductor chip wide more more near the bight of semiconductor chip the time according to claim 9 or the described semiconductor device of claim 10.
12. semiconductor device, it comprises:
Semiconductor chip;
The supporter of semiconductor chip is installed on it;
Be fixed to lead on the supporter via insulator;
Wherein, by the lead end being fixed on the whole periphery of semiconductor chip installing zone at the adhesive linkage that is provided with on the whole surface of described supporter, and
To be bonded to corresponding to the lead terminal chiasma in the bight of described semiconductor chip on the pressure welding area electrode of the semiconductor chip that is provided with on the another side of the side that is adjacent to the semiconductor chip relative with the bight being placed therebetween lead.
13., it is characterized in that: make the bight that is adjacent to described semiconductor chip place the pressure welding area gap ratio of pressure welding area electrode therebetween wide corresponding to the lead spacing of the lead end of these pressure welding area electrodes according to claim 1 each described semiconductor device to the claim 12.
14., it is characterized in that:, make the lead end more approach semiconductor chip by configuration lead end on the whole periphery of described semiconductor chip according to claim 1 each described semiconductor device to the claim 13.
15., it is characterized in that: described lead is fixed on the described supporter via insulating adhesive according to claim 1 each described semiconductor device to the claim 14.
16. according to claim 1 each described semiconductor device to the claim 15, it is characterized in that: described supporter is made up of the material of high heat conductance.
17., it is characterized in that: between the semiconductor chip of described supporter and lead end, be provided with the welding wire support section according to claim 1 each described semiconductor device to the claim 16.
18., it is characterized in that: between the semiconductor chip of described supporter and lead end, be provided with the slit that is used to stretch out the welding wire support section according to claim 1 each described semiconductor device to the claim 16.
19. according to claim 1 each described semiconductor device to the claim 18, it is characterized in that: the semiconductor chip installing zone of described supporter is offset, and makes the pressure welding area electrode of semiconductor chip to be installed and lead surface demonstrate height much at one.
20. make the method for semiconductor device, wherein supporter is provided with the semiconductor chip installing zone that is used to install semiconductor chip, simultaneously lead is fixed to via insulator on the periphery of this semiconductor chip installing zone, described method comprises the steps:
On the whole periphery by means of the semiconductor chip installing zone that lead is fixed to supporter at the adhesive linkage that forms on the whole surface of described supporter;
Described semiconductor chip is fixed on the semiconductor chip installing zone of supporter; And
Make described lead and the mutual bonding of described semiconductor chip.
21. lead frame, wherein supporter is provided with the semiconductor chip installing zone that is used to install semiconductor chip and lead is fixed to the periphery of this semiconductor chip installing zone via insulator,
Wherein, by means of lead being fixed on the whole periphery of described semiconductor chip installing zone at the adhesive linkage that forms on the whole surface of described supporter.
22. lead frame, wherein supporter is provided with the semiconductor chip installing zone that is used to install semiconductor chip and lead is fixed to the periphery of this semiconductor chip installing zone via insulator,
Wherein, by means of at the adhesive linkage that forms on the whole surface of described supporter lead being fixed on the whole periphery of described semiconductor chip installing zone, with regard to the lead spacing of each lead end, make the twice of maximum lead spacing less than minimum lead spacing.
CNB971033129A 1996-03-18 1997-03-17 Lead frame and semiconductor device using the lead frame and method of manufacturing the same Expired - Fee Related CN1156910C (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP060421/96 1996-03-18
JP060421/1996 1996-03-18
JP6042196 1996-03-18
JP9008964A JPH09312375A (en) 1996-03-18 1997-01-21 Lead frame, semiconductor device and manufacture thereof
JP008964/97 1997-01-21
JP008964/1997 1997-01-21

Related Child Applications (1)

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CNB2004100368185A Division CN100359678C (en) 1996-03-18 1997-03-17 Semiconductor device

Publications (2)

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CN1164127A true CN1164127A (en) 1997-11-05
CN1156910C CN1156910C (en) 2004-07-07

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CNB971033129A Expired - Fee Related CN1156910C (en) 1996-03-18 1997-03-17 Lead frame and semiconductor device using the lead frame and method of manufacturing the same
CNB2004100368185A Expired - Fee Related CN100359678C (en) 1996-03-18 1997-03-17 Semiconductor device

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US (1) US6265762B1 (en)
JP (1) JPH09312375A (en)
KR (2) KR100475265B1 (en)
CN (2) CN1156910C (en)
MY (1) MY121618A (en)
TW (1) TW347585B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531493A (en) * 2012-06-29 2014-01-22 飞思卡尔半导体公司 Semiconductor device package and manufacture method thereof
CN108735701A (en) * 2017-04-13 2018-11-02 恩智浦美国有限公司 Lead frame with the illusory lead alleviated for the burr during encapsulating

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6692989B2 (en) * 1999-10-20 2004-02-17 Renesas Technology Corporation Plastic molded type semiconductor device and fabrication process thereof
JPH11274196A (en) * 1998-03-26 1999-10-08 Seiko Epson Corp Manufacture of semiconductor device, molding system and the semiconductor device
KR100350046B1 (en) * 1999-04-14 2002-08-24 앰코 테크놀로지 코리아 주식회사 lead frame and semi-conductor package attached heat spreader using the same
US6975021B1 (en) * 1999-09-03 2005-12-13 Micron Technology, Inc. Carrier for substrate film
JP2001230360A (en) * 2000-02-18 2001-08-24 Hitachi Ltd Semiconductor integrated circuit device and method of manufacturing the same
US7199477B1 (en) * 2000-09-29 2007-04-03 Altera Corporation Multi-tiered lead package for an integrated circuit
JP2002134674A (en) * 2000-10-20 2002-05-10 Hitachi Ltd Semiconductor device and its manufacturing method
TW462120B (en) * 2000-11-10 2001-11-01 Siliconware Precision Industries Co Ltd Tape carrier type semiconductor package structure
JP2002176131A (en) * 2000-12-08 2002-06-21 Hitachi Ltd Manufacturing method for semiconductor device
JP3812447B2 (en) * 2002-01-28 2006-08-23 富士電機デバイステクノロジー株式会社 Resin-sealed semiconductor device
KR100477020B1 (en) * 2002-12-16 2005-03-21 삼성전자주식회사 Multi chip package
US7239024B2 (en) * 2003-04-04 2007-07-03 Thomas Joel Massingill Semiconductor package with recess for die
US20050230821A1 (en) * 2004-04-15 2005-10-20 Kheng Lee T Semiconductor packages, and methods of forming semiconductor packages
US7511364B2 (en) 2004-08-31 2009-03-31 Micron Technology, Inc. Floating lead finger on a lead frame, lead frame strip, and lead frame assembly including same
US7388283B2 (en) * 2005-02-04 2008-06-17 Avago Technologies Ecbu Ip Pte Ltd Method and device for integrating an illumination source and detector into the same IC package that allows angular illumination with a common planar leadframe
JP2006278407A (en) * 2005-03-28 2006-10-12 Renesas Technology Corp Manufacturing method of semiconductor device
US8110913B2 (en) * 2007-06-29 2012-02-07 Stats Chippac Ltd. Integrated circuit package system with integral inner lead and paddle
US7750444B2 (en) * 2008-05-19 2010-07-06 Powertech Technology Inc. Lead-on-chip semiconductor package and leadframe for the package
US9337240B1 (en) * 2010-06-18 2016-05-10 Altera Corporation Integrated circuit package with a universal lead frame
CN102332441B (en) * 2010-07-12 2014-05-14 无锡华润安盛科技有限公司 High-alignment-packaging-type lead frame and packaging structure thereof
US8450841B2 (en) * 2011-08-01 2013-05-28 Freescale Semiconductor, Inc. Bonded wire semiconductor device
JP6100648B2 (en) 2013-08-28 2017-03-22 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59105349A (en) * 1982-12-08 1984-06-18 Hitachi Ltd Integrated circuit device
JP2637247B2 (en) * 1989-09-12 1997-08-06 株式会社東芝 Resin-sealed semiconductor device
US4992628A (en) * 1990-05-07 1991-02-12 Kyocera America, Inc. Ceramic-glass integrated circuit package with ground plane
JPH04162556A (en) * 1990-10-25 1992-06-08 Mitsubishi Electric Corp Lead frame and its manufacturing
US5245214A (en) * 1991-06-06 1993-09-14 Northern Telecom Limited Method of designing a leadframe and a leadframe created thereby
US5510649A (en) * 1992-05-18 1996-04-23 Motorola, Inc. Ceramic semiconductor package having varying conductive bonds
JPH07231007A (en) * 1994-02-15 1995-08-29 Toshiba Corp Semiconductor device
JPH0837252A (en) * 1994-07-22 1996-02-06 Nec Corp Semiconductor device
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
JPH0945723A (en) * 1995-07-31 1997-02-14 Rohm Co Ltd Semiconductor chip, semiconductor device incorporated with semiconductor chip and manufacturing method thereof
US5691567A (en) * 1995-09-19 1997-11-25 National Semiconductor Corporation Structure for attaching a lead frame to a heat spreader/heat slug structure
US5905299A (en) * 1996-01-05 1999-05-18 Texas Instruments, Inc. Thermally enhanced thin quad flatpack package
US5771157A (en) * 1996-03-08 1998-06-23 Honeywell, Inc. Chip-on-board printed circuit assembly using aluminum wire bonded to copper pads

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531493A (en) * 2012-06-29 2014-01-22 飞思卡尔半导体公司 Semiconductor device package and manufacture method thereof
CN108735701A (en) * 2017-04-13 2018-11-02 恩智浦美国有限公司 Lead frame with the illusory lead alleviated for the burr during encapsulating
CN108735701B (en) * 2017-04-13 2021-12-24 恩智浦美国有限公司 Lead frame with dummy leads for glitch mitigation during encapsulation

Also Published As

Publication number Publication date
CN1595646A (en) 2005-03-16
MY121618A (en) 2006-02-28
TW347585B (en) 1998-12-11
KR970067736A (en) 1997-10-13
CN1156910C (en) 2004-07-07
CN100359678C (en) 2008-01-02
KR100473261B1 (en) 2005-03-14
JPH09312375A (en) 1997-12-02
KR100475265B1 (en) 2005-07-01
US6265762B1 (en) 2001-07-24

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