JPH07231007A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device with a reduced chip size, standard ized cell size and improved design efficiency by changing the layout of bonding pads on a semiconductor substrate. CONSTITUTION:Along the sides of a main face of a semiconductor substrate 11, pads 12 are formed which are arranged at specified thickness and pitch from these sides, leads 13 face at the sides of the substrate and are electrically connected to the pads by wires 14. A peripheral region B of the substrate has corner parts C. The thickness of one pad disposed near the part C from the nearest side of the substrate is greater than that of other pad disposed at or near the center of said side. If the pads are disposed in this way, the pitch of the pads disposed at and near the parts C can be equal to or greater than that of those disposed at or near the center of said nearest side whereby the wires never contact with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bonding pad on the surface of a semiconductor element for electrically connecting inner leads constituting a lead frame with a bonding wire.

[0002]

2. Description of the Related Art In general, a lead (outer lead) led out from an envelope of a semiconductor device is hermetically sealed in an envelope such as a resin sealing body, and the lead (inner lead) in the envelope is sealed. ) The tip is electrically connected by a bonding wire to a bonding pad on a semiconductor substrate on which a semiconductor element is formed. This is called a wire bonding method. Wire bonding method has a diameter of 25-30
The bonding pad on the chip and the tip of the inner lead are connected by a capillary that moves while ejecting an ultrafine wire such as Au of μm from the nozzle-like tip.
Currently, wire bonding uses a crimping ball diameter of 90 to 1
The conditions of 00 μm, the positional accuracy of 20 to 30 μm, and the minimum pad arrangement interval of 125 to 150 μm have been put into practical use. However, high-density and highly integrated semiconductor devices tend to have a large number of pins, and although the element region of the semiconductor substrate is being reduced, the peripheral portion thereof is restricted by the above conditions. As a result, the chip size is constrained by the peripheral portion, which hinders the reduction of the chip size.

Under these circumstances, efforts are being made to revise the pad peripheral standard for reducing the chip size. For example, the first method is to reduce the pad opening and to approach the pitch between pads. As the second method, investigations such as narrowing the distance between the pad and the chip edge are underway. However, it is not easy to adopt these methods, and there are some problems.

The problem with the first method is that it is necessary to reduce the diameter of the pressure-bonded balls and improve the positional accuracy, and it is impossible to immediately deal with the problem. Further, making the pitches between the adjacent bonding pads close to each other causes a problem such that the bonding wire connecting the bonding pad and the inner lead is easily deformed. This is because the number of pins in the semiconductor device has increased and the length of the bonding wire has become longer, so that the bonding wire is easily deformed and the bonding wires come into contact with each other. A problem with the second method is that when the bonding pad comes close to the chip edge, if the ball bonding is misaligned, it comes into contact with the chip edge and short-circuits with the semiconductor substrate. This is because the scribe line provided as a cutting margin for dicing is not covered with the passivation film in order to prevent the blade of the dicer from being damaged.

As the wire bonding technology has progressed as described above, the bonding pad formed on the semiconductor substrate is normally incident on the bonding wire connecting the inner lead covered with the envelope and the bonding pad on the semiconductor substrate. Arrange so that the criteria such as angle and wire spacing are satisfied. At present, as a method for satisfying these standards, the bonding pads are moved in the horizontal direction so that the pitch between the pads is increased. In order to adopt the movement in the horizontal direction, the movement of the peripheral cells in which the input circuit, the output circuit or the input / output circuit having the bonding pad is formed and the arrangement of the through cells connecting the peripheral cells are dealt with or A method has been adopted in which a plurality of different peripheral cells are prepared in advance and the cells are selected so as to match the bonding pad standard.

FIG. 6 shows an ideal bonding pad arrangement on a semiconductor substrate in a conventional semiconductor device, an inner lead formed in an envelope, and a bonding wire electrically connecting the bonding pad and the inner lead. . As shown in the figure, the semiconductor substrate 11 is mounted on the chip mounting portion 15 of the lead frame 1 with an adhesive, and an element region A in which an integrated circuit is formed is provided in the central portion of the semiconductor substrate 11. There is. Bonding pads 12 electrically connected to the integrated circuit are arranged on the semiconductor substrate 11 substantially parallel to each side of the semiconductor substrate 11 in both the vertical and horizontal directions. The bonding wire 14 for connecting the bonding pad 12 of the semiconductor substrate 11 and the inner lead 13 of the lead frame 1 is the other bonding wire 1 adjacent to the bonding wire 14.
It is necessary to keep a certain interval to prevent contact with the No. Therefore, as in the arrangement of the bonding pads shown in FIG. 6, it is necessary to increase the distance between the bonding pads because the corners are approached.

This becomes clear by drawing a straight line from the inner lead frame 13 toward the center of the semiconductor substrate 11. A row of the inner pads 13 arranged facing the side X is aligned with a row of the bonding pads 12 arranged in proximity to a side X of the semiconductor substrate (lower side of the semiconductor substrate shown in the figure), and bonding is performed. A case where the pad 12 and the inner lead 13 are connected by the bonding wire 14 will be described. At this time, a straight line 16 connecting the facing tips of the inner leads 13 and the bonding pad 12 is drawn, and this straight line 16 is extended to the center of the element region A at the center of the semiconductor substrate 11. Then, when the straight lines 16 are drawn on all the inner leads 13 and the bonding pads 12 facing the side X, the group of straight lines 16 is formed.
The bonding pads 12 are arranged so as to concentrate at the concentration point O at the center of one element region A. Then, on the normal line of the center point of the bonding pad row on the side X, the concentration point O
Is formed. Therefore, the group of straight lines 16 is radially formed up to the tip of the inner lead 13. The radial straight lines 16 have no direct relation to the arrangement of the bonding pads determined by the relation between the chip size and the envelope and do not coincide with the loci of the bonding wires, but are used to see the relative arrangement of the bonding pads. It plays the role of an auxiliary line.

Of the straight line 16 drawn from the inner lead 13 toward the center of the semiconductor substrate 11, the semiconductor substrate 11
The distance (pitch) between a linear bonding pad passing near the center of one side X and a linear bonding pad adjacent to the linear bonding pad is a. Next, the distance (pitch) between the linear bonding pad passing near the corner of the semiconductor substrate 11 and the adjacent linear bonding pad is set to b. Since the position of the concentration point O is on the normal line above the center point of the bonding pad row, the distance between the concentration point O and the bonding pad is such that the straight line passing near the corner is the side X of the semiconductor substrate. Since it is longer than the straight line passing near the central portion, the bonding pad pitch b near the corner portion is wider than the bonding pad pitch a near the central portion (a <b). Thus, by forming the bonding pad row parallel to each side along the straight line 16, ideal wire bonding with few contact accidents between bonding wires is performed.

FIG. 7 is also a plan view of a semiconductor substrate in a conventional semiconductor device. This shows a schematic diagram with peripheral cells formed to approximate the ideal bond pad placement. Bonding pads 12 are formed in peripheral cells 20 such as an output circuit, an input circuit, and an input / output circuit. The bonding pads 12 are all arranged at the same position on the peripheral cells 20 that are repeatedly formed. Normal,
As for the bonding pad position, as the peripheral cell 20 approaches the corner portion C of the semiconductor substrate, the distance between the peripheral cells 20 is also increased to increase the distance between the bonding pads as shown in FIG. A through cell for connecting a power source or the like is arranged between the peripheral cells 20. A plurality of through cells may be arranged depending on the intervals at which the peripheral cells 20 are arranged,
Alternatively, the through cells having different cell widths are prepared so that the intervals are not opened. In addition to the method of connecting the peripheral cells 20 by the through cells, a plurality of types of cell widths of the peripheral cells 20 themselves are prepared so as to cope with different bonding pad intervals.

[0010]

As described above, when the bonding pad 12 of the semiconductor substrate 11 and the inner lead 13 of the lead frame 1 are connected by the conventional method shown in FIGS. 6 and 7, the bonding wires come into contact with each other. Ideal wire bonding with few accidents is performed. However, in order to prevent a contact accident of the bonding wire 14 with another adjacent bonding wire 14, the pitch of the bonding pads near the corner of the semiconductor substrate 11 needs to be wider than the pitch of the bonding pads arranged in the center of the side. However, such an increase in pitch leads to an increase in chip size. Further, in the above design method, the movement of the peripheral cells for arranging the bonding pads in the horizontal direction and the arrangement of the through cells which connect the cells correspondingly are dealt with, or the peripheral cells having different cell widths are prepared in advance. There is a problem that design efficiency is reduced, such as having to prepare multiple types. The present invention has been made under such circumstances, and an object thereof is to provide a semiconductor device having a reduced chip size. Another object of the present invention is to provide a semiconductor device in which the chip size is reduced, the cell size is standardized, and the design efficiency is improved.

[0011]

The semiconductor device of the present invention comprises:
A semiconductor substrate having a central region element region in which an integrated circuit is formed and a peripheral region adjacent to this element region, and formed on the main surface of the semiconductor substrate, along each side of the semiconductor substrate, A plurality of bonding pads arranged at a predetermined depth and a predetermined pitch from the side, a plurality of leads facing a predetermined side of the semiconductor substrate, the plurality of leads and the plurality of bonding pads. And a bonding wire for connecting to the semiconductor substrate, the peripheral region of the semiconductor substrate has a corner portion, and the depth of the bonding pad located near the corner portion from a side closest to the semiconductor substrate. Is characterized by being deeper than the depth from the side of the bonding pad arranged at or near the center of the closest side. Further, the depth of the bonding pad arranged near the corner from the nearest side of the semiconductor substrate may be deeper as the bonding pad approaches the corner.

Further, the pitch between the bonding pads arranged near the corners and the adjacent bonding pads is such that the pitch between the bonding pads formed in the center of the closest side or in the peripheral region in the vicinity thereof. The pitch is substantially equal to or larger than the pitch. Further, the plurality of bonding pads are formed in the peripheral cells connected to the integrated circuit in the element region inside the semiconductor substrate, respectively, and in the peripheral cells of the bonding pads arranged near the corners. It is characterized in that the position is located near the nearest side of the semiconductor substrate, inside the semiconductor substrate, or in the central portion of the peripheral cell.

[0013]

The depth of the bonding pad located near the corner of the semiconductor substrate from the nearest side of the semiconductor substrate is the center of the nearest side or the bonding pad located near the center. By making the depth deeper than the depth, the pitch of the bonding pads arranged in the corner portion and its vicinity is equal to or larger than the pitch of the bonding pads arranged in the center of the closest side or in the vicinity thereof. be able to. Further, the pitch between the adjacent bonding pads of the bonding pads arranged near the corner portion is equal to or more than the pitch of the bonding pads arranged at the center of the closest side or in the vicinity thereof. By increasing the size, the wire bonding can be efficiently performed without contact between the bonding wires. Further, the bonding pad is formed as a part of the peripheral cell connected to the integrated circuit, and the position of the bonding pad arranged in the position near the corner portion in the peripheral cell is outside near the side of the semiconductor substrate. Since it is arranged inside the semiconductor substrate or in the central portion of the peripheral cell, the peripheral cell is fixed in size without preparing a through cell or a peripheral cell having a different cell width. The bonding pads arranged on the cell can be made to correspond to the bonding pad reference.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. FIG. 1 is a plan view showing a part of the semiconductor device. In this embodiment, for example, a resin sealing body such as an epoxy resin is used as an envelope (not shown), and a semiconductor substrate (chip that is mounted on the chip mounting portion 16 of the lead frame sealed by the envelope is a chip). ) 11 is opposed to the inner lead 13 of the lead frame. Then, the semiconductor substrate 11
The bonding pad 12 is electrically connected to the opposing inner lead 13 and the bonding wire 14. The semiconductor substrate 11 is composed of an element region A where an integrated circuit (not shown) is formed and a peripheral region B where a bonding pad 12 is formed.
The bonding pad 12 is provided on the semiconductor substrate 11 via the peripheral cell 20 including an input circuit, an output circuit, an input / output circuit and the like.
It is electrically connected to an internal integrated circuit. Peripheral cell 2
0 is formed in the peripheral portion of the element region A, or is formed in the peripheral region B in contact with the element region A.

Further, a bonding pad may be incorporated in the peripheral cell. The bonding pads 12 are arranged substantially parallel along each side of the semiconductor substrate 11 except in the vicinity of the corners. Corners C1 and C of the semiconductor substrate 11
2, C3 and C4 are boundaries of the pads 12 belonging to each side. Each of the bonding pads 12 has a predetermined peripheral cell 2 of a peripheral cell row formed in the peripheral portion of the element region A via, for example, an Al wiring 19 formed by vapor deposition.
0 (see FIG. 2). Although the pattern shape of the Al wiring 19 is arbitrary, it is general that the Al wiring 19 is patterned in the horizontal direction of the semiconductor substrate 11 and the vertical direction perpendicular thereto, rather than being patterned in any direction as shown in FIG. . Next, the configuration of the corner portion of the semiconductor substrate will be described with reference to FIG. This figure shows a partial plan view in the vicinity of a corner C2, which is the intersection of the side X and the side Y of the semiconductor substrate 11 of FIG. The illustrated region of the semiconductor substrate 11 is a part of the element region A, a corner portion C2, and a region B'in the vicinity thereof. A bisector 17 is additionally described in the corner portion C2, and this line 17 is used as a boundary line between the bonding pad 12 belonging to the side X and the bonding pad 12 belonging to the side Y. Since the semiconductor substrate 11 is a square, the bisector 17 is in contact with the corner of the element region A.

Next, the arrangement of the bonding pads will be described. The bonding pad 12, which is arranged at the center of each side, is provided inside the semiconductor substrate 11 by a predetermined depth d from the side. The interval (pitch) a between the adjacent bonding pads is almost constant. However, the depth (d1 to d10) from the nearest sides X and Y of the semiconductor substrate 11 of the bonding pad 12 located near the corner C2 is:
It is arranged inside the semiconductor substrate 11 deeper than the depth (d) of the bonding pad 12 arranged at the center of the sides X and Y or in the vicinity thereof (d <d1 to d10). When a locus 18 of these bonding pads 12 on the semiconductor substrate 11 is drawn, the locus 18 at the central portion of each side is substantially parallel to that side, but the peripheral region B of the semiconductor substrate 11 has a region B near the corner portion C2. In ′, an arc having a predetermined radius of curvature is drawn. Of course, this locus shape is a feature of this embodiment, and the present invention is not limited to this.
For example, even with the bonding pads arranged in the central portion of each side, the bonding pad close to the neighboring region B ′ can be deeper than the above-mentioned d, and within the neighboring region B ′. The bonding pad trajectory 18 need not be an arc.

As described above, the bonding wire 14 connecting the bonding pad 12 of the semiconductor substrate 11 and the inner lead 13 of the lead frame needs to be kept at a certain interval in order to prevent contact with another adjacent bonding wire 14. There is. Therefore, conventionally, as in the arrangement of the bonding pads shown in FIG. 6, the distance between the bonding pads is widened as the corners are approached. This is from the inner lead 13 to the semiconductor substrate 1.
It becomes clear by drawing a straight line toward the center of 1. The row of the inner pads 13 arranged facing the side X is faced to the row of the bonding pads 12 arranged close to the side X of the semiconductor substrate, and the bonding pads 12 and the inner leads 13 are bonded to each other by a bonding wire. A case of connecting by 14 will be described. At this time, a straight line 1 connecting the tip of the inner lead 13 and the bonding pad 12 facing each other
6 is drawn, and this straight line 16 is extended to the center of the element region 15 at the center of the semiconductor substrate 11. Then, all the inner leads 13 and the bonding pads 1 facing the side X
The bonding pads 12 are arranged so that when the straight line 16 is drawn on the line 2, the straight line group 16 concentrates on the central point O of the device region 15 of the semiconductor substrate 11. And
The concentration point O is formed on the normal line of the center point of the bonding pad row on the side X.

Therefore, the group of straight lines 16 is formed radially up to the tip of the inner lead 13. This radial straight line is not directly related to the bonding pad arrangement determined by the relationship between the chip size and the envelope and does not match the trace of the bonding wire, but it is an aid for observing the relative bonding pad arrangement. Play the role of a line. Among the straight lines 16 drawn from the inner lead 13 toward the center of the semiconductor substrate 11, a straight bonding pad passing near the center of one side X of the semiconductor substrate 11 and a straight bonding pad adjacent to the straight bonding pad. Let a be the pitch. Next, the pitch between a linear bonding pad passing near the corner of the semiconductor substrate 11 and a linear bonding pad adjacent to the linear bonding pad is set to b. Concentration point O
Is formed on the normal line to the center point of the bonding pad row, the distance between the concentration point O and the bonding pad is such that the straight line passing near the corner is near the center of the side X of the semiconductor substrate. It will be longer than the straight line that passes through. Therefore, the bonding pad pitch b near the corner is wider than the bonding pad pitch a near the center of the side X (see FIG. 6).

As a result, conventionally, as described above, the bonding pad pitch in the vicinity of the corner was only widened. However, in the present invention, the depth from each side of the bonding pad along the side X and the side Y is increased. By making the bonding pad near the corner deeper than the other and making the bonding pad pitch near the corner equal to or wider than the other, the bonding wire 14 is brought into contact with another adjacent bonding wire 14. It is possible to prevent this. The row of bonding pads 12 does not necessarily have to be formed along all sides. It is also possible to form only on arbitrary 1 to 3 sides. The number of pads arranged on one side does not have to be the same on each side, and the number of pads on all four sides may be different. Further, the shape of the semiconductor substrate does not have to be square, and can be any shape such as a rectangle and other polygons. For a semiconductor substrate in which the number of bonding pads differs depending on the side,
The position of the concentration point of the straight line 16 drawn as an auxiliary line as shown in (3) may be different for each side.

According to the present invention, the plurality of bonding pads 12 thus arranged on the semiconductor device 11 are not arranged in parallel with the chip edges of the respective sides, and those close to the corners are directed toward the central portion of the semiconductor device 11. It is located close to. The positions of the plurality of bonding pads 12 arranged inside the chip edge of the semiconductor substrate need to be adjusted by the element region A, and the bonding wires 14 for connecting the inner leads 13 and the bonding pads 12 to each other.
It is also necessary to meet the incident angle and wire spacing criteria. Thus, the semiconductor device 11 of the present invention in which the plurality of bonding pads 12 are arranged does not require any modification or addition to the conventional manufacturing process. Next, with reference to FIG. 3, it will be described that the present invention reduces the peripheral portion of the chip, and consequently reduces the size of the entire chip. The figure is a cross-sectional view showing the same corner portion of the semiconductor substrate as in FIG. 2 and the vicinity thereof. The feature of the present invention lies in the vicinity of the corner portion of the semiconductor substrate. As described in the previous figure, the locus 18 shown by the dotted line of the pad row in the area B'in the vicinity of the corner portion draws an arc. However, the locus 18 'indicated by the dotted line in the neighboring region B'of the conventional pad row arranged in parallel along the side of the semiconductor substrate is the same as the other regions and is parallel to the side of the semiconductor substrate. is there. Therefore, when the bonding pads W, Z at the end of the pad row arranged in this vicinity region B'are relocated to the conventional locus 18 ', these bonding pads are relocated and the bonding pads W', Z'are relocated.
Becomes When rearranged in this way, the pad row to which these bonding pads W ', Z'belong becomes longer along each side, and the pad row on the side X is Δ more than that in FIG.
Only X extends along this side, and the pad row on side Y extends along this side by ΔY. As a result, the lengths of the two sides of the semiconductor substrate of the semiconductor device used in the first embodiment could be reduced by ΔX and ΔY as compared with the conventional one.

Next, a second embodiment will be described with reference to FIGS. FIG. 4 is a plan view of a peripheral cell such as an output circuit used in this semiconductor device, and FIG. 5 is a plan view of a semiconductor device using this peripheral cell. The peripheral cell 30 includes, for example, an output circuit and a bonding pad 31 electrically connected to the output circuit. The output circuit includes, for example, a semiconductor element 3 such as a P-type MOS transistor or an N-type MOS transistor.
It is composed of 2, 33. The VDD power supply wiring and the VSS power supply wiring formed on the semiconductor substrate are formed in the peripheral cell 30, but may be arranged on a semiconductor substrate other than the peripheral cell. In this figure, the bonding pads 31 are arranged at three positions of the upper stage, the middle stage and the lower stage of the peripheral cell 30,
Therefore, in this embodiment, as shown in FIGS. 4A to 4C, three types of peripheral cells 30 are used. That is, the bonding pad 31 changes its position by being arranged in the gap between the semiconductor elements in each peripheral cell. In this embodiment, since the bonding pad is arranged between the two semiconductor devices, the bonding pad can take three different positions. However, if the number of semiconductor devices is larger, the pad position is larger. Becomes
The degree of freedom of the position of the bonding pad at the corner of the semiconductor substrate is increased. For example, the peripheral cell 30 of FIG.
Is provided with four semiconductor elements 32, 33, 34, and 35, the pad position is considered to be five.

In this figure, it is arranged second from the top. Then, the peripheral cells 30 are arranged in the peripheral portion of the peripheral region B of the semiconductor substrate 11. In this case, the peripheral cell 3
The lower stage of 0 is arranged on each side of the semiconductor substrate 11, and the upper stage is arranged inside the semiconductor substrate 11. All the peripheral cells have the same function, the same cell size, and the power supply wirings are arranged at the same position, and only the bonding pad 31 is arranged differently for each peripheral cell. FIG. 5 shows FIG.
3 is a plan view of the semiconductor substrate 11 in which the peripheral cells 30 shown in FIG. The peripheral cells 30 are selected such that the bonding pads 31 arranged in the peripheral cells 30 are arranged in the inward direction of the chip as the corners of the semiconductor substrate 11 are approached. In the conventional example shown in FIG. 6, the bonding pad 12 has a larger pad pitch and a larger chip size as it approaches the corner portion of the semiconductor substrate 11, and a through cell is required. The same cell size is used, but three types of peripheral cells having different bonding pad 31 positions inside the peripheral cells are appropriately selected and arranged, and the corners of the semiconductor substrate 11 are arranged in the same manner as in the first embodiment. The position of the bonding pad 31 arranged near the portion is made deeper than the depth of the bonding pad 31 near the center of the side of the semiconductor substrate 11.

By arranging the bonding pads in this way, it is possible to use the same cell size even when approaching the corner portion of the semiconductor substrate 11, and it is possible to design without using through cells. In this embodiment, three types of cells are used depending on the positions of the bonding pads in the peripheral cells, but the positions of the bonding pads may be increased. If more types are used, the locus of the bonding pad arrangement near the corner of the semiconductor substrate can be made as close to an arc as possible.
The present invention uses the conventional lead frame and does not require any change or addition of the manufacturing process of the semiconductor device such as the bonding technique. In addition, by conducting research on a multi-pin semiconductor device in the field of wire bonding, which is currently underway, it is possible to reduce the pressure bonding ball diameter of the bonding tool, the bonding pads and the bonding wires, and the deformation of the bonding wires. The present invention can also be applied to the technique of suppressing.

[0024]

As described above, according to the present invention, the peripheral region of the semiconductor substrate can be reduced by changing the position of the bonding pad on the semiconductor substrate, and as a result, the chip size can be reduced. Further, even in the multi-pin semiconductor device in which the number of connection pads is increased due to improvement in the function and integration of the semiconductor device, it is possible to reduce the chip size while maintaining the current reliability of wire bonding. Further, by using a plurality of standardized peripheral cells in which bonding pads are arranged, a conventional lead frame is used, and the semiconductor device manufacturing process such as bonding technology is not required to be changed or added. The device can be manufactured.

[Brief description of drawings]

FIG. 1 is a partial plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a partial plan view of the semiconductor substrate of the first embodiment.

FIG. 3 is a partial cross-sectional view of a semiconductor substrate illustrating the effect of the present invention.

FIG. 4 is a plan view of a peripheral cell used in the semiconductor device of the second embodiment.

FIG. 5 is a plan view of a semiconductor substrate used for the semiconductor device of the second embodiment.

FIG. 6 is a partial plan view of a conventional semiconductor device.

FIG. 7 is a plan view of a semiconductor substrate used for a conventional semiconductor device.

[Explanation of symbols]

 1 Lead Frame 11 Semiconductor Substrate 12, 31 Bonding Pad 13 Inner Lead 14 Bonding Wire 15 Chip Mounting Part 16 Straight Line 17 2 Dividing Lines 18 Bonding Pad Track 19 Al Wiring 20, 30 Peripheral Cell 32, 33, 34, 35 Semiconductor Device

Claims (4)

[Claims] 1. A semiconductor substrate having a central region element region in which an integrated circuit is formed and a peripheral region adjacent to the element region; and a semiconductor substrate formed on a main surface of the semiconductor substrate. A plurality of bonding pads arranged along the side at a predetermined depth and a predetermined pitch from the side, a plurality of leads facing a predetermined side of the semiconductor substrate, the plurality of leads and the A bonding wire that connects a plurality of bonding pads, wherein the peripheral region of the semiconductor substrate has a corner portion, and the bonding pad disposed at a position near the corner portion is the most part of the semiconductor substrate of the bonding pad. The depth from the near side is deeper than the depth from the side of the bonding pad arranged at or near the center of the closest side. Semiconductor device. 2. The depth of the bonding pad located near the corner from the nearest side of the semiconductor substrate is deeper as the bonding pad approaches the corner. 1. The semiconductor device according to 1. 3. The pitch between the bonding pads arranged near the corners and the adjacent bonding pads is such that the pitch between the bonding pads formed at the center of the closest side or in the peripheral region in the vicinity thereof. 3. The semiconductor device according to claim 1 or 2, wherein the pitch is substantially equal to or larger than the pitch. 4. The plurality of bonding pads are respectively formed in peripheral cells connected to an integrated circuit in the element region inside the semiconductor substrate, and the bonding pads of the bonding pads arranged near the corners are formed. 4. The position in the peripheral cell is located near the nearest side of the semiconductor substrate, inside the semiconductor substrate, or in the central part of the peripheral cell, according to any one of claims 1 to 3. The semiconductor device according to.