CN116406169A - Organic field effect transistor memory and preparation method thereof - Google Patents
Organic field effect transistor memory and preparation method thereof Download PDFInfo
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- CN116406169A CN116406169A CN202310277624.7A CN202310277624A CN116406169A CN 116406169 A CN116406169 A CN 116406169A CN 202310277624 A CN202310277624 A CN 202310277624A CN 116406169 A CN116406169 A CN 116406169A
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Abstract
The invention discloses an organic field effect transistor memory, which comprises a source electrode layer, a drain electrode layer, an organic semiconductor vapor deposition layer, a soluble semiconductor layer, a charge storage layer, a self-assembly layer, a gate insulating layer and a gate electrode layer as a substrate, wherein the source electrode layer, the drain electrode layer, the organic semiconductor vapor deposition layer, the soluble semiconductor layer, the charge storage layer, the self-assembly layer and the gate insulating layer are sequentially arranged from top to bottom, and the gate insulating layer is positioned on the gate electrode layer. The invention also discloses a preparation method of the organic field effect transistor memory. The organic field effect transistor memory and the preparation method thereof provided by the invention can effectively improve the growth morphology of the TIPS-Pentacene and PS mixed solution after phase separation, and improve the performances such as the yield and mobility of devices.
Description
Technical Field
The invention relates to an organic field effect transistor memory and a preparation method thereof, belonging to the technical field of semiconductor memories.
Background
In the past few years, facing the high-speed development of electronic products such as flat panel display drivers, radio frequency identification tags and sensors, organic Field Effect Transistors (OFETs) have also been developed toward high carrier mobility, large memory space and more easily fabricated thin films, and considerable progress has been made in integrating them into chips. The obtaining of the desired properties of the device by mixing two or more organic components is one of the methods for preparing the desired thin film, with the aim of obtaining better properties or perfecting the deficiency by utilizing the complementary advantages of the two materials. If the materials are soluble in the same solvent, the desired solvent is better prepared and better solvent mixing is achieved. This approach has a number of applications in heterojunction cells and light emitting diodes, but there are still many limitations to the use in organic field effect transistors.
Compared with a single-component film, the Organic Field Effect Transistor (OFETs) film prepared by multiple solute solutions has different film properties due to the influence of solubility in the solute solvent, solvent volatilization speed, solute crystallization speed, substrate surface hydrophilicity and hydrophobicity and the like. Meanwhile, the spin coating of the solution can be combined with different spin coating methods, such as ink-jet printing, solution film scooping, photo etching and meniscus shearing methods, to obtain the device high-quality film.
The organic field effect transistor memory is an organic field effect transistor having a memory function, and thus parameters for evaluating the performance of the organic field effect transistor memory generally include characteristic parameters of the field effect transistor as a carrier (output versus transfer characteristic curve, field effect mobility, threshold voltage, current switching ratio) and characteristic parameters of the memory (memory window, sustain time, number of read-write erase cycles, etc.). PS (polystyrene) is a common dielectric material with a high dielectric constant and good solution processability, which effectively reduces the operating voltage of the organic field effect transistor memory. TIPS-Pentacene is a common organic semiconductor layer, has good solubility in organic solvents, and has a price which is low compared with other solvent-soluble organic semiconductor layer materials, so that the TIPS-Pentacene is one of the best choices for preparing OFETs by the solution spin coating method at present. The solution prepared by dissolving PS and TIPS-Pentacene in anisole has a deeper research on forming an organic semiconductor transmission layer for preparing OFETS by vertical phase separation by utilizing surface energy drive, but due to the problems of dripping size of spin-coating solution, humidity in the environment and the like, the problems of lower yield and mobility in the OFETS are inevitably caused.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides an organic field effect transistor memory and a preparation method thereof, which can effectively improve the growth morphology of a TIPS-Pentacene and PS mixed solution after phase separation and improve the performances of device yield, mobility and the like.
In order to solve the technical problems, the invention adopts the following technical scheme:
an organic field effect transistor memory comprises a source electrode layer, a drain electrode layer, an organic semiconductor vapor deposition layer, a soluble semiconductor layer, a charge storage layer, a self-assembly layer, a gate insulating layer and a gate electrode layer as a substrate, wherein the source electrode layer, the drain electrode layer, the organic semiconductor vapor deposition layer, the soluble semiconductor layer, the charge storage layer, the self-assembly layer and the gate insulating layer are sequentially arranged from top to bottom, and the gate insulating layer is positioned on the gate electrode layer.
The source electrode layer and the drain electrode layer are made of metal Cu; the material of the organic semiconductor vapor deposition layer is pentacene; the gate insulating layer is made of silicon dioxide; the gate electrode is highly doped silicon.
The thickness of the source electrode layer and the drain electrode layer is 100nm; the thickness of the organic semiconductor layer is 30-50 nm; the thickness of the gate insulating layer is 50nm.
A preparation method of an organic field effect transistor memory comprises the following steps:
step a, octadecyl trichlorosilane is dissolved in toluene for dilution, so that OTS self-assembly solution is obtained;
step b, dissolving the TIPS-Pentacene in anisole solvent, heating to completely dissolve the TIPS-Pentacene, and standing to obtain a TIPS-Pentacene solution; dissolving PS in anisole solvent, standing and dissolving at normal temperature to obtain PS solution; mixing the TIPS-Pentacene solution with the PS solution, heating, magnetically stirring and mixing for standby to obtain a mixed solution;
step c, taking a silicon wafer as a substrate, wherein the silicon wafer comprises an N-type heavily doped silicon as a gate electrode layer and a gate insulating layer grown on the gate electrode layer, and sequentially cleaning the silicon wafer by acetone, ethanol and deionized water, and drying the silicon wafer;
d, placing the cleaned substrate treated in the step c into ultraviolet ozone for treatment;
step e, placing the substrate treated in the step d in the solution prepared in the step a under a vacuum environment, standing, taking out, rinsing with toluene, blowing off the surface solution with a blower, and drying in an oven to obtain the substrate with the self-assembled layer;
f, placing the sample prepared in the step e in ultraviolet ozone treatment, sucking the mixed solution prepared in the step b by using an injector, spin-coating a film on the self-assembled layer prepared in the step e, placing the spin-coated sample in an oven, and removing redundant solvent to obtain a charge storage layer and a soluble semiconductor layer;
and g, sequentially carrying out vacuum evaporation on the organic semiconductor layer and the source-drain electrode layer on the charge storage layer prepared in the step f.
In step a, the concentration after dilution was 0.03mmol/ml.
In the step b, the concentration of the TIPS-Pentacene solution is 20mg/mL, and the heating temperature of the TIPS-Pentacene is 70 ℃; PS solution concentration is 20mg/mL; the TIPS-Pentacene solution and the PS solution were mixed in a volume ratio of 1:4, and the heating temperature was 70 ℃.
In the step c, the thickness of the gate insulating layer is 50nm; in the step d, the ultraviolet ozone treatment time is 10min.
In the step e, standing for 12 hours; the oven drying temperature is 90 ℃ and the time is 1h.
In the step f, the external ozone treatment time is 10min, the oven drying temperature is 90 ℃ and the time is 30min; the spin coating process comprises the following steps: regulating the rotating speed to 2000rpm to uniformly rotate for 30s.
In the step g, the vacuum evaporation process comprises the following steps: vapor deposition rate
Vacuum degree is controlled to be 5 multiplied by 10 -4 Pa～4×10 - 4 Pa。
The invention has the beneficial effects that: the invention provides an organic field effect crystalThe body tube memory and the preparation method thereof are a method for introducing an OTS self-assembled film through a solution processing method by a spin coating mode, so that the growth morphology of the TIPS-Pentacene and PS mixed solution after phase separation is effectively improved, and the yield and mobility of the device are improved; the charge storage layer of the organic field effect transistor memory provided by the invention is prepared by adopting a solution spin coating method, has the characteristics of simple preparation process and large-area preparation, and adopts easily available materials with low price; the organic field effect transistor memory provided by the invention can generate higher carrier mobility under a lower operating voltage condition, and has good transistor performance; the organic field effect transistor memory provided by the invention has a large storage space, is stable in one hundred-time read-write-erase cycle test, has no obvious charge leakage condition in a ten-thousand-second maintenance time test, and can be stably maintained at 10 2 . The storage performance is stable; the organic field effect transistor memory provided by the invention has simple preparation process, can prepare and regulate the appearance of the thin film in a large area, and is convenient for popularization and integrated commercial application.
Drawings
FIG. 1 is a schematic diagram of an organic field effect transistor memory according to the present invention;
FIG. 2 a is an AFM image of an OTS film in an organic field effect transistor memory of example 1, and b is a non-UV pre-hydrophilic-hydrophobic test image of the OTS film;
FIG. 3 a is an AFM surface morphology of TIPS-Pentacene after vertical phase separation of TIPS-Pentacene and PS in an organic field effect transistor memory according to example 1, and b is a Pentacene AFM image evaporated over TIPS-Pentacene;
FIG. 4 is a graph showing a transfer characteristic of an organic field effect transistor memory according to the present invention;
FIG. 5 is a graph showing the output characteristics of an organic field effect transistor memory according to the present invention;
fig. 6 is a memory characteristic curve of an organic field effect transistor memory according to the present invention:
FIG. 7 is a diagram showing the read-write-erase characteristics of an organic field effect transistor memory according to the present invention:
FIG. 8 is a graph showing the retention characteristics of an organic field effect transistor memory according to the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings, and the following examples are only for more clearly illustrating the technical aspects of the present invention, and are not to be construed as limiting the scope of the present invention.
In the present invention, polystyrene (PS) and soluble semiconductor 6, 13-bis (triisopropylsilylethynyl) Pentacene (TIPS-Pentacene) were purchased from sigma company, and Pentacene and Octadecyltrichlorosilane (OTS) were purchased from TCI company.
As shown in fig. 1, the invention discloses an organic field effect transistor memory, the structure of the memory sequentially comprises a source electrode layer, a drain electrode layer, an organic semiconductor evaporation layer, a soluble semiconductor layer, a charge storage layer, a self-assembled layer, a gate insulating layer and a gate electrode layer as a substrate from top to bottom, wherein the self-assembled film layer is formed by dissolving OTS in toluene and soaking a substrate in the solution for 12 hours; the soluble semiconductor layer and the charge storage layer are prepared by spin-coating TIPS-Pentacene and PS in anisole solution on an OTS film after ultraviolet.
The organic field effect transistor memory uses N-type heavily doped silicon as a gate electrode layer, and silicon dioxide with the thickness of 50nm growing on the N-type heavily doped silicon is used as a gate insulating layer; the cleaned substrate is put into OTS solution after being ultraviolet, and is kept stand for 12 hours under vacuum condition, then is cleaned and dried by toluene solution, and the cleaned sample is respectively spin-coated with mixed solution with the ratio of 1:4 after being ultraviolet. Pentacene with the thickness of about 40nm is evaporated to be used as an organic semiconductor layer, and metal Cu with the thickness of 100nm is used as a source electrode and a drain electrode.
The preparation method of the organic field effect transistor memory comprises the following specific steps:
step one, preparing OTS self-assembly solution: and (3) dissolving octadecyl trichlorosilane in toluene, and carrying out ultrasonic treatment for 15min to obtain a self-assembly solution with the diluted concentration of 0.03mmol/ml for later use.
Preparing a solution method to prepare a mixed solution: dissolving TIPS-Pentacene in anisole solvent with concentration of 20mg/mL, heating at 70deg.C to dissolve completely, and standing to obtain TIPS-Pentacene solution; dissolving PS in anisole solvent with concentration of 20mg/mL, standing at normal temperature for dissolving to obtain PS solution for later use; mixing TIPS-Pentacene with PS solution at a ratio of 1:4, heating at 70deg.C, and magnetically stirring.
And thirdly, taking the N-type heavily doped silicon and the silicon wafer of the 50nm gate insulating layer grown on the N-type heavily doped silicon as a substrate, and sequentially cleaning the silicon wafer by using acetone, ethanol and deionized water, and drying the silicon wafer.
And fourthly, placing the cleaned substrate after treatment in ultraviolet ozone for 10min.
And fifthly, placing the treated substrate in the configured OTS solution under a vacuum environment, and standing for 12h. Taking out, rinsing with toluene, blowing off the surface solution with a blower, and drying in an oven at 90 ℃ for 1h to obtain a substrate with a hydrophobic film layer, wherein the prepared film AFM photograph is shown as a in FIG. 2, b is a hydrophilic-hydrophobic test image of the OTS film before ultraviolet, and the contact angle is changed, so that the OTS film is successfully attached to the substrate.
And step six, placing the prepared sample on an ultraviolet ozone treatment for 10min, cooling to room temperature, sucking the prepared mixed solution OTS film by a syringe, spin-coating the film on the prepared mixed solution OTS film, placing the spin-coated sample in a baking oven at 90 ℃ for 30min, removing the redundant solvent, and obtaining a charge storage layer and a soluble semiconductor layer, wherein the prepared film AFM photo is shown as a picture in figure 3.
Step seven, vacuum evaporating pentacene and a source-drain Cu electrode on the device in sequence, wherein the evaporation rate is
Vacuum degree is controlled to be 5 multiplied by 10 -4 Pa～4×10 -4 Pa, and obtaining the product. Wherein the channel width of the mask was 1500 μm and the length thereof was 100 μm, a thin film AFM photograph was prepared as shown in FIG. 3 b.
In the preparation process of the organic field effect transistor memory, the room temperature of a laboratory is always constant at 25 ℃ and the humidity is kept below 50%.
Comparative example 1
The organic field effect transistor memory prepared by the solution method comprises the following specific steps:
step one, preparing a mixed solution by a solution preparation method: dissolving TIPS-Pentacene in anisole solvent with concentration of 20mg/mL, heating at 70deg.C to dissolve completely, and standing to obtain TIPS-Pentacene solution; dissolving PS in anisole solvent with concentration of 20mg/mL, standing at normal temperature for dissolving to obtain PS solution for later use; mixing TIPS-Pentacene with PS solution at a ratio of 1:4, heating at 70deg.C, and magnetically stirring;
cutting the N-type heavily doped silicon and the 50nm silicon dioxide gate insulating layer grown on the N-type heavily doped silicon into a size of 1.5cm multiplied by 1.5cm, cleaning the N-type heavily doped silicon and the 50nm silicon dioxide gate insulating layer by 15min acetone, 15min ethanol and 15min deionized water in sequence, and drying the N-type heavily doped silicon and the silicon dioxide gate insulating layer at 120 ℃.
And thirdly, placing the clean substrate after the drying treatment in ultraviolet ozone for 10min.
Step four, sucking the prepared mixed solution by an injector, spin-coating a film on the ultraviolet substrate, placing the spin-coated sample in a 90 ℃ oven for 30min, and removing the redundant solvent to obtain a charge storage layer and a soluble semiconductor layer;
step five, pentacene and a source-drain Cu electrode are sequentially vacuum evaporated on the charge storage layer, wherein the evaporation rate is that
Vacuum degree is controlled to be 5 multiplied by 10 -4 Pa～4×10 -4 Pa. Wherein the width of the channel of the mask is 1500 μm and the length is 100 μm.
After the device fabrication of example 1 and comparative example 1 was completed, the organic field effect transistor memories fabricated in example 1 and comparative example 1 were tested for electrical properties using Keithley 4200, respectively, and the test results were as follows:
FIG. 4 a is a graph showing the transfer curve of the memory device of comparative example 1, in which carrier mobility is 0.042cm 2 V -1 s -1 Threshold voltage (-3.28V), switching ratio is greater than 10 4 . Figure 4b is a transfer curve of the memory device made in example 1,as can be seen from the graph, the carrier mobility was 0.10cm 2 V -1 s -1 Threshold voltage (1.62V), switching ratio greater than 10 4 . By comparison, it is obviously found that the carrier mobility, threshold voltage and the like of the device can be greatly improved by introducing the OTS film.
FIG. 5 a is a graph showing the output curve of the memory device of comparative example 1, and FIG. 5 b is a graph showing the output curve of the memory device of example 1, where V is fixed DS The output curves are tested under the conditions of different grid voltages of between 0V and 2V, between 4V and 6V and between 8V and 10V, and the OTS self-assembled thin film device is better in field effect characteristic.
Fig. 6 is a graph showing the memory characteristic of the device of example 1, and it can be seen from the graph that the OTS self-assembled thin film has bipolar memory characteristics, can store both holes and electrons, and has a large memory window.
Fig. 7 shows that the memory of example 1 also has good repeated erasing capability on the surface of the positive-negative write-read-erase-read characteristic data, and the erasing window of the device is not changed basically after a certain period of erasing cycles. .
FIG. 8 is a graph showing the positive and negative data retention capabilities of the device of example 1, from which it can be seen that the memory switching ratio of the device remains at 10 after 10000s 2 As described above, the memory reliability of the device is high.
According to the detection results of comparative example 1 and example 1, the organic field effect transistor memory and the preparation method thereof can greatly improve the carrier mobility of the device, and have the capability of multiple reading, writing and erasing compared with the device without introducing OTS self-assembled film, and have good stability. And the device material is low in cost and has a certain commercial value.
The foregoing is only a preferred embodiment of the invention, it being noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the invention.
Claims (10)
1. An organic field effect transistor memory, characterized by: the organic semiconductor memory device comprises a source electrode layer, a drain electrode layer, an organic semiconductor vapor deposition layer, a soluble semiconductor layer, a charge storage layer, a self-assembly layer, a gate insulating layer and a gate electrode layer which are sequentially arranged from top to bottom, wherein the gate insulating layer is positioned on the gate electrode layer.
2. An organic field effect transistor memory according to claim 1, wherein: the source electrode layer and the drain electrode layer are made of metal Cu; the material of the organic semiconductor vapor deposition layer is pentacene; the gate insulating layer is made of silicon dioxide; the gate electrode is highly doped silicon.
3. An organic field effect transistor memory according to claim 1, wherein: the thickness of the source electrode layer and the drain electrode layer is 100nm; the thickness of the organic semiconductor layer is 30-50 nm; the thickness of the gate insulating layer is 50nm.
4. A preparation method of an organic field effect transistor memory is characterized by comprising the following steps: the method comprises the following steps:
step a, octadecyl trichlorosilane is dissolved in toluene for dilution, so that OTS self-assembly solution is obtained;
step b, dissolving the TIPS-Pentacene in anisole solvent, heating to completely dissolve the TIPS-Pentacene, and standing to obtain a TIPS-Pentacene solution; dissolving PS in anisole solvent, standing and dissolving at normal temperature to obtain PS solution; mixing the TIPS-Pentacene solution with the PS solution, heating, magnetically stirring and mixing for standby to obtain a mixed solution;
step c, taking a silicon wafer as a substrate, wherein the silicon wafer comprises an N-type heavily doped silicon as a gate electrode layer and a gate insulating layer grown on the gate electrode layer, and sequentially cleaning the silicon wafer by acetone, ethanol and deionized water, and drying the silicon wafer;
d, placing the cleaned substrate treated in the step c into ultraviolet ozone for treatment;
step e, placing the substrate treated in the step d in the solution prepared in the step a under a vacuum environment, standing, taking out, rinsing with toluene, blowing off the surface solution with a blower, and drying in an oven to obtain the substrate with the self-assembled layer;
f, placing the sample prepared in the step e in ultraviolet ozone treatment, sucking the mixed solution prepared in the step b by using an injector, spin-coating a film on the self-assembled layer prepared in the step e, placing the spin-coated sample in an oven, and removing redundant solvent to obtain a charge storage layer and a soluble semiconductor layer;
and g, sequentially carrying out vacuum evaporation on the organic semiconductor layer and the source-drain electrode layer on the charge storage layer prepared in the step f.
5. The method for manufacturing an organic field effect transistor memory according to claim 4, wherein: in step a, the concentration after dilution was 0.03mmol/ml.
6. The method for manufacturing an organic field effect transistor memory according to claim 4, wherein: in the step b, the concentration of the TIPS-Pentacene solution is 20mg/mL, and the heating temperature of the TIPS-Pentacene is 70 ℃; PS solution concentration is 20mg/mL; the TIPS-Pentacene solution and the PS solution were mixed in a volume ratio of 1:4, and the heating temperature was 70 ℃.
7. The method for manufacturing an organic field effect transistor memory according to claim 4, wherein: in the step c, the thickness of the gate insulating layer is 50nm; in the step d, the ultraviolet ozone treatment time is 5min.
8. The method for manufacturing an organic field effect transistor memory according to claim 4, wherein: in the step e, standing for 12 hours; the oven drying temperature is 90 ℃ and the time is 1h.
9. The method for manufacturing an organic field effect transistor memory according to claim 4, wherein: in the step f, the external ozone treatment time is 10min, the oven drying temperature is 90 ℃ and the time is 30min; the spin coating process comprises the following steps: regulating the rotating speed to 2000rpm to uniformly rotate for 30s.
10. The method for manufacturing an organic field effect transistor memory according to claim 4, wherein: in the step g, the vacuum evaporation process comprises the following steps: vapor deposition rate
Vacuum degree is controlled to be 5 multiplied by 10 -4 Pa～4×10 -4 Pa。
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