CN116387312A - GaN HEMT device - Google Patents

GaN HEMT device Download PDF

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Publication number
CN116387312A
CN116387312A CN202310342327.6A CN202310342327A CN116387312A CN 116387312 A CN116387312 A CN 116387312A CN 202310342327 A CN202310342327 A CN 202310342327A CN 116387312 A CN116387312 A CN 116387312A
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gan
barrier layer
metal anode
hemt device
layer
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Inventor
张辉
付杰
严丹妮
刘成
叶念慈
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Hunan Sanan Semiconductor Co Ltd
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Hunan Sanan Semiconductor Co Ltd
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Priority to CN202310342327.6A priority Critical patent/CN116387312A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The application discloses a GaN HEMT device, which comprises a substrate, a buffer layer, a GaN channel layer and a barrier layer, wherein the substrate, the buffer layer, the GaN channel layer and the barrier layer are stacked along a first direction, and the surface of the barrier layer far away from the GaN channel layer is provided with a source electrode, a grid electrode structure and a drain electrode which are mutually spaced; the reverse free-wheeling diode is arranged on the surface of the barrier layer, far away from the GaN channel layer, between the grid structure and the drain electrode, and comprises a metal anode and a plurality of first P-GaN structures, wherein each first P-GaN structure is at least partially positioned on one side of the metal anode, close to the drain electrode, and the plurality of first P-GaN structures are in contact with the metal anode and are arranged in a comb-tooth shape. The first P-GaN structures are arranged on the surface of the barrier layer, which is far away from the GaN channel layer, and the plurality of first P-GaN structures are arranged in parallel and at intervals in the second direction, and the metal anode and the barrier layer form Schottky contact and ohmic contact with the first P-GaN structures. Through the arrangement, the problems of large reverse leakage current and poor voltage withstand capability of the integrated Schottky diode in the prior art are solved.

Description

GaN HEMT device
Technical Field
The application relates to the field of semiconductors, in particular to a GaN HEMT device.
Background
Compared with the first generation of semiconductor material Si, the third generation of wide band gap semiconductor material GaN has more excellent physical properties of the material, and the physical parameters such as the band gap, the electron mobility, the electron saturation rate, the critical breakdown electric field, the thermal conductivity, the high/low frequency Baliga figure of merit and the like are far higher than those of the Si material. Currently, P-GaN gate power HEMTs have been commercialized and have excellent performance.
In many power switching circuits, such as inverters and DC-DC converters, power transistors need to be connected in anti-parallel with freewheeling diodes to achieve reverse conduction. However, since the P-GaN gate power HEMT has no body diode, the coupling of the reverse turn-on voltage of the HEMT to the device threshold voltage results in a higher reverse turn-on voltage, which results in higher energy losses and lower efficiency. External parallel diodes not only add cost, but also introduce additional parasitic inductance and capacitance. One solution to this problem is to integrate a planar schottky diode on the HEMT, but planar schottky diodes suffer from the disadvantages of large reverse leakage current and poor withstand voltage.
Disclosure of Invention
The application mainly provides a GaN HEMT device to solve the problem that integrated Schottky diode reverse leakage current is big, withstand voltage ability is poor among the prior art.
In order to solve the technical problems, one technical scheme adopted by the application is as follows: the GaN HEMT device comprises a substrate, a buffer layer, a GaN channel layer and a barrier layer which are sequentially stacked along a first direction; the surface of the barrier layer far away from the GaN channel layer is provided with a source electrode, a grid electrode structure and a drain electrode which are mutually spaced, and the grid electrode structure is arranged between the source electrode and the drain electrode.
The semiconductor device further comprises a reverse freewheeling diode integrated on the surface of the barrier layer, which is far away from the GaN channel layer, wherein the reverse freewheeling diode is arranged between the grid structure and the drain electrode and comprises a metal anode and a plurality of first P-GaN structures, the metal anode and the grid structure are arranged at intervals, each first P-GaN structure is at least partially positioned on one side of the metal anode, which is close to the drain electrode, and the first P-GaN structures are in contact arrangement with the metal anode and are arranged in a comb-tooth shape. The first P-GaN structures are arranged on the surface, far away from the GaN channel layer, of the barrier layer, the metal anode extends along the second direction, the first P-GaN structures are mutually parallel and are arranged at intervals in the second direction, and each first P-GaN structure extends along the third direction; and the metal anode and the barrier layer form Schottky contact and form ohmic contact with the first P-GaN structure.
The beneficial effects of this application are: different from the condition of the prior art, the application discloses a GaN HEMT device, which comprises a substrate, a buffer layer, a GaN channel layer and a barrier layer which are stacked along a first direction, wherein the surface of the barrier layer, which is far away from the GaN channel layer, is provided with a source electrode, a grid electrode structure and a drain electrode which are mutually spaced; the reverse free-wheeling diode is integrated on the surface of the barrier layer far away from the GaN channel layer and located between the grid structure and the drain electrode, and comprises a metal anode and a plurality of first P-GaN structures, wherein each first P-GaN structure is at least partially located on one side of the metal anode close to the drain electrode, and the plurality of first P-GaN structures are in contact with the metal anode and are arranged in a comb-tooth shape. The first P-GaN structures are arranged on the surface of the barrier layer, which is far away from the GaN channel layer, the metal anodes extend along the second direction, the plurality of first P-GaN structures are arranged in parallel and at intervals in the second direction, the metal anodes and the barrier layer form Schottky contact, and ohmic contact is formed between the metal anodes and the first P-GaN structures. Through the arrangement, the problems of large reverse leakage current and poor voltage withstand capability of the integrated Schottky diode in the prior art are solved.
Drawings
For a clearer description of embodiments of the present application or of the solutions of the prior art, the drawings that are required to be used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the present application, and that other drawings may be obtained, without inventive effort, by a person skilled in the art from these drawings, in which:
fig. 1 is a schematic structural diagram of a first embodiment of a GaN HEMT device provided in the present application;
fig. 2 is a schematic top view of the GaN HEMT device provided in fig. 1;
fig. 3 is a schematic cross-sectional view of a first cross-section of the GaN HEMT device provided in fig. 1;
fig. 4 is a schematic cross-sectional view of a second cross-section of the GaN HEMT device provided in fig. 1;
fig. 5 is a schematic structural diagram of a second embodiment of a GaN HEMT device provided in the present application;
fig. 6 is a schematic cross-sectional view of a first cross-section of the GaN HEMT device provided in fig. 5;
fig. 7 is a schematic structural diagram of a third embodiment of a GaN HEMT device provided in the present application;
fig. 8 is a schematic cross-sectional view of a first cross-section of the GaN HEMT device provided in fig. 7;
fig. 9 is a schematic structural diagram of a fourth embodiment of a GaN HEMT device provided in the present application;
fig. 10 is a schematic cross-sectional view of a first cross-section of the GaN HEMT device provided in fig. 9;
fig. 11 is a schematic flow chart of a method for manufacturing a GaN HEMT device provided by the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," "third," and the like in the embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1 to 10, fig. 1 is a schematic structural diagram of a first embodiment of a GaN HEMT device provided in the present application, fig. 2 is a schematic structural diagram of a top view of the GaN HEMT device provided in fig. 1, fig. 3 is a schematic structural diagram of a first cross section of the GaN HEMT device provided in fig. 1, fig. 4 is a schematic structural diagram of a second cross section of the GaN HEMT device provided in fig. 1, fig. 5 is a schematic structural diagram of a second embodiment of the GaN HEMT device provided in the present application, fig. 6 is a schematic structural diagram of a first cross section of the GaN HEMT device provided in fig. 5, fig. 7 is a schematic structural diagram of a third embodiment of the GaN HEMT device provided in the present application, fig. 8 is a schematic structural diagram of a first cross section of the GaN HEMT device provided in fig. 7, fig. 9 is a schematic structural diagram of a fourth embodiment of the GaN HEMT device provided in the present application, and fig. 10 is a schematic structural diagram of a first cross section of the GaN HEMT device provided in fig. 9.
Referring to fig. 1, the present application provides a GaN HEMT device 100, where the GaN HEMT device 100 includes a substrate 1, a buffer layer 2, a GaN channel layer 3 and a barrier layer 4 sequentially stacked along a first direction A1, a surface of the barrier layer 4 away from the GaN channel layer 3 is provided with a source 5, a gate structure 6 and a drain 7 spaced apart from each other, and the gate structure 6 is disposed between the source 5 and the drain 7. The GaN HEMT device 100 further includes a reverse freewheeling diode 8, the reverse freewheeling diode 8 is integrated on the surface of the barrier layer 4 away from the GaN channel layer 3, and the reverse freewheeling diode 8 is disposed between the gate structure 6 and the drain electrode 7. Specifically, the reverse flywheel diode 8 includes a metal anode 81 and a plurality of first P-GaN structures 82, where the metal anode 81 and the gate structure 6 are disposed at intervals, each first P-GaN structure 82 is at least partially located on a side of the metal anode 81 near the drain electrode 7, and the plurality of first P-GaN structures 82 are disposed in contact with the metal anode 81 and are arranged in a comb-tooth shape. The first P-GaN structures 82 are disposed on the surface of the barrier layer 4 away from the GaN channel layer 3, the metal anode 81 extends along the second direction A2, the plurality of first P-GaN structures 82 are disposed parallel to each other and spaced apart from each other in the second direction A2, and each of the first P-GaN structures 82 extends along the third direction A3. The metal anode 81 forms a schottky contact with the barrier layer 4 and an ohmic contact with the first P-GaN structure 82. The first direction A1 is a thickness direction of the GaN HEMT device 100, the third direction A3 is a direction extending from the source 5 to the drain 7, i.e., a length direction, and the second direction A2 is a direction perpendicular to the third direction A3 and the first direction A1, i.e., a width direction.
Through the above arrangement, in the second direction A2, the plurality of first P-GaN structures 82 are arranged in a comb-tooth shape, that is, the plurality of first P-GaN structures 82 are parallel to each other and are arranged at intervals, and the plurality of first P-GaN structures 82 do not completely cover the barrier layer 4, so when the GaN HEMT device 100 is turned on in the forward direction, the drain electrode 7 applies positive pressure, the integrated reverse freewheeling diode 8 is in an off state, and 2DEG (two-dimensional electron gas) still exists in the GaN channel layer 3 below the barrier layer 4 which is not covered by the plurality of first P-GaN structures 82, so that the GaN HEMT device 100 is normally turned on. When the GaN HEMT device 100 is turned off and withstand voltage, the integrated reverse freewheeling diode 8 bears voltage, holes in the plurality of first P-GaN structures 82 arranged in a comb-tooth shape are mutually depleted with 2DEG in the GaN channel layer 3 below the interval positions of the plurality of first P-GaN structures 82, a super-node structure is formed, a local electric field concentration effect can be improved, a device drift region electric field is modulated, breakdown voltage of the GaN HEMT device 100 is improved, a Schottky barrier reduction effect is greatly weakened, and leakage current of the GaN HEMT device 100 is reduced. When the GaN HEMT device 100 is in reverse follow current, one end of the source electrode 5 of the GaN HEMT device 100 is in positive pressure, the Schottky junction formed by the metal anode 81 and the barrier layer 4 is conducted, and current reaches the drain electrode 7 through the 2DEG channel below the barrier layer 4, so that loss is small, and the problems of large reverse leakage current and poor voltage withstand capability of the integrated Schottky diode in the prior art are effectively solved.
Specifically, the gate structure 6 includes a second P-GaN structure 61 and a gate 62 that are stacked, the second P-GaN structure 61 is disposed on a surface of the barrier layer 4 away from the GaN channel layer 3, the gate 62 is disposed on a surface of the second P-GaN structure 61 away from the barrier layer 4, the source 5 forms ohmic contact with the barrier layer 4, the drain 7 forms ohmic contact with the barrier layer 4, the gate 62 and the second P-GaN structure 61 may form ohmic contact or may also form schottky contact, and the metal anode 81 is electrically connected with the source 5, where the material of the barrier layer 4 includes AlGaN, and the material of the buffer layer 2 may include GaN.
Referring to fig. 1 to 4, along the second direction A2, the metal anode 81 is in contact with both the surface of the first P-GaN structure 82 remote from the barrier layer 4 and the surface of the barrier layer 4 remote from the GaN channel layer 3, and a part of the metal anode 81 covers a part of the first P-GaN structure 82 and another part of the metal anode 81 covers a part of the barrier layer 4. The GaN HEMT device 100 includes a first section B1 and a second section B2 that are spaced apart in the second direction A2 and parallel to each other, the first section B1 being located in a region where the first P-GaN structures 82 are located, the second section B2 being located in a region spaced between the plurality of first P-GaN structures 82, on the first section B1, the metal anode 81 covering a portion of a surface of the first P-GaN structures 82 away from the barrier layer 4, on the second section B2, a surface of the barrier layer 4 away from the GaN channel layer 3 being not provided with the first P-GaN structures 82, the metal anode 81 being entirely located on a surface of the barrier layer 4 away from the GaN channel layer 3 and covering a portion of a surface of the barrier layer 4 away from the GaN channel layer 3. Wherein in the second direction A2, the width of the metal anode 81 is the same as the width of the barrier layer 4, and the ratio of the first P-GaN structure 82 on the surface of the barrier layer 4 away from the GaN channel layer 3 is between 10% -90%.
Specifically, in this embodiment, referring to fig. 3 and 4, the first P-GaN structure 82 is located between the gate structure 6 and the drain electrode 7, the first P-GaN structure 82 is spaced from the gate structure 6, the first P-GaN structure 82 is spaced from the drain electrode 7, as shown in fig. 3, on the first cross section B1, the metal anode 81 covers the first end of the first P-GaN structure 82 near the gate structure 6 and is located on the surface of the first P-GaN structure 82 far from the barrier layer 4, on the first cross section B1, the metal anode 81 is completely located on the surface of the first P-GaN structure 82 far from the barrier layer 4 and does not cover the surface of the barrier layer 4 far from the GaN channel layer 3, so that effective contact between the metal anode 81 and the first P-GaN structure 82 is achieved.
It can be understood that, in this embodiment, the plurality of first P-GaN structures 82 are arranged in a comb-tooth shape, and the two-dimensional electron gas in the GaN channel layer 3 under the barrier layer 4 covered by the first P-GaN structures 82 is partially consumed by the influence of the first P-GaN structures 82, but the two-dimensional electron gas in the GaN channel layer 3 under the barrier layer 4 not covered by the first P-GaN structures 82 is not consumed, and the GaN HEMT device 100 is still normally turned on. The multiple first P-GaN structures 82 of the reverse freewheeling diode 8 of the GaN HEMT device 100 are arranged in a comb-tooth shape, so that the on-resistance of the GaN HEMT device 100 is not affected by the doping concentration and thickness variation of the first P-GaN structure 82, the parameters of the first P-GaN structure 82 can be freely adjusted, the electric field can be better adjusted, the voltage-withstanding capability of the GaN HEMT device 100 is improved, and the schottky leakage current is reduced.
Referring to fig. 5 and 6, in another embodiment, the first P-GaN structure 82 is still located between the gate structure 6 and the drain electrode 7, and on the first cross section B1, the metal anode 81 covers the surface of the first P-GaN structure 82 away from the barrier layer 4 and is spaced apart from the first end and the second end of the first P-GaN structure 82, the first end of the first P-GaN structure 82 is the end close to the gate structure 6, the second end is the end close to the drain electrode 7, that is, on the first cross section B1, the metal anode 81 is completely located on the surface of the first P-GaN structure 82 away from the barrier layer 4, a part of the first P-GaN structure 82 is located on the side of the metal anode 81 close to the gate structure 6, and another part is located on the side of the metal anode 81 close to the drain electrode 7, so as to ensure effective contact between the metal anode 81 and the first P-GaN structure 82. The first P-GaN structure 82 extends toward the gate structure 6 near the first end of the gate structure 6, and the first end of the first P-GaN structure 82 may be disposed in contact with the gate structure 6, specifically, the first end of the first P-GaN structure 82 may be disposed in contact with the second P-GaN structure 61 of the gate structure 6, and the second end of the first P-GaN structure 82 is disposed at a distance from the drain electrode 7.
In other embodiments, the first end of the first P-GaN structure 82 may be spaced apart from the gate structure 6, the second end of the first P-GaN structure 82 near the drain electrode 7 may extend toward the drain electrode 7 and be in contact with the drain electrode 7, the metal anode 81 may be spaced apart from the drain electrode 7, or the first P-GaN structure 82 may be spaced apart from both the gate structure 6 and the drain electrode 7.
Referring to fig. 7 and 8, in another embodiment, a first P-GaN structure 82 is located between the gate structure 6 and the drain electrode 7, the first P-GaN structure 82 is spaced apart from the gate structure 6, and the first P-GaN structure 82 is spaced apart from the drain electrode 7. On the first section B1, along the third direction A3, a part of the metal anode 81 covers the first P-GaN structure 82 near the first end of the gate structure 6 and is located on the surface of the first P-GaN structure 82 far away from the barrier layer 4, and another part of the metal anode 81 covers the end face of the first P-GaN structure 82 near the first end of the gate structure 6, that is, on the first section B1, part of the metal anode 81 is located on the surface of the first P-GaN structure 82 far away from the barrier layer 4 and part of the metal anode 81 is located on the surface of the barrier layer 4 far away from the GaN channel layer 3, and the metal anode 81 is in contact with both the barrier layer 4 and the first P-GaN structure 82, so that the metal anode 81 can be in more effective contact with the first P-GaN structure 82, and dynamic characteristics of the GaN HEMT device 100 are ensured.
Referring to fig. 9 and 10, in still another embodiment, the metal anode 81 and the first P-GaN structure 82 are both disposed on the surface of the barrier layer 4 away from the GaN channel layer 3, the metal anode 81 is located between the gate structure 6 and the first P-GaN structure 82 on the first cross section B1, the first P-GaN structure 82 is located on the side of the metal anode 81 near the drain 7, and the metal anode 81 covers the end face of the first P-GaN structure 82 near the first end of the gate structure 6, that is, on the first cross section B1, the end face of the metal anode 81 near the first P-GaN structure 82 is disposed in contact with the surface of the metal anode 81 near the drain 7, and on the second cross section B2, the metal anode 81 covers a portion of the surface of the barrier layer 4 away from the GaN channel layer 3. The first P-GaN structure 82 may be spaced apart from the drain electrode 7, or may extend to be in contact with the drain electrode 7.
In this embodiment, the metal anode 81 and the first P-GaN structure 82 form an effective ohmic contact, and in the third direction A3, the length of the metal anode 81 of the reverse flywheel diode 8 is matched with the process, and may be identical to the length of the gate 62 or the drain 7, or may be slightly longer than the length of the gate 62 or the drain 7. In other embodiments, the first P-GaN structure 82 may be provided in other shapes.
The doping concentration of the first P-GaN structure 82 may be different from the doping concentration of the second P-GaN structure 61, for example, the doping concentration of the first P-GaN structure 82 is in the range of 1E16-5E19, the doping concentration of the second P-GaN structure 61 is in the range of 1E17-1E19, or the doping concentration of the second P-GaN structure 61 may be in the range of 1E17-1E18, so that the GaN HEMT device 100 has good performance. In other embodiments, the doping concentration of the first P-GaN structure 82 may be the same as the doping concentration of the second P-GaN structure 61, wherein the thicknesses of the first P-GaN structure 82 and the second P-GaN structure 61 may be the same or different. Specifically, the first P-GaN structure 82 and the second P-GaN structure 61 may be formed from the same P-GaN layer, which is beneficial to reducing process complexity and process difficulty, and simplifying process compared to the first P-GaN structure 82 and the second P-GaN structure 61 that are formed using different P-GaN layers.
In a specific embodiment, the plurality of first P-GaN structures 82 of the reverse freewheeling diode 8 are disposed at equal intervals in the second direction A2, the spacing between two adjacent first P-GaN structures 82 is equal, specifically, the spacing between two adjacent first P-GaN structures 82 is in the range of 50nm-5 μm, and the width of each first P-GaN structure 82 may also be set in the range of 50nm-5 μm, so that the performance of the GaN HEMT device 100 is stronger, parasitic parameters are reduced, and the chip area is saved. In other embodiments, the plurality of P-GaN structures may be disposed at unequal intervals, and the interval between two adjacent first P-GaN structures 82 may be set to other values.
Referring to fig. 11, fig. 11 is a schematic flow chart of a method for manufacturing a GaN HEMT device provided in the present application.
Referring to fig. 11, the present application further provides a preparation method of the GaN HEMT device 100, where the preparation method includes:
s1: a substrate 1 is provided and a nitride epitaxial layer is prepared on the substrate 1.
Specifically, a substrate 1 is provided and a nitride epitaxial layer is prepared and formed from one surface of the substrate 1, wherein the nitride epitaxial layer comprises a buffer layer 2, a GaN channel layer 3, a barrier layer 4 and a P-GaN layer which are sequentially stacked, and the material of the barrier layer 4 comprises GaN. The nitride epitaxial layer can be formed by vapor deposition, sputtering, and the like.
S2: the P-GaN layer of the nitride epitaxial layer is etched to form the first P-GaN structure 82 and the second P-GaN structure 61.
Specifically, the P-GaN layer in the nitride epitaxial layer formed in the step S1 is selectively etched, so that the P-GaN layer forms a plurality of first P-GaN structures 82 and second P-GaN structures 61, where the plurality of first P-GaN structures 82 are arranged in a comb-tooth shape, and in the second direction A2, the plurality of first P-GaN structures 82 are parallel to each other and are arranged at intervals. Along the third direction A3, the first P-GaN structures 82 and the second P-GaN structures 61 may be disposed at intervals or may be disposed in contact with each other, which can be understood that in this embodiment, the first P-GaN structures 82 formed by the preparation are arranged in a comb-tooth shape, which can effectively solve the problems of large reverse leakage current and poor voltage-withstanding capability of the integrated schottky diode in the prior art.
S3: a source electrode 5 and a drain electrode 7 are prepared on the surface of the barrier layer 4 remote from the GaN channel layer 3.
Specifically, after step S2, a metal is deposited on the surface of the barrier layer 4 of the nitride epitaxial layer remote from the GaN channel layer 3, and the deposited metal forms an effective ohmic contact with the barrier layer 4. The deposited metal is spaced apart from the first P-GaN structure 82 and the second P-GaN structure 61, and along the second direction A2, a portion of the deposited metal is located on a side of the second P-GaN structure 61 away from the first P-GaN structure 82 to form the source 5, and a portion is located on a side of the first P-GaN structure 82 away from the second P-GaN structure 61 to form the drain 7. That is, the first P-GaN structure 82 and the second P-GaN structure 61 are located between the source 5 and the drain 7, and the first P-GaN structure 82 is located at a side of the second P-GaN structure 61 near the drain 7.
S4: a metal anode 81 is prepared.
Specifically, metal is deposited on the surface of the plurality of first P-GaN structures 82 away from the barrier layer 4 and the surface of the barrier layer 4 away from the GaN channel layer 3, along the second direction A2, the deposited metal partially covers the surface of the first P-GaN structures 82 away from the barrier layer 4, partially covers the surface of the barrier layer 4 between two adjacent first P-GaN structures 82 away from the GaN channel layer 3, the deposited metal forms ohmic contact with the first P-GaN structures 82 and forms schottky contact with the barrier layer 4, and in the third direction A3, the deposited metal is disposed at intervals with the source electrode 5 and the drain electrode 7 to form the metal anode 81. The metal anode 81 forms a reverse freewheeling diode 8 with the plurality of first P-GaN structures 82.
S5: a gate 62 is prepared at the surface of the second P-GaN structure 61 remote from the barrier layer 4.
Specifically, a metal is deposited on the surface of the second P-GaN structure 61 away from the barrier layer 4, such that the metal completely covers the second P-GaN structure 61, and the deposited metal forms a schottky contact with the second P-GaN structure 61 to prepare the gate 62.
Through the method, the GaN HEMT device 100 provided by the application can be finally prepared and formed, and the problems of large reverse leakage current and poor voltage withstand capability of the integrated Schottky diode in the prior art can be solved.
The application discloses a GaN HEMT device 100, through the integration GaN HEMT device 100 that has reverse freewheel diode 8 that this application provided, reverse freewheel diode 8 includes the first P-GaN structure 82 that a plurality of intervals set up for the reverse conduction loss of GaN HEMT device 100 is less, withstand voltage ability is strong, leakage current is little, parasitic parameter is less, has practiced thrift the chip area, has effectively solved the problem that integrated schottky diode reverse leakage current is big among the prior art, withstand voltage ability is poor.
The foregoing description is only exemplary embodiments of the present application and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.

Claims (11)

1. A GaN HEMT device comprises a substrate, a buffer layer, a GaN channel layer and a barrier layer which are sequentially stacked along a first direction; the surface of the barrier layer, which is far away from the GaN channel layer, is provided with a source electrode, a grid electrode structure and a drain electrode which are mutually spaced, and the grid electrode structure is arranged between the source electrode and the drain electrode; it is characterized in that the method comprises the steps of,
the reverse freewheeling diode is integrated on the surface of the barrier layer far away from the GaN channel layer, is arranged between the grid structure and the drain electrode, comprises a metal anode and a plurality of first P-GaN structures, wherein the metal anode and the grid structure are arranged at intervals, each first P-GaN structure is at least partially positioned on one side of the metal anode, which is close to the drain electrode, and the plurality of first P-GaN structures are arranged in contact with the metal anode and are arranged in a comb-tooth shape; the first P-GaN structures are arranged on the surface, far away from the GaN channel layer, of the barrier layer, the metal anode extends along the second direction, the first P-GaN structures are mutually parallel and are arranged at intervals in the second direction, and each first P-GaN structure extends along the third direction; the metal anode and the barrier layer form Schottky contact and form ohmic contact with the first P-GaN structure;
wherein the third direction is a direction extending from the source to the drain, and the second direction is a direction perpendicular to the third direction and the first direction.
2. The GaN HEMT device of claim 1, wherein along the second direction, the metal anode is in contact with both a surface of the first P-GaN structure that is remote from the barrier layer and a surface of the barrier layer that is remote from the GaN channel layer, and a portion of the metal anode covers a portion of the first P-GaN structure and another portion of the metal anode covers a portion of the barrier layer;
the GaN HEMT device comprises a first section and a second section which are spaced in the second direction and are parallel to each other, wherein the metal anode covers part of the surface of the first P-GaN structure, which is far away from the barrier layer, on the first section, and the metal anode covers part of the surface of the barrier layer, which is far away from the GaN channel layer, on the second section.
3. The GaN HEMT device of claim 2, wherein the first P-GaN structure is spaced apart from the gate structure and the first P-GaN structure is spaced apart from the drain;
on the first section, the metal anode covers the surface of the first P-GaN structure, which is close to the first end of the grid structure and is far away from the barrier layer, of the first P-GaN structure; or (b)
And on the first section, along the third direction, a part of the metal anode covers the surface of the first P-GaN structure, which is close to the first end of the grid structure and is far away from the barrier layer, and the other part of the metal anode covers the end face of the first P-GaN structure, which is close to the first end of the grid structure.
4. The GaN HEMT device of claim 2, wherein, in the first cross-section, the metal anode overlies a surface of the first P-GaN structure remote from the barrier layer and is disposed in spaced relation to first and second ends of the first P-GaN structure; the first P-GaN structure extends towards the gate structure near the first end of the gate structure and is arranged in contact with the gate structure.
5. The GaN HEMT device of claim 1, wherein the metal anode and the first P-GaN structure are both disposed on a surface of the barrier layer away from the GaN channel layer, the first P-GaN structure being on a side of the metal anode near the drain;
the GaN HEMT device comprises a first section and a second section which are spaced in the second direction and are parallel to each other, and the end face of the first P-GaN structure, which is close to the first end of the gate structure, is in contact with the surface of the metal anode, which is close to the drain electrode, on the first section; on the second section, the metal anode covers a portion of the surface of the barrier layer remote from the GaN channel layer.
6. The GaN HEMT device of claim 1, wherein the first P-GaN structure extends toward the drain proximate the second end of the drain and is disposed in contact with the drain, the metal anode being disposed in spaced relation to the drain.
7. The GaN HEMT device of claim 1, wherein the gate structure comprises a second P-GaN structure and a gate that are stacked, the second P-GaN structure being disposed on a surface of the barrier layer that is remote from the GaN channel layer, the gate being disposed on a surface of the second P-GaN structure that is remote from the barrier layer; the source electrode and the barrier layer form ohmic contact, the drain electrode and the barrier layer form ohmic contact, and the grid electrode and the second P-GaN structure form ohmic contact or Schottky contact; the metal anode is electrically connected with the source electrode;
the doping concentration of the second P-GaN structure is the same as that of the first P-GaN structure, and the thickness of the second P-GaN structure is the same as that of the first P-GaN structure.
8. The GaN HEMT device of claim 7, wherein the second P-GaN structure is formed from the same P-GaN layer as the first P-GaN structure.
9. The GaN HEMT device of claim 1, wherein when the GaN HEMT device is forward turned on, the drain is positive and the reverse freewheeling diode is off, the GaN channel layer corresponding to the position of the barrier layer not covered by the first P-GaN structure having two-dimensional electron gas.
10. The GaN HEMT device of claim 1, wherein the material of the barrier layer comprises AlGaN; along the second direction, a plurality of the first P-GaN structures cover 10% -90% of the surface of the barrier layer away from the GaN channel layer.
11. The GaN HEMT device of claim 1, wherein a plurality of the first P-GaN structures are arranged at equal intervals in the second direction, and a distance between two adjacent first P-GaN structures is 50nm-5um.
CN202310342327.6A 2023-03-31 2023-03-31 GaN HEMT device Pending CN116387312A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118116915A (en) * 2024-04-23 2024-05-31 南京大学 Comb-tooth-shaped anti-irradiation GaN HEMT device structure and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118116915A (en) * 2024-04-23 2024-05-31 南京大学 Comb-tooth-shaped anti-irradiation GaN HEMT device structure and manufacturing method thereof
CN118116915B (en) * 2024-04-23 2024-07-02 南京大学 Comb-tooth-shaped anti-irradiation GaN HEMT device structure and manufacturing method thereof

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