CN113611742A - GaN power device integrated with Schottky tube - Google Patents

GaN power device integrated with Schottky tube Download PDF

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Publication number
CN113611742A
CN113611742A CN202110907784.6A CN202110907784A CN113611742A CN 113611742 A CN113611742 A CN 113611742A CN 202110907784 A CN202110907784 A CN 202110907784A CN 113611742 A CN113611742 A CN 113611742A
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conductive material
layer
barrier layer
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CN113611742B (en
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罗小蓉
贾艳江
张�成
邓思宇
孙涛
杨可萌
魏杰
廖德尊
郗路凡
赵智家
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a GaN power device integrated with a Schottky tube. When the integrated Schottky tube is in a forward conduction state, the integrated Schottky tube is in a turn-off state; during reverse follow current, the integrated Schottky tube is conducted, so that the Schottky tube has low conduction voltage drop and fast reverse recovery characteristic, and the area of a device is reduced; two-dimensional electron gas under the P-type GaN grid depletion gate is combined with the P-type highly-doped GaN barrier layer with pores to realize an enhanced vertical device; the P-type high-doping GaN barrier layer modulates the electric field distribution to realize high voltage resistance; the tri-gate structure can provide stronger gate control capability and improve the switching speed of the device.

Description

GaN power device integrated with Schottky tube
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a GaN power device integrated with a Schottky tube.
Background
Since the GaN material has superior characteristics of a wide band gap, a high electron saturation velocity, a high electron mobility, a high critical breakdown electric field, and the like, the GaN device can efficiently operate at high temperature, high voltage, and high frequency. Compared with a lateral GaN HEMT (High-electron-mobility transistor) device, the vertical GaN device has the advantages that the electric field peak value is far away from the surface of the device, the breakdown voltage mainly depends on the thickness of a drift layer, and the sensitivity to traps and surface states is low, so that the vertical GaN device is more suitable for High-power application.
In many power switching applications it is desirable for the device to have a low loss reverse conduction capability to provide a freewheeling path for an inductive load. Because the conduction voltage drop of the body diode of the vertical GaN device is large, large power loss is caused, and low-loss reverse conduction is usually realized by connecting a power transistor and a freewheeling diode in reverse parallel. This approach not only increases cost and chip area, but also introduces additional parasitic inductance and capacitance.
Disclosure of Invention
In order to solve the problems, the invention provides a GaN power device integrated with a Schottky tube.
The technical scheme of the invention is as follows:
a GaN power device integrated with a Schottky tube comprises a first conductive material 1, an N-type highly-doped GaN layer 2, a GaN buffer layer 3, a barrier layer 4 and a passivation layer 5 which are sequentially stacked from bottom to top in the vertical direction of the device; a P-type highly-doped GaN barrier layer 7 with pores is inserted into the GaN buffer layer 3, and the discontinuous P-type highly-doped GaN barrier layers 7 are symmetrically distributed along the transverse direction of the device; along the transverse direction of the device, the center of the device comprises a grid structure and a Schottky anode groove structure which are arranged in parallel along the longitudinal direction of the device, second conductive materials 6 are symmetrically distributed on two sides of the device, and a space is reserved between the second conductive materials 6 and the two structures;
the longitudinal direction is a third dimension direction perpendicular to the transverse direction and the vertical direction;
a drain electrode is led out from the lower surface of the first conductive material 1;
the second conductive material 6 penetrates through the passivation layer 5 from top to bottom and is in contact with the barrier layer 4, the contact type is ohmic contact, and a source electrode is led out of the upper surface of the second conductive material 6;
the method is characterized in that:
the Schottky anode groove structure consists of a dielectric material 8 and a third conductive material 9, sequentially penetrates through the passivation layer 5 and the barrier layer 4 from top to bottom, is in contact with the GaN buffer layer 3, is positioned right above the hole of the P-type highly-doped GaN barrier layer 7, and has a groove width larger than the width of the hole of the P-type highly-doped GaN barrier layer 7; the dielectric material 8 is located at the bottom and side walls of the trench; the third conductive material 9 is embedded in the dielectric material 8 at the bottom of the groove, the bottom of the third conductive material is in contact with the GaN buffer layer 3, the contact type is Schottky contact, and the anode of a Schottky diode is led out of the upper surface of the third conductive material 9 and is in short circuit with the source electrode;
the grid structure comprises a P-type GaN layer 10, a dielectric material 12 and a fourth conductive material 11, wherein the P-type GaN layer 10 penetrates through the passivation layer 5 and is in contact with the barrier layer 4, and the dielectric material 12 covers the top of the P-type GaN layer 10 and the front side wall and the rear side wall of the semiconductor along the longitudinal direction; the fourth conductive material 11 covers the dielectric material 12;
the grid is led out from the upper surface of the fourth conductive material 11.
The Schottky diode is integrated in the longitudinal direction to realize reverse follow current, so that the area is saved and parasitic parameters are reduced compared with the mode of externally connecting the follow current diodes in parallel in a reverse direction; the P-type highly-doped GaN barrier layer assists in depleting the drift region, so that electric field distribution is optimized, and further the withstand voltage of the device is improved; the P-type high-doping GaN barrier layer with the pores enables two-dimensional electron gas (2DEG) to form vertical current only through the pores, and the enhancement type vertical device is realized by combining the P-type GaN gate with the 2DEG under the depletion gate; the tri-gate structure can provide stronger gate control capability and improve the switching speed of the device.
Drawings
FIG. 1 is a schematic structural view of example 1;
FIG. 2 is a sectional view along AA' of example 1;
FIG. 3 is a sectional view taken along BB' of example 1;
FIG. 4 is a sectional view taken along line CC' of example 1;
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
example 1
As shown in fig. 1, the device comprises a first conductive material 1, an N-type highly doped GaN layer 2, a GaN buffer layer 3, a barrier layer 4 and a passivation layer 5 which are sequentially stacked from bottom to top along the vertical direction of the device; a P-type highly-doped GaN barrier layer 7 with pores is inserted into the GaN buffer layer 3, and the discontinuous P-type highly-doped GaN barrier layers 7 are symmetrically distributed along the transverse direction of the device; along the transverse direction of the device, the center of the device comprises a grid structure and a Schottky anode groove structure which are arranged in parallel along the longitudinal direction of the device, second conductive materials 6 are symmetrically distributed on two sides of the device, and a space is reserved between the second conductive materials 6 and the two structures;
the longitudinal direction is a third dimension direction perpendicular to the transverse direction and the vertical direction;
a drain electrode is led out from the lower surface of the first conductive material 1;
the second conductive material 6 penetrates through the passivation layer 5 from top to bottom and is in contact with the barrier layer 4, the contact type is ohmic contact, and a source electrode is led out of the upper surface of the second conductive material 6;
the method is characterized in that:
the Schottky anode groove structure consists of a dielectric material 8 and a third conductive material 9, sequentially penetrates through the passivation layer 5 and the barrier layer 4 from top to bottom, is in contact with the GaN buffer layer 3, is positioned right above the hole of the P-type highly-doped GaN barrier layer 7, and has a groove width larger than the width of the hole of the P-type highly-doped GaN barrier layer 7; the dielectric material 8 is located at the bottom and side walls of the trench; the third conductive material 9 is embedded in the dielectric material 8 at the bottom of the groove, the bottom of the third conductive material is in contact with the GaN buffer layer 3, the contact type is Schottky contact, and the anode of a Schottky diode is led out of the upper surface of the third conductive material 9 and is in short circuit with the source electrode;
the grid structure comprises a P-type GaN layer 10, a dielectric material 12 and a fourth conductive material 11, wherein the P-type GaN layer 10 penetrates through the passivation layer 5 and is in contact with the barrier layer 4, and the dielectric material 12 covers the top of the P-type GaN layer 10 and the front side wall and the rear side wall of the semiconductor along the longitudinal direction; the fourth conductive material 11 covers the dielectric material 12;
the grid is led out from the upper surface of the fourth conductive material 11.
The working principle of the embodiment is as follows: when the grid electrode is blocked in the forward direction, a low potential is applied to the grid electrode, the P-type GaN depletes a 2DEG channel below the grid electrode, and a current path above a hole of the P-type highly-doped GaN blocking layer is blocked, so that the device is turned off, and enhancement is realized; the P-type highly-doped GaN barrier layer assists in depleting the drift region, optimizing electric field distribution and improving voltage resistance; when the grid electrode is conducted in the forward direction, the grid electrode is heightened, the potential restores the 2DEG under the grid electrode, electrons start from the source electrode and pass through the channel 2DEG at the heterojunction, then enter the GaN buffer layer and the N-type highly-doped GaN layer through the pores between the P-type highly-doped GaN blocking layers, and finally reach the drain electrode. The anode of the Schottky diode is in short circuit with the source electrode of the transistor device, when the Schottky diode is in forward conduction, the source electrode is added with low potential, the drain electrode is added with high potential, and the Schottky diode is in a turn-off state; when the current flows reversely, the source electrode is increased in potential, the drain electrode is increased in potential, and the current flows in from the anode of the Schottky diode, passes through the GaN buffer layer and the N-type highly-doped GaN layer and then flows out from the drain electrode.

Claims (2)

1. A GaN power device integrated with a Schottky tube comprises a first conductive material (1), an N-type highly-doped GaN layer (2), a GaN buffer layer (3), a barrier layer (4) and a passivation layer (5) which are sequentially stacked from bottom to top along the vertical direction of the device; a P-type highly-doped GaN barrier layer (7) with pores is inserted into the GaN buffer layer (3), namely the P-type highly-doped GaN barrier layer (7) is in discontinuous symmetrical distribution along the transverse direction of the device; along the transverse direction of the device, the center of the device comprises a grid structure and a Schottky anode groove structure which are arranged in parallel along the longitudinal direction of the device, second conductive materials (6) are symmetrically distributed on two sides of the device, and a space is reserved between the second conductive materials (6) and the grid structure and between the second conductive materials and the Schottky anode groove structure;
defining the longitudinal direction to be a third dimension direction perpendicular to the transverse direction and the vertical direction;
a drain electrode is led out from the lower surface of the first conductive material (1);
the second conductive material (6) penetrates through the passivation layer (5) from top to bottom and is in contact with the barrier layer (4), the contact type is ohmic contact, and a source electrode is led out of the upper surface of the second conductive material (6);
the method is characterized in that:
the Schottky anode groove structure is composed of a dielectric material (8) and a third conductive material (9), sequentially penetrates through the passivation layer (5) and the barrier layer (4) from top to bottom, is in contact with the GaN buffer layer (3), is positioned right above a P-type highly-doped GaN barrier layer (7) hole, and is wider than the P-type highly-doped GaN barrier layer (7) hole; the dielectric material (8) is positioned at the bottom and the side wall of the groove; the third conductive material (9) is embedded in the dielectric material (8) at the bottom of the groove, the bottom of the third conductive material is in contact with the GaN buffer layer (3), the contact type is Schottky contact, and the anode of a Schottky diode is led out of the upper surface of the third conductive material (9) and is in short circuit with the source electrode;
the grid structure comprises a P-type GaN layer (10), a dielectric material (12) and a fourth conductive material (11), the P-type GaN layer (10) penetrates through the passivation layer (5) and is in contact with the barrier layer (4), and the dielectric material (12) covers the top of the P-type GaN layer (10) and the front side wall and the rear side wall of the semiconductor along the longitudinal direction; the fourth conductive material (11) covers the dielectric material (12);
and a grid is led out from the upper surface of the fourth conductive material (11).
2. The enhancement mode GaN vertical electron transistor of the integrated Schottky tube according to claim 1, wherein the barrier layer (4) is made of one or a combination of AlN, AlGaN, InGaN and InAlN.
CN202110907784.6A 2021-08-09 2021-08-09 GaN power device integrated with Schottky tube Active CN113611742B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114447101A (en) * 2022-01-24 2022-05-06 电子科技大学 Vertical GaN MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with freewheeling channel diode

Citations (4)

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Publication number Priority date Publication date Assignee Title
CN105118830A (en) * 2015-08-03 2015-12-02 电子科技大学 Enhanced HEMT of integrated SBD
CN107482059A (en) * 2017-08-02 2017-12-15 电子科技大学 A kind of GaN hetero-junctions longitudinal direction is inverse to lead FET
CN111312815A (en) * 2020-02-28 2020-06-19 中国科学院微电子研究所 GaN-based power transistor structure and preparation method thereof
US20210234030A1 (en) * 2019-03-27 2021-07-29 Southeast University Heterojunction semiconductor device having high blocking capability

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105118830A (en) * 2015-08-03 2015-12-02 电子科技大学 Enhanced HEMT of integrated SBD
CN107482059A (en) * 2017-08-02 2017-12-15 电子科技大学 A kind of GaN hetero-junctions longitudinal direction is inverse to lead FET
US20210234030A1 (en) * 2019-03-27 2021-07-29 Southeast University Heterojunction semiconductor device having high blocking capability
CN111312815A (en) * 2020-02-28 2020-06-19 中国科学院微电子研究所 GaN-based power transistor structure and preparation method thereof

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
LI ZHANG，ET. AL.: "p -GaN Gate Power Transistor With Distributed Built-in Schottky Barrier Diode for Low-loss Reverse Conduction" *
RUOPU ZHU， ET. AL.: "A split gate vertical GaN power transistor with intrinsic reverse conduction capability and low gate charge" *
TAO SUN，ET. AL.: "Vertical GaN Power Transistor with Embedded Fin-shaped Diode for High Performance Power Conversion" *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114447101A (en) * 2022-01-24 2022-05-06 电子科技大学 Vertical GaN MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with freewheeling channel diode
CN114447101B (en) * 2022-01-24 2023-04-25 电子科技大学 Vertical GaN MOSFET integrated with freewheeling channel diode

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