CN116384324B - Power module and bonding wire material determination method thereof - Google Patents
Power module and bonding wire material determination method thereof Download PDFInfo
- Publication number
- CN116384324B CN116384324B CN202310652036.7A CN202310652036A CN116384324B CN 116384324 B CN116384324 B CN 116384324B CN 202310652036 A CN202310652036 A CN 202310652036A CN 116384324 B CN116384324 B CN 116384324B
- Authority
- CN
- China
- Prior art keywords
- bonding wire
- bonding
- section
- power module
- igbt chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000463 material Substances 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000010949 copper Substances 0.000 claims abstract description 69
- 229910052802 copper Inorganic materials 0.000 claims abstract description 69
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 61
- 238000004088 simulation Methods 0.000 claims abstract description 37
- 238000004806 packaging method and process Methods 0.000 claims abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 19
- 238000005259 measurement Methods 0.000 claims description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 239000010410 layer Substances 0.000 description 63
- 230000004048 modification Effects 0.000 description 12
- 238000012986 modification Methods 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 11
- 239000000758 substrate Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 7
- 238000012546 transfer Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
- G06F30/3953—Routing detailed
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
- G01B21/32—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring the deformation in a solid
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
- G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/02—System on chip [SoC] design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/14—Force analysis or force optimisation, e.g. static or dynamic forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Wire Bonding (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The application provides a power module and a bonding wire material determining method. The packaging structure of the power module is provided with an IGBT chip and an upper copper layer, wherein the IGBT chip and the upper copper layer are connected with each other through K bonding wires, m bonding wires are made of a first material, other K-m bonding wires are made of a second material, and the mechanical strength of the first material is greater than that of the second material; m is the number of bonding wires meeting the first condition; the K bonding wires are made of a second material in simulation; the first condition is: the maximum plastic strain value of the bonding wire measuring position in the preset running time is larger than or equal to the preset strain value; or m is a preset value, and m is the number of bonding wires meeting a second condition; the second condition is: the maximum plastic strain value of the bonding wire measuring position in the preset running time is positioned in the top m in the rank from large to small of the maximum plastic strain value corresponding to each bonding wire.
Description
Technical Field
The application relates to the related technical field of semiconductor power device packaging, in particular to an IGBT power module using a bonding wire.
Background
Bonding wires are mainly applied to connection between electrode parts of semiconductor devices such as transistors and integrated circuits or between chips and external leads, and wire bonding is one of the main ways of realizing electrical interconnection inside IGBT power devices.
For the power module, the connection between the IGBT chip and the upper copper layer is realized through a plurality of bonding wires which are arranged in parallel. The bonding wire of the current power device generally adopts an aluminum bonding wire, and the copper wire bonding is a bonding technology for replacing aluminum bonding because the aluminum bonding wire is easy to fail and fall off or break in the use process. The copper bonding wire has excellent performances in mechanical and electrical aspects, but the hardness of the copper bonding wire is high, so that the bonding difficulty is increased, bonding can be successfully realized by improving bonding strength and ultrasonic energy in bonding, and if the bonding strength and the ultrasonic energy are too high, the silicon substrate below the bonding pad is easily damaged. Of course, the above-mentioned problems in copper bonding can also be solved by adding a protective layer (the material is typically titanium tungsten). It is apparent that copper bond wires are far more costly to process than aluminum bond wires. If copper bonding wires are adopted in the connection between the IGBT chip and the upper copper layer, the manufacturing cost and the manufacturing time are obviously increased, and the production efficiency is lower.
Disclosure of Invention
The application aims to solve the problem that an aluminum bonding wire is easy to break when the aluminum bonding wire is adopted between an IGBT chip and an upper copper layer of a power module.
In order to solve the technical problems, the application adopts the following technical scheme: the utility model provides a power module, power module's packaging structure has IGBT chip, is located the upper copper layer of IGBT chip below, connect each other through K bonding lines between IGBT chip and the upper copper layer that corresponds, among the K bonding lines, m bonding lines are first material, and other K-m bonding lines are the second material, the mechanical strength of first material is greater than the mechanical strength of second material, and m, K-m are all greater than 0.
Wherein: m is the number of bonding wires satisfying the first condition (i.e., the m bonding wires are m bonding wires satisfying the first condition); the first condition is: the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is larger than or equal to the preset strain value; or, m is a preset value, m is the number of bonding wires meeting the second condition (i.e. the m bonding wires are m bonding wires meeting the second condition); the second condition is: and the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is positioned in the top m in the rank from large to small of the maximum plastic strain value corresponding to each bonding wire.
Applicants have found that the chip surface is not an equithermal surface, there is a temperature difference, the temperature at the gate electrode welds on the chip is typically lower, and the temperature at the passive regions at the chip edge is lower, and the active regions contain a greater number of cells. The temperature difference on the surface of the chip causes different stress borne by each bonding wire, the higher the temperature is, the larger the stress borne by the bonding wires is, the bonding wires with large stress can be broken or fall off firstly along with continuous operation of the module, the breaking and falling off of a certain bonding wire can lead to the increase of the stress of other bonding wires, and the bonding wires can further accelerate failure. In the application, the maximum plastic strain value of the measuring position of each bonding wire in the preset running time is obtained. Comparing the maximum plastic strain value of each bonding wire with a preset strain value, namely, the bonding wires meeting the first condition adopt a first material with larger mechanical strength, and the other bonding wires adopt a second material; or selecting m bonding wires with the highest plastic strain value ranking at the top, namely adopting a first material with larger mechanical strength as the first m bonding wires, and adopting a second material as the other bonding wires. Through the arrangement, the application detects the plastic strain of the bonding wires, judges which bonding wires are easy to fall off according to the plastic strain value, and adopts the first material with larger mechanical strength, and other materials adopt the second material, so that the two materials are mixed and used in the connection of the chip and the upper copper layer, the reliability of the bonding wires is improved, and the cost is saved.
In the above technical solution, m is the number of bonding wires satisfying the first condition, and m is the number of bonding wires satisfying the first condition in the simulation of the power module; in the simulation, the K bonding wires are made of a second material; or, m is the number of bonding wires meeting the second condition, and m is the number of bonding wires meeting the second condition in the simulation of the power module; in the simulation, the K bonding wires are made of a second material.
In the further scheme, the maximum plastic strain value of the measurement position of each bonding wire in the preset operation time is obtained by simulation.
In the above technical scheme, the first material is copper, and the second material is aluminum.
In the above technical scheme, the measurement position of the bonding wire is the bonding wire heel position on the upper surface of the IGBT chip.
The applicant finds that the position of the bonding wire heel is most likely to break, the temperature of the bonding wire is increased after the chip is turned on and no current flows through the bonding wire after the chip is turned off in one period, the temperature of the bonding wire is reduced, and in the turn-on and turn-off process, the bonding wire heel is expanded with heat and contracted with cold, and is the fixed end, so that the bonding wire heel bears the maximum stress, and the heel is taken as the measuring position.
In the above technical scheme, the bonding wire comprises a first arched section, a first extension section and a second arched section which are sequentially connected; the two ends of the first arch section and the two ends of the second arch section form heel feet of the bonding wire, and the height of the second arch section is larger than that of the first arch section.
The first extension section both ends correspond respectively with first arch section one end, second arch section one end is connected, first arch section one end, the other end and second arch section one end all is located the upper surface of IGBT chip, first extension section extends at the IGBT chip upper surface, the second arch section other end is located the upper surface of copper layer.
The measuring position of the bonding wire is one end of the second arch section, or the measuring position of the bonding wire is one end of the first arch section and one end of the second arch section.
In the application, each bonding wire comprises a first arch section, a first extension section and a second arch section which are sequentially connected, and one end of the first arch section, the other end of the first arch section and one end of the second arch section are all positioned on the upper surface of the IGBT chip, so that the chip has a plurality of electric interfaces to realize redundancy, the connection between the chip and an upper copper layer is not influenced even if a certain heel is broken, the supporting area of the bonding wire is increased, and the setting of the bonding wire is more stable. The applicant has found that the end of the second arch-shaped segment, which is connected to the upper copper layer and is higher in height, is generally more prone to fracture than the end of the first arch-shaped segment, and therefore the end of the second arch-shaped segment (i.e. the heel) can be used as a measurement location. Of course, the first arch segment end and the second arch segment end can be used as the measurement positions of a bonding wire, that is, the maximum value of the plastic strain value of the first arch segment end in the preset operation time and the plastic strain value of the second arch segment end in the preset operation time is the maximum plastic strain value of the measurement position of the bonding wire in the preset operation time, so that the plastic strain condition of the bonding wire can be more comprehensively known.
In the technical scheme, the preset operation time corresponds to p switching periods of the IGBT chip, and p is more than or equal to 1.
The application also provides a bonding wire material determining method of the power module, the packaging structure of the power module is provided with an IGBT chip and an upper copper layer positioned below the IGBT chip, the power module is provided with K bonding wires for connecting the IGBT chip and the upper copper layer, and m and K-m are both larger than 0.
The bonding wire material determining method comprises the following steps:
A. simulating the power module to obtain the maximum plastic strain value of the measurement position of each bonding wire in the preset operation time; in the simulation, the K bonding wires are made of a second material.
B. If the ith bonding wire meets the first condition/the second condition in the simulation, determining the material of the ith bonding wire as a first material; otherwise, the material of the ith bonding wire is determined to be a second material.
Wherein:
the number of bonding wires meeting the first condition/the second condition in the K bonding wires is m, and m and K-m are both larger than 0; the first material has a mechanical strength greater than the mechanical strength of the second material.
The first condition is: and the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is larger than or equal to the preset strain value.
The second condition is: and the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is positioned in the top m of the ranking from large to small of the maximum plastic strain value corresponding to each bonding wire, and m is a preset value.
In the above technical scheme, the first material is copper, and the second material is aluminum.
In the above technical scheme, the measurement position of the bonding wire is the bonding wire heel position on the upper surface of the IGBT chip.
In the technical scheme, the preset operation time corresponds to p switching periods of the IGBT chip, and p is more than or equal to 1.
In the above technical scheme, the bonding wire comprises a first arched section, a first extension section and a second arched section which are sequentially connected; the two ends of the first arch section and the two ends of the second arch section form heel feet of the bonding wire, and the height of the second arch section is larger than that of the first arch section.
The first extension section both ends correspond respectively with first arch section one end, second arch section one end is connected, first arch section one end, the other end and second arch section one end all is located the upper surface of IGBT chip, first extension section extends at the IGBT chip upper surface, the second arch section other end is located the upper surface of copper layer.
The measuring position of the bonding wire is one end of the second arch section, or the measuring position of the bonding wire is one end of the first arch section and one end of the second arch section.
The application has the advantages and positive effects that: the application adopts the mode of mixing bonding wires of two materials to connect the copper layer on the DBC board with the chip, so that the power module has good reliability, good packaging quality and reduced cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
Fig. 1 is a schematic top view of the internal structure of a power module according to the present application.
Fig. 2 is a schematic perspective view of the EA portion of fig. 1.
Fig. 3 is a cross-sectional view of the package structure of fig. 1 including one IGBT chip.
Fig. 4 is an enlarged schematic view of a portion of the EB structure of fig. 3.
Fig. 5 is a schematic diagram of plastic strain of the first bond wire during a switching cycle prior to modification.
Fig. 6 is a schematic diagram of the plastic strain of the second bond wire during a switching cycle prior to modification.
Fig. 7 is a schematic diagram of plastic strain of the third bond wire during a switching cycle prior to modification.
Fig. 8 is a schematic diagram of plastic strain of the fourth bond wire during a switching cycle prior to modification.
Fig. 9 is a schematic diagram of the plastic strain of the fifth bond wire during a switching cycle prior to modification.
Fig. 10 is a schematic diagram of plastic strain of the first bond wire during a switching cycle after modification.
Fig. 11 is a schematic diagram of the plastic strain of the second bonding wire during a switching cycle after modification.
Fig. 12 is a schematic diagram of plastic strain of the third bonding wire during a switching cycle after modification.
Fig. 13 is a schematic diagram of plastic strain of the fourth bond wire during a switching cycle after modification.
Fig. 14 is a schematic diagram showing the plastic strain of the fifth bonding wire in one switching cycle after modification.
In the above figures: 1. a first wire bond; 2. a second wire bond; 3. a third bond wire; 4. a fourth bond wire; 5. a fifth bond wire; 10. an IGBT chip; 20. a diode; 101. a chip solder layer; 102. a copper layer is arranged on the substrate; 103. a ceramic layer; 104. a lower copper layer; 105. a substrate solder layer; 106. a substrate layer; 107. a housing; 1071. a terminal; 11. a first arcuate segment; 12. a second arcuate segment; 13. a first extension; 14. and a second extension.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
As shown in fig. 1-4, the application discloses an IGBT power module in which copper-aluminum bonding wires on a chip are mixed. The application is different from the traditional structure that each bonding wire is an aluminum bonding wire, and the copper bonding wire and the aluminum bonding wire are used together.
The packaging structure of the power module is provided with an IGBT chip 10 and an upper copper layer 102 positioned below the IGBT chip 10, wherein the IGBT chip 10 and the corresponding upper copper layer 102 are connected with each other through K bonding wires. In the application, the power module is of a structure of two IGBT chips connected in series and comprises two subunits. Each subunit electrical portion is an IGBT chip. Each IGBT chip is connected with the upper copper layer through five bonding wires.
The outermost layer of the module is a protective shell 107 (which can be made of plastic); the shell 107 is filled with silica gel with dustproof, shockproof, insulating and heat-insulating functions; the housing has terminals 1071 for connection to the internal and external circuitry of the module; the terminal 1071 is connected to the IGBT chip 10 through the upper copper layer 102 and bonding wires (i.e. the first bonding wire 1, the second bonding wire 2, the third bonding wire 3, the fourth bonding wire 4, the fifth bonding wire 5). The IGBT power module is stacked from various components. A chip solder layer 101 is arranged below the IGBT chip 10, the lower surface of the chip solder layer 101 is connected with an upper copper layer 102, a ceramic layer 103 is arranged below the upper copper layer 102, the lower surface of the ceramic layer 103 is connected with a lower copper layer 104, and a substrate solder layer 105 is arranged below the lower copper layer 104; a heat-dissipating copper bottom plate (i.e., substrate layer 106) is disposed under substrate solder layer 105, i.e., the surface area of the upper surface of substrate layer 106 is greater than the surface area of the lower surface of substrate solder layer 105. Wherein the upper copper layer 102, the ceramic layer 103 and the lower copper layer 104 form a DBC structure.
And among the K bonding wires, m bonding wires are made of a first material, the other K-m bonding wires are made of a second material, the mechanical strength of the first material is greater than that of the second material, and m and K-m are both greater than 0. In this embodiment, k=5 and m=2, i.e. 3 bonding wires and 2 copper bonding wires are used.
In one scheme, m is the number of bonding wires meeting a first condition in the simulation of the power module; in the simulation, the K bonding wires are made of a second material; the first condition is: and the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is larger than or equal to the preset strain value.
In another scheme, m is a preset value, and m is the number of bonding wires meeting a second condition in the simulation of the power module; in the simulation, the K bonding wires are made of a second material; the second condition is: and the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is positioned in the top m in the rank from large to small of the maximum plastic strain value corresponding to each bonding wire.
The first material is copper and the second material is aluminum.
The measurement position of the bonding wire is the position of the heel of the bonding wire on the upper surface of the igbts chip 10.
As shown in fig. 2-4, the bonding wire comprises a first arched section 11, a first extension section 13 and a second arched section 12 which are sequentially connected; the two ends of the first arch-shaped section 11 and the two ends of the second arch-shaped section 12 form heel feet of the bonding wire, and the top end of the second arch-shaped section 12 is higher than the top end of the first arch-shaped section 11.
The two ends of the first extension section 13 are respectively connected with one end of the first arch section 11 and one end of the second arch section 12 correspondingly, one end of the first arch section 11, the other end of the first arch section and one end of the second arch section 12 are all positioned on the upper surface of the IGBT chip 10, the first extension section 13 extends on the upper surface of the IGBT chip 10, and the other end of the second arch section 12 is positioned on the upper surface of the upper copper layer 102; the measurement position of the bonding wire is one end of the second arched section 12, or the measurement position of the bonding wire is one end of the first arched section 11 and one end of the second arched section 12.
The heel is the root of the arched section of the bonding wire, which is attached to the surface of the chip. As shown in fig. 4, the root pins P1 and P2 are root parts of the first arch segment 11, that is, the root pin P1 is the junction between the first arch segment 11 and the second extension segment 14 extending on the upper surface of the chip, and the root pin P2 is the junction between the first arch segment 11 and the first extension segment 13 extending on the upper surface of the chip. The root P3 is the junction of the second arch segment 12 and the first extension segment 13.
The preset operation time corresponds to p switching periods of the IGBT chip, and p is more than or equal to 1.
The application also provides a bonding wire material determining method of the power module, the packaging structure of the power module is provided with the IGBT chip 10 and the upper copper layer 102 positioned below the IGBT chip 10, the power module is provided with K bonding wires for connecting the IGBT chip 10 and the upper copper layer 102, and m and K-m are both larger than 0.
The bonding wire material determining method comprises the following steps:
A. simulating the power module to obtain the maximum plastic strain value of the measurement position of each bonding wire in the preset operation time; in the simulation, the K bonding wires are made of a second material.
B. If the ith bonding wire meets the first condition/the second condition in the simulation, determining the material of the ith bonding wire as a first material; otherwise, the material of the ith bonding wire is determined to be a second material.
Wherein:
and the number of bonding wires meeting the first condition/the second condition in the K bonding wires is m, and m and K-m are both larger than 0.
The first material has a mechanical strength greater than the mechanical strength of the second material.
The first condition is: and the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is larger than or equal to the preset strain value.
The second condition is: and the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is positioned in the top m of the ranking from large to small of the maximum plastic strain value corresponding to each bonding wire, and m is a preset value.
This scheme is described in further detail below.
The simulation of the present application can be performed in finite elements. In the simulation, the convection coefficient of the chip surface was set to 10W/(m) 2 K). The power module bottom (i.e., below the substrate layer 106) defines 5000W/(m) at turn-off 2 The convection coefficient of K) is set to 10W/(m) to simulate the accelerated cooling in the turn-off process, and the convection coefficient of the other surfaces (including the surfaces of the chip solder layer, the substrate solder layer, the upper copper layer, the lower copper layer and the ceramic layer) 2 K). According to experiments, the loss power of the single IGBT chip is 15W in the normal working state of the power module, so that the loss power during the on period of the single IGBT chip is set to be 15W in a simulation mode. No power is generated during the turn-off of the IGBT chip. The on time is set to 4s and the off time is set to 6s.
In the simulation, some specific parameters used are: each bonding wire is made of aluminum and has the density of 2700kg/m 3 The heat transfer coefficient was 237W/(m.K). The copper bonding wire is made of copper and has the density of 8960kg/m 3 The heat transfer coefficient was 401W/(m.K). IGBT chip material is silicon, density is 2329kg/m 3 The heat transfer coefficient was 149W/(m.K). The solder layer material is 96.5Sn3.5Ag, and the density is 7400kg/m 3 The heat transfer coefficient was 78W/(m.K). The upper copper layer, the lower copper layer and the copper bottom plate are made of copper, and the density is 8960kg/m 3 The heat transfer coefficient was 401W/(m.K). The ceramic layer material is Al 2 O 3 Density of 3700kg/m 3 The heat transfer coefficient was 35W/(m.K).
When the bonding wire model is constructed in simulation, the angle of the bonding wire is set to be in conformity with the reality. Since the bonding wire has a certain hardness, the actual shape of the bonding wire can be simulated in a simulation according to the shape (e.g., curvature or bending angle) of the actual bonding wire in an actual state. For example, a bonding wire image may be acquired by image acquisition, and bonding wire shape may be extracted. If the curve is the curve, the actual curvature can be obtained, or the integral shape of the bonding wire can be obtained by connecting a plurality of straight line segments, so that the simulated bonding wire model is consistent with the actual situation.
The simulation of the application is different from the prior art in that the construction of a bonding wire model is added in the simulation, and the plastic strain of the heel position is measured. The other contents in the simulation are the contents of the prior art.
In the application, after the turn-on and turn-off period of the IGBT chip is finished, the plastic strain of the heel of each bonding wire is extracted.
In the application, five bonding wires are all aluminum wires in simulation. Since the positions of the bonding wire heel are subjected to the maximum stress, after the simulation is performed for one breaking period, the plastic strains of the five bonding wire heel parts (the positions of the root feet of the bonding wires, corresponding to the bonding wires in fig. 2 and pointed by arrows) are respectively extracted, simulation results of the bonding wires are respectively shown in fig. 5-9, the maximum plastic strains of the bonding wires in the simulation time are obtained, and the maximum plastic strains of the bonding wires are compared. From fig. 5-9, it can be seen that the maximum plastic strain (0.029333 mm/mm) of the third bond wire is the maximum of the individual bond wires, while the maximum plastic strain (0.028512 mm/mm) of the second bond wire is ranked second.
The K bonding wires are made of a second material before improvement of the scheme, and the obtained plastic strain values of the measurement positions of the bonding wires in the preset operation time are obtained. In the figures 5-9, 0-10s is 1 switching cycle (including on and off processes).
In one implementation of this embodiment, the preset strain value may be set empirically, for example, in this embodiment, the preset strain value is set to 0.025mm/mm, and then for five bonding wires connected to the upper copper layer of the IGBT chip, copper wires should be used for the second bonding wire 2 and the third bonding wire 3, and aluminum wires may be used for other bonding wires.
In another implementation of this embodiment, the m value may also be preset to 2. After ranking the maximum plastic strain values of the bonding wires, the maximum strain value of the second bonding wire 2 and the maximum strain value of the third bonding wire 3 are ranked two times, so that for five bonding wires connected with the upper copper layer of the IGBT chip, copper wires are adopted for the second bonding wire 2 and the third bonding wire 3, and aluminum wires can be adopted for other bonding wires.
In order to verify the actual effect, in the simulation, the second bonding wire 2 and the third bonding wire 3 are copper wires, and the other bonding wires are aluminum wires, and simulation is performed (i.e. after the scheme is improved), so that simulation results of the bonding wires are respectively shown in fig. 10-14. As can be seen from fig. 10-14, the maximum plastic strain at the heel of the five bond wires at this time is 0.02522mm/mm. Comparing the simulation results of fig. 5-9 and the simulation results of fig. 10-14, it can be seen that the scheme of the application changes the maximum plastic strain from 0.029333mm/mm to 0.02522mm/mm, and the maximum plastic strain is reduced by 14%, thereby obviously reducing the breaking risk of the bonding wire and improving the connection reliability of the IGBT chip and the upper copper layer. The maximum plastic strain value of each bonding wire between the chip and the upper copper layer is obviously reduced, so that the falling time of the bonding wire which falls off first is obviously prolonged, and the service life of the bonding wire is prolonged.
In addition, two IGBT chips in the power module are symmetrically arranged, so that the material of each bonding wire between one IGBT chip and the upper copper layer can be determined according to the symmetrical relation only by analyzing the bonding wire between the other IGBT chip and the upper copper layer. In addition, the power module is further provided with a diode 20 (in fig. 3, only an IGBT chip is illustrated, a diode provided on the upper copper layer 102 by a diode solder layer is omitted, and the ceramic layer 103 is omitted), and although the diode is also connected to the upper copper layer by a plurality of bonding wires, the bonding wires connected to the diode are empirically low in temperature, and the bonding wires on the diode are small in deformation amount so as not to fail, so that all the bonding wires of the diode can still use aluminum wires.
Compared with the prior art which adopts the copper bonding wire, the copper wire is reduced, so that the IGBT power module has good reliability, good packaging quality and reduced cost, namely, balance consideration is realized on the packaging quality and the cost.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The foregoing describes the embodiments of the present application in detail, but the description is only a preferred embodiment of the present application and should not be construed as limiting the scope of the application. All equivalent changes and modifications within the scope of the present application are intended to be covered by the present application. Modifications of the application which are equivalent to various embodiments of the application will occur to those skilled in the art upon reading the application, and are within the scope of the application as defined in the appended claims. Embodiments of the application and features of the embodiments may be combined with each other without conflict.
Claims (9)
1. The utility model provides a power module, power module's packaging structure has IGBT chip (10), is located upper copper layer (102) of IGBT chip (10) below, connect each other through K bonding lines between IGBT chip (10) and the upper copper layer (102) that correspond, its characterized in that: among the K bonding wires, m bonding wires are made of a first material, the other K-m bonding wires are made of a second material, the mechanical strength of the first material is greater than that of the second material, and m and K-m are both greater than 0;
wherein:
m is the number of bonding wires meeting the first condition when K bonding wires are arranged in the simulation of the power module and all adopt the second material; the first condition is: the maximum plastic strain value of the measuring position of the bonding wire in the preset running time of the power module is larger than or equal to the preset strain value; or alternatively
m is a preset value, and m is the number of bonding wires meeting a second condition when K bonding wires are all made of a second material in the simulation of the power module; the second condition is: and the maximum plastic strain value of the measuring position of the bonding wire in the preset running time of the power module is positioned in the top m in the ranking from large to small of the maximum plastic strain value corresponding to each bonding wire.
2. The power module of claim 1, wherein: the measurement position of the bonding wire is the position of a bonding wire heel positioned on the upper surface of the IGBT chip (10).
3. The power module of claim 2, wherein: the bonding wire comprises a first arched section (11), a first extension section (13) and a second arched section (12) which are connected in sequence; the two ends of the first arch section (11) and the two ends of the second arch section (12) form heel feet of the bonding wire, and the height of the second arch section (12) is larger than that of the first arch section (11);
the two ends of the first extension section (13) are respectively connected with one end of the first arch section (11) and one end of the second arch section (12) correspondingly, one end of the first arch section (11), the other end of the first arch section and one end of the second arch section (12) are both positioned on the upper surface of the IGBT chip (10), the first extension section (13) extends on the upper surface of the IGBT chip (10), and the other end of the second arch section (12) is positioned on the upper surface of the upper copper layer (102);
the measuring position of the bonding wire is one end of the second arched section (12), or the measuring position of the bonding wire is one end of the first arched section (11) and one end of the second arched section (12).
4. The power module of claim 1, wherein: the first material is copper and the second material is aluminum.
5. The utility model provides a bonding wire material determination method of power module, power module's packaging structure has IGBT chip (10), is located upper copper layer (102) of IGBT chip (10) below, power module has K bonding wires that are used for connecting IGBT chip (10) and upper copper layer (102), its characterized in that:
the bonding wire material determining method comprises the following steps:
A. simulating the power module to obtain the maximum plastic strain value of the measurement position of each bonding wire in the preset operation time;
in the simulation, the K bonding wires are made of a second material;
B. if the ith bonding wire meets the first condition/the second condition in the simulation, determining the material of the ith bonding wire as a first material; otherwise, determining the material of the ith bonding wire as a second material;
wherein:
m is the number of bonding wires meeting a first condition/a second condition in the simulation of the power module, and m and K-m are both larger than 0;
the first material has a mechanical strength greater than the mechanical strength of the second material;
the first condition is: the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is larger than or equal to the preset strain value;
the second condition is: and the maximum plastic strain value of the measuring position of the bonding wire in the preset running time is positioned in the top m of the ranking from large to small of the maximum plastic strain value corresponding to each bonding wire, and m is a preset value.
6. The bonding wire material determination method according to claim 5, wherein: the first material is copper and the second material is aluminum.
7. The bonding wire material determination method according to claim 5, wherein: the measurement position of the bonding wire is the position of a bonding wire heel positioned on the upper surface of the IGBT chip (10).
8. The bonding wire material determination method according to claim 5, wherein: the preset operation time corresponds to p switching periods of the IGBT chip, and p is more than or equal to 1.
9. The bonding wire material determination method according to claim 5, wherein: the bonding wire comprises a first arched section (11), a first extension section (13) and a second arched section (12) which are connected in sequence; the two ends of the first arch section (11) and the two ends of the second arch section (12) form heel feet of the bonding wire, and the height of the second arch section (12) is larger than that of the first arch section (11);
the two ends of the first extension section (13) are respectively connected with one end of the first arch section (11) and one end of the second arch section (12) correspondingly, one end of the first arch section (11), the other end of the first arch section and one end of the second arch section (12) are both positioned on the upper surface of the IGBT chip (10), the first extension section (13) extends on the upper surface of the IGBT chip (10), and the other end of the second arch section (12) is positioned on the upper surface of the upper copper layer (102);
the measuring position of the bonding wire is one end of the second arched section (12), or the measuring position of the bonding wire is one end of the first arched section (11) and one end of the second arched section (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310652036.7A CN116384324B (en) | 2023-06-05 | 2023-06-05 | Power module and bonding wire material determination method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310652036.7A CN116384324B (en) | 2023-06-05 | 2023-06-05 | Power module and bonding wire material determination method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116384324A CN116384324A (en) | 2023-07-04 |
| CN116384324B true CN116384324B (en) | 2023-10-31 |
Family
ID=86969773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310652036.7A Active CN116384324B (en) | 2023-06-05 | 2023-06-05 | Power module and bonding wire material determination method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116384324B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8381155B1 (en) * | 2011-10-03 | 2013-02-19 | The Regents Of The University Of Michigan | Vertical interconnect patterns in multi-layer integrated circuits |
| EP2662891A1 (en) * | 2012-05-07 | 2013-11-13 | Heraeus Materials Technology GmbH & Co. KG | Aluminium coated copper bond wire and method of making the same |
| CN111519227A (en) * | 2020-03-30 | 2020-08-11 | 安徽广宇电子材料有限公司 | Anti-oxidation treatment equipment of copper wire material for bonding wire preparation |
| CN112560328A (en) * | 2020-11-18 | 2021-03-26 | 电子科技大学 | IGBT bonding lead fault diagnosis method based on surface micro-strain signal |
| CN112597678A (en) * | 2020-12-15 | 2021-04-02 | 重庆大学 | Numerical simulation method for fretting wear failure evolution of crimping type IGBT device |
| CN113176738A (en) * | 2021-03-23 | 2021-07-27 | 首钢集团有限公司 | Method and apparatus for controlling press formability |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102009045184B4 (en) * | 2009-09-30 | 2019-03-14 | Infineon Technologies Ag | Bond connection between a bonding wire and a power semiconductor chip |
| TWI569396B (en) * | 2014-12-08 | 2017-02-01 | 財團法人工業技術研究院 | Chip structure having bonding wire |
| US20190287943A1 (en) * | 2015-08-31 | 2019-09-19 | Delta Electronics (Shanghai) Co., Ltd | Power package module of multiple power chips and method of manufacturing power chip unit |
-
2023
- 2023-06-05 CN CN202310652036.7A patent/CN116384324B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8381155B1 (en) * | 2011-10-03 | 2013-02-19 | The Regents Of The University Of Michigan | Vertical interconnect patterns in multi-layer integrated circuits |
| EP2662891A1 (en) * | 2012-05-07 | 2013-11-13 | Heraeus Materials Technology GmbH & Co. KG | Aluminium coated copper bond wire and method of making the same |
| CN111519227A (en) * | 2020-03-30 | 2020-08-11 | 安徽广宇电子材料有限公司 | Anti-oxidation treatment equipment of copper wire material for bonding wire preparation |
| CN112560328A (en) * | 2020-11-18 | 2021-03-26 | 电子科技大学 | IGBT bonding lead fault diagnosis method based on surface micro-strain signal |
| CN112597678A (en) * | 2020-12-15 | 2021-04-02 | 重庆大学 | Numerical simulation method for fretting wear failure evolution of crimping type IGBT device |
| CN113176738A (en) * | 2021-03-23 | 2021-07-27 | 首钢集团有限公司 | Method and apparatus for controlling press formability |
Non-Patent Citations (3)
| Title |
|---|
| IGBT模块材料选型的仿真研究;喻磊;肖标;黄安迪;余雪萍;胡洋;;南方电网技术(第05期);全文 * |
| IGBT模块键合损伤机理、演化规律及状态监测;姚芳;马静;唐圣学;丁祥宽;;仪器仪表学报(第04期);全文 * |
| IGBT模块键合线失效研究;周文栋;王学梅;张波;赖伟;;电源学报(第01期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116384324A (en) | 2023-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Calata et al. | Three-dimensional packaging for power semiconductor devices and modules | |
| US6563211B2 (en) | Semiconductor device for controlling electricity | |
| EP2963684B1 (en) | Power semiconductor device | |
| US9455207B2 (en) | All-in-one power semiconductor module | |
| US7605456B2 (en) | Inverter unit | |
| CN105932016A (en) | Dynamic and static current-sharing and multi-chip paralleled power module | |
| TW200529406A (en) | Semiconductor apparatus | |
| KR20140066090A (en) | Power semiconductor module and method of manufacturing the same | |
| US8860220B2 (en) | Semiconductor device and method for manufacturing the same | |
| CN110010596B (en) | Packaging structure for multi-chip parallel power module | |
| CN108172617A (en) | A kind of circle large scale igbt chip crimping encapsulating structure and manufacturing method | |
| JP2009213269A (en) | Power conversion apparatus | |
| CN106611749A (en) | Semiconductor device | |
| CN201773840U (en) | IGBT (insulated-gate bipolar transistor) power module without bonding wires | |
| CN116384324B (en) | Power module and bonding wire material determination method thereof | |
| JP2002368192A (en) | Semiconductor device | |
| Chi et al. | High reliability wire-less power module structure | |
| CN113035787B (en) | Reverse conducting type power semiconductor module packaging structure and packaging method thereof | |
| JPWO2019216160A1 (en) | Power semiconductor devices, their manufacturing methods, and power converters | |
| JP2006066704A (en) | Semiconductor device | |
| JP7479771B2 (en) | Semiconductor device, manufacturing method thereof, and power conversion device | |
| JPH06302639A (en) | Power semiconductor device | |
| CN109003952A (en) | A kind of inverter IGBT encapsulating structure of standing balance | |
| JP2005310844A (en) | Power semiconductor module | |
| CN209216957U (en) | A kind of power device lead frame |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |