CN116364681B - Induction chip packaging structure, process and semiconductor device - Google Patents
Induction chip packaging structure, process and semiconductor device Download PDFInfo
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- CN116364681B CN116364681B CN202310567944.6A CN202310567944A CN116364681B CN 116364681 B CN116364681 B CN 116364681B CN 202310567944 A CN202310567944 A CN 202310567944A CN 116364681 B CN116364681 B CN 116364681B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
Abstract
The application discloses an induction chip packaging structure, a process and a semiconductor device, which comprises a packaging body, wherein a bare chip and an RDL electrically connected with the bare chip are packaged in the packaging body, and the packaging body is also packaged with: the metal layer is plated with holes by etching the wrapping cover, the plated hole wall surface and the wrapping cover are electroplated, and the metal layer on the plated hole wall surface is exposed after being cut; the top bonding pad and the bottom bonding pad are respectively connected with the corresponding metal layers on the encapsulation surface so as to uniformly wrap the encapsulation body corresponding to the right-angle sides.
Description
Technical Field
The application belongs to the technical field of chip packaging, and particularly relates to an induction chip packaging structure, an induction chip packaging process and a semiconductor device.
Background
Along with the continuous progress of integrated circuit packaging technology, the integrated level of an integrated circuit is improved, the functions are also more and more enriched, the semiconductor packaging refers to a process of processing a wafer passing through a test according to the shape and the function requirements of a product to obtain an independent chip, the manufacturing flow of the chip is divided according to an industrial chain, and the core links mainly comprise four parts: IC design, chip manufacture, chip packaging and finished product test, wherein the chip packaging and finished product test, our country is expected to rise up by virtue of resource advantage, the improvement of packaging technology, can control the chip yield effectively, the chip packaging (Package) is the process of assembling the integrated circuit into the final product of the chip, namely the integrated circuit Die (Die) produced by the wafer foundry, namely the wafer from the wafer front process is cut into small wafers after dicing process, put on a substrate with bearing function, lead out the pipe feet, then fixedly Package into a whole, the packaging means that the circuit pins on the silicon chip are led to the external joint by leads or circuits so as to facilitate the connection of other devices, and the chip packaging is that the chip must be isolated from the outside in order to prevent the corrosion of impurities in the air to the chip circuit; the packaged chip is more convenient to install and transport, plays roles in installing, fixing, sealing, protecting the chip, enhancing electric heating performance and the like, and is connected to pins of the packaging shell through leads or circuits on the chip, and the pins are connected with other devices through leads on a printed circuit board, so that the connection between the internal chip and an external circuit is realized.
In many chip types, such as electromagnetic induction, after the chip is packaged, the functional surface of the chip is also packaged in a plastic package material, the distance between the chip and the packaging edge directly influences the performance of the chip, when equipment to be sensed is close to the chip, a component with an antenna function generates induction current, the chip can activate a circuit in the chip by using the induction current and transmits data stored in the chip to the equipment to be sensed through an electromagnetic field, the smaller the distance between the chip and the packaging edge is, the more beneficial is, when the distance is larger, the thicker the plastic package material blocks induction signals, the induction performance of the chip is directly influenced, but the design of the conventional chip bonding pad is unreasonable, the structure is not stable enough, the mounting surface of the chip is fixed, the mounting flexibility of the chip is poor, and when the space of a welding plate is limited, the mounting surface cannot be correspondingly selected to reasonably use the space.
Disclosure of Invention
In order to solve the problems in the prior art, the application provides an induction chip packaging structure, an induction chip packaging process and a semiconductor device.
In order to achieve the above objective, the present application provides an induction chip package structure, which includes a package body, wherein a die and an RDL electrically connected with the die are encapsulated in the package body, and the package body is further encapsulated with:
the metal layer is plated with holes by etching the wrapping cover, the plated hole wall surface and the wrapping cover are electroplated, and the metal layer on the plated hole wall surface is exposed after being cut;
the top bonding pad and the bottom bonding pad are respectively connected with the corresponding metal layers on the encapsulation surface so as to uniformly wrap the corresponding right-angle sides of the encapsulation body;
the bottom pad is electrically connected with the RDL, and the bare chip is electrically transmitted from the RDL to the bottom pad.
Further, the plating hole is square, rectangular, semicircular or a combination of the two, and the thickness range of the metal layer electroplated on the inner wall of the plating hole and the encapsulation surface is more than or equal to 50 mu m, so that the integrity of the metal layer during cutting is ensured.
Further, the metal layer is ground after being encapsulated, the thickness of the metal layer is reduced by 10-40 mu m, and the metal layer is completely exposed, so that the bonding strength of the metal layer and the bonding pad is ensured.
Further, the package encapsulates at least one die, and the back of the die is coated with an insulating layer and then attached to a substrate for encapsulation to buffer stress.
Further, the metal layer, the top pad and the bottom pad are all formed by an electroplating process.
Further, the package body further comprises side pads, and the side pads are plated on the other two encapsulation surfaces of the package body at the same time of forming the bottom pads so as to enhance welding stability.
A semiconductor device comprises the induction chip packaging structure.
An induction chip packaging method comprises the following steps:
RDL encapsulation step: electroplating rewiring at the position of the exposed die interface electric connection convex block after encapsulation, and encapsulating the rewiring;
top and bottom bond pad formation steps: etching the wrapping cover to uniformly form plated holes, electroplating a metal layer on the wall surface of the plated holes and the wrapping surface, wrapping and grinding to expose the metal layer, electroplating a bonding pad connected with the metal layer, and wrapping the bonding pad; the bonding pads comprise a top bonding pad and a bottom bonding pad which are respectively formed on two opposite encapsulation surfaces of the packaging body, and are symmetrically arranged about packaging materials between the two encapsulation surfaces, and plated holes on the bottom surface are connected with the RDL so as to ensure the electrical transmission of the RDL and the bottom bonding pad;
the cutting is unit steps: the encapsulation material is ground on multiple sides and the top bonding pad and the bottom bonding pad are exposed, the encapsulation body is cut along a cutting line in a cutting line, the cutting line is positioned in the width range of the metal layer on the wall surface of the plated hole, so that the metal layer is cut, the welding feet of the right-angle side metal package of the encapsulation body are uniformly formed, and the electric property of the bare chip is transmitted to the bottom bonding pad through the convex blocks and the RDL.
Further, the RDL packaging step further includes providing a substrate, attaching at least one die with an electrical connection bump formed thereon to the substrate, packaging the die and bump, and grinding to expose the top surface of the bump.
Further, in the step of forming the top bonding pad and the bottom bonding pad, the shape of the plating hole is square, rectangle, semicircle or the combination of the two, and the thickness range of the metal layer electroplated on the inner wall of the plating hole and the encapsulation surface is more than or equal to 50 mu m so as to ensure the integrity of the metal layer during cutting.
Further, in the step of forming the top bonding pad and the bottom bonding pad, when the metal layer is exposed by encapsulation grinding, the metal layer is ground to be thinned by 10-40 mu m, and the metal layer is completely exposed so as to ensure the bonding strength of the metal layer and the bonding pad.
Further, in the step of forming the top bonding pad and the bottom bonding pad, the package substrate is removed, and the top bonding pad and the bottom bonding pad are respectively formed on two opposite encapsulation surfaces.
Further, the method also comprises a step of forming the side bonding pads, wherein the side bonding pads are also electroplated on the other two encapsulation surfaces of the package body at the same time of forming the bottom bonding pads, so that the welding stability is enhanced.
The application of the application: the mounting surface of the packaging structure can be correspondingly selected, the space of the welding plate is reasonably utilized, the mounting surface of the chip is variable, the mounting flexibility is good, the five surfaces of the packaging body are respectively provided with the welding pads, the welding points are more, the tin climbing observation is obvious, the welding effect is good, the metal layer is formed on the inner wall surface of the plating hole and the packaging surface in a drilling mode, the welding pads are plated on the end surface of the metal layer, the contact area between the metal layer and the packaging material is increased, the bonding force between the metal layer and the packaging material is enhanced, the welding pad structure is more stable, the process flow is simple, and the cost is lower.
Drawings
FIG. 1 is a longitudinal sectional view of an induction chip package structure according to the present application;
FIG. 2 is a cross-sectional view of an induction chip package structure according to the present application;
FIG. 3 is a top view of an induction chip package structure according to the present application;
FIG. 4 is a bottom view of an induction chip package structure according to the present application;
FIG. 5 is a block flow diagram of an induction chip packaging process according to the present application;
FIG. 6 is a schematic diagram illustrating an RDL encapsulation step of an induction chip packaging process according to the present application;
FIG. 7 is a schematic diagram of a top etching step of an induction chip packaging process according to the present application;
FIG. 8 is a schematic diagram of a top bonding pad encapsulation of an induction chip encapsulation process according to the present application;
FIG. 9 is a schematic diagram of a bottom etching step of an induction chip packaging process according to the present application;
FIG. 10 is a schematic diagram of a bottom pad package of an induction chip packaging process according to the present application;
FIG. 11 is a schematic diagram of a dicing unit of an induction chip packaging process according to the present application;
fig. 12 is a schematic diagram of a conventional pad structure.
The figure indicates: die 1, RDL2, bottom pad 3, side pads 4, top pad 5, package 6.
Detailed Description
The following description of the embodiments of the present application will be made more complete and less obvious to those skilled in the art, based on the embodiments of the present application, for a part, but not all of the embodiments of the present application, without making any creative effort.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must be specifically oriented, constructed and operated in the specific orientations, and thus should not be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with the interior of two elements, the specific meaning of the terms in this application will be understood by those of ordinary skill in the art.
Among the various types of chips, NFC (near field communication), such as electromagnetic induction, is a wireless communication technology that can communicate within an extremely short distance, and the principle of NFC chips is based on RFID, radio frequency identification technology, which uses electromagnetic fields to transmit data, and NFC chips have two modes of operation: a reader/writer mode in which the NFC chip can communicate with other NFC devices or RFID tags, and a card mode in which the NFC chip can be read like a normal IC card, an antenna in the NFC chip being a key element for communication, when the NFC device is close to the NFC chip, the device generates an electromagnetic field which excites the antenna in the NFC chip to generate an induced current, which is then used by the NFC chip to activate the circuitry in the chip and to transfer data stored in the chip to the NFC device via the electromagnetic field.
In summary, the working principle of the NFC inductive chip is to use an electromagnetic field to transmit data, and when the NFC device approaches the NFC chip, the device generates an electromagnetic field to excite an antenna in the chip to generate an induced current, so as to realize communication.
In the existing induction chip, in order to enhance the stability of welding, a plurality of uniformly-spaced bonding pads are formed on the welding surface of the chip to be welded together, and each bonding pad is overlapped through a conductive block to increase the height, as shown in figure 12, but the welding structure has poor stability, because the conductive block is stacked by layer-by-layer encapsulation, electroplating and the like, the contact surface of the conductive block is limited, the bonding force between the conductive block made of metal material and the plastic package material made of epoxy resin material is limited, and the structure is unstable; the welding quality of the solder paste is also easily affected, the bonding pad is only exposed on one plastic cover, the exposed area is limited, the bonding pad is at a certain distance from the edge of the packaging material, the tin climbing observation is not obvious during welding, whether the solder paste is sufficient is judged by observing the tin climbing phenomenon during welding, the cold welding is easy to occur when the tin climbing observation is not obvious, the poor welding is caused, and the electrical connection of the chip is short-circuited; the chip can be welded and attached on only one side, the thinnest plastic packaging material packaged at the functional side of the chip cannot be guaranteed in different attaching directions, and the welding surface of the chip cannot be selected according to the limited space of the welding plate so as to reasonably utilize the space.
For better understanding of the objects, structures and functions of the present application, a further detailed description of an induction chip package structure, process and semiconductor device according to the present application is provided below with reference to fig. 1 to 12.
Referring to fig. 1-4, fig. 1 is a longitudinal section view of an induction chip package structure according to the present application, which includes a package body 6, wherein a die 1 and an RDL2 electrically connected with the die 1 are encapsulated in the package body 6, and the package body 6 is further encapsulated with:
the metal layer is plated with holes by etching the wrapping cover, the plated hole wall surface and the wrapping surface are electroplated, and the metal layer on the plated hole wall surface is exposed after being cut;
the top bonding pad 5 and the bottom bonding pad 3 are respectively connected with the corresponding metal layers on the encapsulation surface so as to uniformly wrap the encapsulation body 6 corresponding to the right-angle sides;
the bottom bonding pad 3 is electrically connected with the RDL2, and the die 1 is electrically transferred from the RDL2 to the bottom bonding pad 3.
Referring to fig. 5-11, fig. 5 is a flow chart of an induction chip packaging process according to the present application, which includes the following steps:
s1: at least one bare chip 1 is attached to the substrate and encapsulated, bumps are exposed by grinding, RDL2 electrically connected with the bumps is electroplated, RDL2 is encapsulated, plated holes are etched, and cutting lines penetrate through the plated holes;
s2: electroplating a metal layer on the wall surface of the plated hole and the encapsulation surface, and encapsulating and grinding the thinned metal layer;
s3: electroplating a top welding disk 5 connected with the metal layer on the encapsulation surface, and encapsulating;
s4: removing the substrate, and etching a plating hole again on the encapsulation surface, wherein the top end of part of the plating hole is communicated with RDL 2;
s5: electroplating a metal layer on the wall surface of the plated hole and the encapsulation surface, and encapsulating and grinding the thinned metal layer;
s6: electroplating a bottom welding disk 3 and a side welding disk 4 which are connected with the metal layer on the encapsulation surface, and encapsulating;
s7: cutting wires cut the metal layer, the top welding disk 5, the bottom welding disk 3 and the side welding disk 4 to form outer pins wrapped by the corresponding right-angle sides of the package body 1.
Referring to fig. 6 and S1, after an insulating layer is coated on the back surface of the die 1, the die 1 is mounted on a substrate for encapsulation to buffer stress, the insulating layer is a polyimide film commonly used in the art, and the like, the die 1 is electroplated with an electrical connection bump at an I/O interface of the die, the bump leads out the electrical property of the die 1, the bump can be a ball-embedded or a conductive post, after the back surface of the die 1 is mounted on the substrate, the die 1 and the bump are completely encapsulated by using a plastic package material, the encapsulation is a supporting plate commonly used in the art, such as an FR-4 substrate.
Referring to fig. 6 and S1, the package surface far from the substrate is polished by mechanical polishing until the top surface of the bump is exposed, and RDL2 (re-wiring layer) is electroplated on the top surface of the bump to reform the circuit, and the electrical property of the die 1 is transferred to RDL2 through the bump.
Referring to fig. 6 and S1, the RDL2 is encapsulated again, after encapsulation, a plated hole is formed on the encapsulated surface by etching through laser drilling, the size of the plated hole is adjusted according to the size of the exposed soldering leg required by the product, and the plated hole can be square, rectangular, semicircular or a combined pattern of any two of the three.
Referring to fig. 7 and S2, a metal layer is formed by electroplating on the inner side wall of the plated hole and the area where the plated hole is connected with the encapsulation surface, wherein the thickness range of the metal layer electroplated on the inner wall of the plated hole and the encapsulation surface is equal to or greater than 50 μm to ensure that the metal layer is complete when being cut, then the encapsulation encapsulates the metal layer, the encapsulation material simultaneously fills the gap in the plated hole, the metal layer is exposed by grinding, and meanwhile, the thickness of the metal layer is reduced by 10-40 μm, so that the metal layer is completely exposed, the metal layer is thinned to reduce the height of the formed bonding pad, ensure the structural stability of the bonding pad, and the roughness of the surface of the ground metal layer is increased, so that the bonding force of the top bonding pad 5 connected by subsequent electroplating is better.
Referring to fig. 8 and S3, a top bonding pad 5 is electroplated on the metal layer, the top bonding pad 5 is connected with the top surface of the metal layer, the top bonding pad 5 is encapsulated, the top bonding pad 5 is designed to be a plurality of sequentially arranged according to the product requirement, and the top bonding pad 5 is not electrically connected with the die 1.
Referring to fig. 9 and S4, after the substrate is removed, the back surface of the die 1 is exposed to the package body 6, and the encapsulant is etched on the back surface to form a plated hole, where the plated hole is divided into a part vertically symmetrical to the plated hole at the top pad 5 and another part located in another area inside the package body 6, the top of the symmetrical plated hole is communicated with RDL2, and the plated hole of the other part may be optionally electrically connected or not.
Referring to fig. 10, S5 and S6, the bottom pad 3 and the side pad 4 are electroplated in the same manner as the top pad 5, the bottom pad 3 is electrically connected to the RDL2, the side pad 4 is not electrically connected, the top pad 5, the bottom pad 3 and the metal layers respectively connected with the two pads are symmetrically arranged with respect to the encapsulating material therebetween, and the cutting lines (dotted line portion in fig. 7) of the cutting lines in the direction can be cut to the metal layers, and the encapsulating material completely encapsulates the bottom pad 3 and the side pad 4.
Referring to fig. 11 and S7, after the encapsulation surface is ground in multiple sides, the side bonding pad 4, the top bonding pad 5 and the bottom bonding pad 3 are respectively exposed, and then cut along the cutting line, the metal layer is cut in the width thereof, and the end of the metal layer is connected with the bonding pad, so that a right angle-shaped outer bonding leg is formed, and a plurality of outer bonding legs are arranged, the direct edge of the encapsulation body 6 is uniformly wrapped, a metal layer is formed on the inner wall surface of the plating hole and the encapsulation surface in a drilling manner, then the bonding pad is electroplated on the top surface of the metal layer, the contact area between the metal layer and the encapsulation material is increased, the bonding force between the metal layer and the encapsulation material is enhanced, the bonding pad structure is more stable, the metal layer is cut on one side of the metal layer in an electroplating way, so that the exposed metal layer and the bonding pad are connected together to form a right angle-shaped outer bonding leg, and the right angle edge of the encapsulation body is wrapped, namely, and the encapsulation body can be welded and attached on five other surfaces except for the functional surface of a bare chip; when the bottom surface is attached, the welding firmness is enhanced through the bottom of the bottom bonding pad 3 and the bottom of the side bonding pad 4; further, a convex bonding pad can be electroplated on the top surface, and when the top surface is attached, the welding is enhanced through the top of the top bonding pad 5 and the convex bonding pad; the side parts of the side bonding pads 4 are welded in a reinforcing manner during left surface mounting, the side parts of the side bonding pads 4 are welded in a reinforcing manner during right surface mounting, and the side parts of the top bonding pads 5 and the bottom bonding pads 3 are welded in a reinforcing manner during front surface mounting.
A semiconductor device comprises the induction chip packaging structure.
The induction type chip is arranged on the mounting machine table, the induction ends are respectively arranged on the X, Y, Z axes of different mounting directions according to the tracks, the X, Y, Z coordinate axes are provided with magnetic fields in the respective extending directions, the chip is required to be welded on the welding plate, the welding direction is required to be selected according to the welding scene, so that the surface of the bare chip closest to the edge of the packaging material in the packaging structure is always aligned with the induction ends, the smaller the distance between the functional surface of the chip and the packaging edge is, the more beneficial the smaller the distance between the functional surface of the chip and the packaging edge is, the less the interference and the blocking of the packaging material on signals are, after the welding direction is selected, the mounting surface of the packaging structure can be correspondingly selected, so that the space of the welding plate is reasonably utilized, the mounting surface of the chip is changeable, and the mounting flexibility is good.
The application can correspondingly select the mounting surface of the packaging structure, so that the space of the welding plate is reasonably utilized, the mounting surface of the chip is changeable, the mounting flexibility is good, the five surfaces of the packaging body 6 are respectively provided with the welding pads, the welding points are more, the tin climbing observation is obvious, the welding effect is good, the metal layer is formed on the inner wall surface of the plating hole and the packaging surface in a drilling mode, the welding pads are plated on the end surface of the metal layer, the contact area between the metal layer and the packaging material is increased, the bonding force between the metal layer and the packaging material is enhanced, the welding pad structure is more stable, the process flow is simple, and the cost is lower.
The application adopts copper material as the metal seed layer, which is used for ensuring the binding force between the metal and plastic package material for subsequent electroplating, and simultaneously providing the surface to which conductive ions are attached for electroplating, thereby ensuring the electroplating effect.
All the steps of the packaging process are to form the package by adopting a plastic package material injection molding mode and matching with mould pressing.
It will be understood that the present application has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the present application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the application without departing from the essential scope thereof. Therefore, it is intended that the application not be limited to the particular embodiment disclosed, but that the application will include all embodiments falling within the scope of the appended claims.
Claims (11)
1. The utility model provides an induction chip packaging structure, includes the packaging body, the encapsulation has bare chip and with bare chip electric connection's RDL in the packaging body, its characterized in that, still encapsulate in the packaging body has:
the metal layer is plated with holes by etching the wrapping cover, the plated hole wall surface and the wrapping surface are electroplated, the metal layer on the plated hole wall surface is exposed after being cut, and the thickness range of the metal layer electroplated on the plated hole inner wall and the wrapping surface is more than or equal to 50 mu m;
the top bonding pad and the bottom bonding pad are respectively connected with the corresponding metal layers on the encapsulation surface so as to uniformly wrap the corresponding right-angle sides of the encapsulation body;
the bottom welding disc is electrically connected with the RDL, and the bare chip is electrically transmitted to the bottom welding disc from the RDL;
the package further includes side pads, the bottom pads are formed while the other two package surfaces of the package are also plated with the side pads to enhance solder stability,
the convex bonding pads are electroplated on the top surface of the packaging body, and the packaging body can be attached on one surface selected from the bottom surface, the top surface, the left surface, the right surface and the front surface.
2. The inductive chip package structure of claim 1, wherein the plated hole is square, semicircular or a combination thereof to ensure integrity of the metal layer during dicing.
3. The induction chip packaging structure according to claim 2, wherein the metal layer is ground after being encapsulated, the thickness of the metal layer is thinned by 10-40 μm, and the metal layer is completely exposed so as to ensure the bonding strength between the metal layer and the bonding pad.
4. The inductive chip package of claim 3, wherein said package encapsulates at least one die, and wherein the back side of the die is coated with an insulating layer and then attached to a substrate for encapsulation to buffer stress.
5. The inductive chip package structure of claim 4, wherein said metal layer, top pad and bottom pad are all formed by an electroplating process.
6. A semiconductor device comprising the inductive chip package of claim 1.
7. The induction chip packaging method is characterized by comprising the following steps of:
RDL encapsulation step: electroplating rewiring at the position of the exposed die interface electric connection convex block after encapsulation, and encapsulating the rewiring;
top and bottom bond pad formation steps: etching the wrapping cover to uniformly form a plating hole, electroplating a metal layer on the wall surface of the plating hole and the wrapping surface, wherein the thickness range of the metal layer electroplated on the inner wall of the plating hole and the wrapping surface is more than or equal to 50 mu m, wrapping and grinding to expose the metal layer, electroplating a bonding pad connected with the metal layer, and wrapping the bonding pad; the bonding pads comprise a top bonding pad and a bottom bonding pad which are respectively formed on two opposite encapsulation surfaces of the packaging body, and are symmetrically arranged about packaging materials between the two encapsulation surfaces, and plated holes on the bottom surface are connected with the RDL so as to ensure the electrical transmission of the RDL and the bottom bonding pad;
the cutting is unit steps: the encapsulation material is ground on multiple sides and the top bonding pad and the bottom bonding pad are exposed, the encapsulation body is cut along a cutting line in a cutting line, the cutting line is positioned in the width range of the metal layer on the wall surface of the plating hole, so that the metal layer is cut, the welding feet wrapped by the right-angle side metal of the encapsulation body are uniformly formed, and the electric property of the bare chip is transmitted to the bottom bonding pad through the convex blocks and the RDL;
and a side bonding pad forming step, wherein the side bonding pads are also electroplated on the other two encapsulation surfaces of the package body at the same time of forming the bottom bonding pads so as to enhance the welding stability,
the convex bonding pads are electroplated on the top surface of the packaging body, and the packaging body can be attached on one surface selected from the bottom surface, the top surface, the left surface, the right surface and the front surface.
8. The method of claim 7, further comprising providing a substrate, attaching at least one die with an electrical connection bump formed thereon to the substrate, encapsulating the die and bump, and polishing to expose a top surface of the bump.
9. The method of claim 7, wherein in the step of forming the top and bottom pads, the plated hole is square, semicircular, or a combination thereof to ensure the integrity of the metal layer when the metal layer is cut.
10. The method of claim 9, wherein in the step of forming the top and bottom pads, when the metal layer is exposed by encapsulation grinding, the metal layer is ground to be thinned by 10-40 μm, and the metal layer is completely exposed to ensure bonding strength between the metal layer and the pads.
11. The method of claim 10, wherein the top and bottom bonding pads are formed on opposite surfaces of the package substrate, and the method further comprises removing the package substrate, wherein the top and bottom bonding pads are formed on opposite surfaces of the package substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310567944.6A CN116364681B (en) | 2023-05-19 | 2023-05-19 | Induction chip packaging structure, process and semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310567944.6A CN116364681B (en) | 2023-05-19 | 2023-05-19 | Induction chip packaging structure, process and semiconductor device |
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| CN116364681A CN116364681A (en) | 2023-06-30 |
| CN116364681B true CN116364681B (en) | 2023-08-15 |
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| CN (1) | CN116364681B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000040592A (en) * | 1998-12-18 | 2000-07-05 | 윤종용 | Wafer level chip scale package having dummy solder ball |
| KR20100069545A (en) * | 2008-12-16 | 2010-06-24 | (주)웨이브닉스이에스피 | Terminal integrated type metal-based package module and terminal integrated type packaging method for metal-based package module |
| CN202585413U (en) * | 2012-05-25 | 2012-12-05 | 深圳市九洲光电科技有限公司 | Full-color surface-mounting device having front face brushed into black |
| CN107211526A (en) * | 2015-03-31 | 2017-09-26 | 惠普发展公司有限责任合伙企业 | Printed circuit board (PCB) |
| CN114783888A (en) * | 2022-06-16 | 2022-07-22 | 合肥矽迈微电子科技有限公司 | Exposed welding leg of chip packaging body and processing method thereof |
-
2023
- 2023-05-19 CN CN202310567944.6A patent/CN116364681B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000040592A (en) * | 1998-12-18 | 2000-07-05 | 윤종용 | Wafer level chip scale package having dummy solder ball |
| KR20100069545A (en) * | 2008-12-16 | 2010-06-24 | (주)웨이브닉스이에스피 | Terminal integrated type metal-based package module and terminal integrated type packaging method for metal-based package module |
| CN202585413U (en) * | 2012-05-25 | 2012-12-05 | 深圳市九洲光电科技有限公司 | Full-color surface-mounting device having front face brushed into black |
| CN107211526A (en) * | 2015-03-31 | 2017-09-26 | 惠普发展公司有限责任合伙企业 | Printed circuit board (PCB) |
| CN114783888A (en) * | 2022-06-16 | 2022-07-22 | 合肥矽迈微电子科技有限公司 | Exposed welding leg of chip packaging body and processing method thereof |
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| CN116364681A (en) | 2023-06-30 |
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