WO2023010555A1

WO2023010555A1 - Chip package structure and electronic device

Info

Publication number: WO2023010555A1
Application number: PCT/CN2021/111275
Authority: WO
Inventors: 童亮; 刘立筠; 张珊; 刘国文
Original assignee: 华为技术有限公司
Priority date: 2021-08-06
Filing date: 2021-08-06
Publication date: 2023-02-09
Also published as: CN117203745A

Abstract

The present application relates to the technical field of packaging and provides a chip package structure and an electronic device, capable of solving the problem that a package substrate cannot carry more electronic devices due to the limited area of the package substrate. The chip package structure comprises a substrate, a chip, a first circuit device, and an elevated plate. The substrate comprises an upper surface (a first surface) and a lower surface (a second surface), and a metal wire is disposed in the substrate. The chip is disposed on the upper surface of the substrate. The top of the first circuit device is fixed on the lower surface of the substrate and is electrically connected to the chip by means of the metal wire. The top of the elevated plate is fixed on the lower surface of the substrate, and a metal via hole communicating with the top and the bottom of the elevated plate is formed in the elevated plate. The metal via hole is electrically connected to the metal wire. The surface of the bottom of the first circuit device is flush with the surface of the bottom of the elevated plate.

Description

Chip packaging structure and electronic equipment

technical field

The present application relates to the technical field of packaging, in particular to a chip packaging structure and electronic equipment.

Background technique

In electronic circuits, capacitors or inductors are commonly used devices. The size of the capacitors and inductors to be used can vary widely for different needs. Some capacitors and inductors are small in size and can be formed inside the chip, while some capacitors and inductors are large in size and can only be set outside the chip.

Figure 1 shows a typical IC packaging structure. The package structure includes a package substrate 10 , a chip 11 and an inductor 12 . Wherein, the packaging substrate 10 is used to carry the chip 11 and the inductor 12 . The inside of the package substrate 10 is provided with signal lines, and the bottom of the package substrate 10 is provided with solder balls. In some scenarios, the signal flowing into the chip 11 must first pass through the inductor 12 . Therefore, to flow into the chip 11 , the signal needs to pass through the packaging substrate 10 , the inductor 12 , and the packaging substrate 10 in sequence, and then enter the chip 11 . During this process, the signal enters the package substrate 10 twice, which increases the complexity of wiring on the package substrate. Moreover, with the improvement of industrial demand, more and more electronic devices will be carried on the top surface of the packaging substrate. Not only the signal lines in the packaging substrate will become denser, but also the space on the top surface of the packaging substrate will become increasingly tight.

Contents of the invention

Embodiments of the present application provide a chip packaging structure and electronic equipment, which can solve the problem that more electronic devices cannot be carried due to the limited area of the packaging substrate.

The present application provides a chip packaging structure, which includes a substrate, a chip, a first circuit device, and an elevated board. Wherein, the substrate includes an upper surface (first surface) and a lower surface (second surface), and metal circuits are arranged on the substrate. The chip is arranged on the upper surface of the substrate. The top of the first circuit device is fixed on the lower surface of the substrate, and is electrically connected to the chip through metal lines. The top of the elevated board is fixed on the lower surface of the substrate, and a metal via hole connecting the top and bottom of the elevated board is provided in the elevated board, and the metal via hole is electrically connected to the metal line; the first circuit device The surface of the bottom is flush with the surface of the bottom of the raised plate.

On the one hand, in the present application, the first circuit device is arranged on the lower surface of the substrate, which no longer occupies the space on the upper surface of the substrate, and can make the upper surface of the substrate more capable of carrying more devices; at the same time, it can make the printed circuit board ( Printed circuit board (PCB) signals can directly flow into the chip after passing through the first circuit device and the substrate; in this case, more metal lines in the substrate can be distributed in the direction vertical to the substrate, simplifying the wiring complexity of the substrate degree, so that the interaction path between the first circuit device and the chip in the vertical direction is shortened. On the other hand, by setting the elevated plate on the lower surface of the substrate outside the area of the first circuit device, and setting a metal via hole connecting the top and bottom inside the elevated plate; by setting the surface of the bottom of the elevated plate and the first circuit The surface of the bottom of the device is even, and the height difference between the bottom of the first circuit device and the lower surface of the substrate is filled by the first circuit device, and the lower surface of the substrate is aligned with the bottom of the first circuit device by an elevating plate. Planar pins (lead-out pins) are electrically connected to the PCB, thereby improving the processability and stability of the chip packaging structure when it is placed on the board (that is, on the board), and ensuring a reliable connection between the chip packaging structure and the PCB.

In some possible implementation manners, the elevated plate is a ring structure, and the first circuit device is surrounded by the elevated plate.

In some possible implementation manners, the first circuit device is a chip, an electron tube, a capacitive device, a resistive device or an inductive device.

In some possible implementation manners, the chip, the first circuit device and the raised board are wrapped by molding; that is, the chip, the first circuit device and the raised board are integrally molded in the chip packaging structure.

In some possible implementation manners, the first circuit device includes a first pin and a second pin; the first pin is located on the top of the first circuit device and is fixed on the lower surface of the substrate for electrically connecting with the metal line. sexual connection; the second pin is located at the bottom of the first circuit device. In this case, the first circuit device can be electrically connected to the metal lines in the substrate through the first pins on the top, and can be electrically connected to the PCB through the second pins on the bottom.

In some possible implementation manners, the top and the bottom of the elevated board are respectively provided with welding pads connected to two ends of the metal via hole. In this case, the elevated board can be electrically connected to the metal lines in the substrate through the solder pads on the top, and electrically connected to the PCB through the solder pads on the bottom. In some possible implementations, metal side walls are formed on the sides of the elevated board; the metal side walls extend along the sides of the elevated board to the top and bottom of the elevated board, and are exposed at the top and bottom of the elevated board. Metal vias on the top and bottom of the elevated board. In this case, the metal via hole and the metal sidewall can transmit signals at the same time, which is equivalent to having two flow paths, thereby increasing the flow path, thereby improving the flow capability of the chip package structure in the vertical direction.

In some possible implementation manners, the metal vias are filled with resin to improve the reliability of the metal vias.

The present application also provides an electronic device, including a printed circuit board and a chip package structure as provided in any of the aforementioned possible implementation modes; The board is electrically connected.

In some possible implementation manners, the bottom of the first circuit device in the chip package structure is fixed on the printed circuit board and is electrically connected to the printed circuit board.

Description of drawings

FIG. 1 is a schematic diagram of a chip packaging structure provided by the related art of the present application;

FIG. 2 is a schematic diagram of a chip package structure provided by an embodiment of the present application;

Fig. 3 is a schematic plan view of an elevated board provided by an embodiment of the present application;

Fig. 4 is the schematic cross-sectional view of the elevated plate in Fig. 3 along the OO' position;

FIG. 5 is a schematic cross-sectional view of an elevated plate provided in an embodiment of the present application;

Fig. 6 is a schematic cross-sectional view of an elevated board provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly described below in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, and Not all examples. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The terms "first" and "second" in the description, embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be interpreted as indicating or implying relative importance, nor can they be interpreted as indicating or imply order. Words such as "connected" and "connected" are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. "At least one (item)" means one or more, and "multiple" means two or more. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, of a sequence of steps or elements. A method, system, product or device is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to the process, method, product or device. "Up", "Down", "Left", "Right", "Top", "Bottom", etc. are only used relative to the orientation of components in the drawings. These directional terms are relative concepts, and they For description and clarification relative to, it may change accordingly according to the change in orientation of parts in the drawings.

Some embodiments of the present application provide an electronic device, and the electronic device may be applied in fields such as a network center and a base station, and the present application does not make any special limitations on this.

As shown in FIG. 2, the electronic device includes a printed circuit board (printed circuit board, PCB) 02, and at least one chip package structure 01 connected to the PCB 02. In Fig. 2, it is only schematically illustrated by taking a chip package structure 01 as an example, but the application is not limited thereto. In other possible implementation modes, two or more than two can also be set on the PCB 02 chip package structure 01.

The present application does not limit the types and applications of the above-mentioned chip package structure 01 . Schematically, the chip package structure 01 may be a 3D (dimension) chip package structure, a 2.5D chip package structure, a SiP (system in package, system-in-package) structure, and the like. The chip packaging structure 01 can be applied to power management chip packaging structures, radio frequency front-end chip packaging structures, and the like.

The specific configuration of the chip package structure 01 provided in the embodiment of the present application will be schematically described below.

Referring to FIG. 2 , the chip packaging structure 01 is provided with a substrate 1 , at least one chip 2 (die), and at least one first circuit device 3 .

The substrate 1 has an upper surface a1 (that is, the first surface) and a lower surface a2 (that is, the second surface) that are oppositely disposed, and metal circuits are disposed in the substrate 1 . Schematically, the upper surface a1 and the lower surface a2 of the substrate 1 are usually provided with connection structures electrically connected to the internal metal lines, such as pads (or pads, pads), micro bumps (μbump), etc.; The connection structure, pins, etc. are similar to this and will not be repeated here.

The chip 2 is disposed on the upper surface a1 of the substrate 1 and is electrically connected to the metal circuit in the substrate 1 . Schematically, the chip 2 can be connected to the connection structure (such as pad) on the upper surface of the substrate 1 through pins (such as pads) provided on the bottom surface thereof.

The first circuit device 3 is arranged on the lower surface a2 of the substrate 1, the top of the first circuit device 3 is fixed on the lower surface a2 of the substrate 1, and the first circuit device 3 is electrically connected to the chip 2 through the metal circuit provided in the substrate 1 .

Schematically, the first circuit device 3 can be connected to the connection structure (such as a pad) provided on the lower surface of the substrate 1 through the pins provided on the top (ie, the first pins). Of course, in some possible implementations, the bottom of the first circuit device 3 can also be provided with pins (i.e. the second pin), the bottom of the first circuit device 3 can be fixed on the PCB 02, and the bottom of the first circuit device 3 can be fixed on the PCB 02, and the bottom of the first circuit device 3 can be fixed on the PCB 02, and the bottom of the first circuit device 3 can be fixed on the PCB 02, and the bottom of the first circuit device 3 can be fixed. Pin is electrically connected with PCB 02.

The present application does not limit the specific arrangement form of the above-mentioned first circuit device 3 . The first circuit device 3 can be an active device, such as a chip (integrated circuit), an electron tube, etc.; it can also be a passive device, such as an inductance device, a capacitor device, a resistance device, etc. For example, in some embodiments, the first circuit device 3 may be a large inductive device. The chip packaging structure 01 may be provided with one first circuit device 3 , or may be provided with two or more first circuit devices 3 . In practice, the first circuit device 3 can be set as required.

It can be understood here that, compared with placing the circuit device on the upper surface a1 of the substrate 1, the first circuit device 3 is arranged on the lower surface a2 of the substrate 1 in this application. On the one hand, the substrate 1 is no longer occupied. The space on the upper surface of the substrate can make the upper surface of the substrate 1 more capable of carrying more devices; on the other hand, the signal through the PCB 02 can directly flow into the chip 2 after passing through the first circuit device 3 and the substrate 1; in this case Therefore, more metal circuits in the substrate 1 can be distributed in the direction perpendicular to the substrate 1 , which simplifies the wiring complexity of the substrate and shortens the interaction path between the first circuit device 3 and the chip 2 in the vertical direction.

On this basis, as shown in FIG. 2 , since the first circuit device 3 itself has a certain thickness, there is a certain height difference Δh between the bottom of the first circuit device 3 and the lower surface a2 of the substrate 1 . Based on this, in order to ensure that the lower surface a2 of the substrate 1 is normally out of the pin (lead-out pin), and is electrically connected to the PCB 02 normally, in the chip package structure 01 provided in the embodiment of the present application, the lower surface a2 of the substrate 1 can be Located in the area outside the first circuit device 3, a frame board 4 (frame board, FB) is set, and the electrical connection between the substrate 1 and the PCB 02 is realized through the frame board 4, that is, the PCB 02 is connected to the substrate 1 through the frame board 4. Metal wires for electrical connection.

Fig. 3 is a schematic plan view of the elevated plate 4 in Fig. 2, and Fig. 4 is a sectional view of Fig. 3 along OO' position. As shown in Fig. 2, Fig. 3 and Fig. 4, the top of the elevated plate 4 is fixed on the lower surface a2 of the base plate 1, and a metal via hole 40 connecting the top and the bottom is provided inside the elevated plate 4, and on the frame The top of the elevated plate 4 is electrically connected to the metal line in the substrate 1 through the metal via 40; in this case, the bottom of the elevated plate 4 can be fixed on the PCB 02 and electrically connected to the PCB 02 through the metal via 40 . That is to say, by setting the elevating plate 4 in the area outside the first circuit device 3 on the lower surface a2 of the substrate 1, the electrical connection between the PCB 02 and the substrate 02 is realized through the elevating plate 4.

In some possible implementation manners, as shown in FIG. 4 , solder pads P connected to both ends of the metal via hole 40 are respectively provided on the top and bottom of the elevated board 4 . In this case, the elevated board 4 can be electrically connected to the metal lines in the substrate 1 through the solder pads P located on the top, and electrically connected to the PCB 02 through the solder pads P located at the bottom. In the following embodiments, the top and bottom of the elevated board 4 are respectively provided with soldering pads P connected to both ends of the metal via hole 40 as an example for schematic illustration.

It can be understood that, in order to ensure that the electrical connection between the PCB 02 and the substrate 02 is realized by the elevating plate 4, it should be ensured that the surface of the bottom of the elevating plate 4 protrudes from the surface of the bottom of the first circuit device 3, or that the elevating plate The surface of the bottom of 4 is flush with the surface of the bottom of the first circuit device 3 . Considering the thickness of the entire chip package structure 01 , to avoid increasing the thickness of the chip package structure 01 , it is generally possible to set the bottom surface of the elevated plate 4 to be flush with the bottom surface of the first circuit device 3 .

Under the condition that the surface of the bottom of the elevated plate 4 is flush with the surface of the bottom of the first circuit device 3, the gap between the bottom of the first circuit device 3 and the lower surface a2 of the substrate 1 can be filled by the elevated plate 4. The height difference Δh, in this case, the bottom of the elevating board 4 and the bottom of the first circuit device 3 can be electrically connected to the PCB 02 through the pin (that is, the lead-out pin) on the same plane, thereby improving the chip package structure 02. The manufacturability and stability of the board (that is, the PCB) ensure the reliable connection of the chip package structure 01 and the PCB 02. In the following embodiments, the bottom surface of the elevated board 4 is flush with the bottom surface of the first circuit device 3, and the bottom surface of the elevated board 4 and the bottom of the first circuit device 3 are electrically connected to the PCB 02 as An example is illustrated.

It should be noted that the above description about the bottom surface of the elevated board 4 being “flat” with the bottom surface of the first circuit device 3 does not refer to absolute coplanarity, and those skilled in the art should understand that at least Ensure that the bottom surface of the elevated board 4 and the bottom surface of the first circuit device 3 can be connected to the PCB 02 to achieve normal connection, that is, the bottom surface of the elevated board 3 and the bottom of the first circuit device 3 There may be a certain height difference on the surface, but the height difference can be regarded as "flat" within the error range allowed by the connection process. For example, taking the welding process as an example, the welding plane can allow an error within 30 μm, then the height difference between the bottom surface of the elevated plate 4 and the bottom surface of the first circuit device 3 can be regarded as a flat surface within 30 μm. together.

It should also be noted that in the chip packaging structure 01 provided in the embodiment of the present application, the elevated board 4 and the first circuit device 3 can be packaged as a whole, that is, the chip 2, the first circuit device 3 and the elevated board 4 are integrally packaged. Wrapped in plastic wrap. In other possible implementation manners, the elevated board 4 and the first circuit device 3 may also be fixed on the lower surface of the substrate 1 by means of underfill. This application does not limit this, and it can be set according to actual needs.

In addition, in the present application, there is no limitation on the shape and quantity of the elevating plate 4 arranged in the chip packaging structure 01 , which can be arranged according to actual needs. For example, in some possible implementations, as shown in FIG. 2 and FIG. 3 , a ring-shaped elevated plate 4 may be provided in the chip package structure 01 , and the first circuit device 3 is surrounded by the ring-shaped elevated plate. For another example, in some possible implementations, the elevated board 4 can be in the shape of a strip or a block; in this case, multiple elevated boards 4 can be set in the chip packaging structure 01, such as a plurality of elevated boards 4 can be distributed along the circumference of the chip package structure 01.

In addition, referring to FIG. 4 , considering the actual manufacturing process of the metal via 40, the central part of the metal via 40 is a hole V. Therefore, in order to improve the reliability of the metal via 40, in some possible implementation methods, The void V of the metal via 40 is filled.

In the present application, there is no limitation on the filling material in the void V of the metal via 40 . For example, the filling material can be a conductive material, such as copper, copper alloy, aluminum, etc.; for another example, the filling material can also be an insulating material, such as a resin material. It can be understood that filling the void V of the metal via hole 40 with a conductive material (such as copper) can improve the flow capacity of the chip package structure in the vertical direction.

Schematically, in some possible implementation manners, the void V of the metal via hole 40 may be filled with copper material by pouring copper paste.

Schematically, in some possible implementation manners, resin may be used to fill the void V of the metal via hole 40 .

In addition, since the thickness and density of the metal vias 40 are limited by manufacturing process conditions, the flow capacity of the chip package structure 01 in the vertical direction is limited to a certain extent. Based on this, in order to meet the requirements of the chip packaging structure 01 for large flow capacity in the vertical direction, as shown in FIG. The metal side wall S extends along the side of the elevated plate 4 to the top and bottom of the elevated plate 4 , and is connected to the metal via hole 40 through the solder pad P. In this case, the metal via 40 and the metal sidewall S can transmit signals at the same time, which is equivalent to having two flow paths, thereby increasing the flow path, thereby improving the flow capacity of the chip package structure in the vertical direction .

On this basis, in order to further increase the flow capacity of the chip package structure 01 in the vertical direction, as shown in FIG. The metal sidewall S, the two metal sidewalls S extend along the side of the raised board 4 to the top and bottom of the raised board 4 , and are connected to the metal via hole 40 through the welding pad P. In this case, the two metal sidewalls S and the metal via 40 can transmit signals at the same time, which is equivalent to having three flow paths, which further increases the flow path and improves the vertical stability of the chip package structure. flow capacity.

In the chip package structure provided by the embodiment of the present application, a group (multiple) of metal vias 40 can be electrically connected to one metal sidewall S, or can be electrically connected to multiple independently provided metal sidewalls S. This is not limited, and can be set according to actual needs. Schematically, in some embodiments, a group of metal vias 40 are connected to a plurality of independently arranged metal sidewalls S. In this case, the same electrical signal can be transmitted through the plurality of metal sidewalls S respectively, so as to meet the needs of the chip. Requirements for the package structure; for example, multiple metal sidewalls S can be used to meet the requirements of multiple power supplies and multiple signals for the chip package structure.

The manufacturing process of the elevated plate 4 will be schematically described below.

Schematically, the elevated board 4 can be made of organic resin material, and the metal parts (such as metal vias 40, metal side walls S, soldering pads P, etc.) provided in the elevated board 4 can be made of copper, but not Not limited to this.

In some possible implementation manners, the elevated board 4 can be manufactured using low-cost PCB preparation technology.

Schematically, a plate of resin material can be used first, and the through hole through the top and bottom of the plate and the overall outline (such as ring shape, strip shape, etc.) can be engraved through the milling cutter operation to make the main structure of the elevated plate 4 . Then, electroplating or electroless plating can be used to perform metallization on the inside of the through hole and part of the side of the main structure to form metal vias, metal side walls, etc.; then use a milling cutter to mill off the excess to obtain the required elevated board 4.

It can be understood that, compared with the related art of using ball planting, copper pillars, etc. to pin out a substrate with a height difference, generally only a height difference within 1 mm can be met. The elevated plate 4 provided in this application adopts the method of the metal via 40 , based on the current manufacturing process of the metal via 40 (such as electroplating process), the height of the metal via 40 can reach more than 2 mm. That is to say, the use of the elevated plate 4 provided by the embodiment of the present application can solve the problem that the height difference of the lower surface of the substrate exceeds 2mm and the pins, so as to meet the needs of a wider range of chip packaging structures. For example, a chip packaging structure that can meet the extremely large height difference brought about by ultra-large height circuit devices.

Schematically, in some possible implementation manners, the height of the metal via hole 40 in the elevated plate 4 may be 2mm-3mm; for example, it may be 2mm, 2.5mm, 3mm and so on.

In addition, it can also be understood that, in this application, the height difference between the substrate 1 and the first circuit device 4 is filled by adding an elevated plate 4 in the chip package structure 01, so that the size of the chip package structure 01 will hardly be enlarged, that is, The size of the chip package structure 01 is almost unchanged. If there is no need to change the size and position of the original pads in the chip package structure, the board-level application restrictions are small.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A chip packaging structure, characterized in that, comprising:

a substrate, the substrate includes a first surface and a second surface, and metal circuits are arranged on the substrate;

a chip disposed on the first surface;

a first circuit device, the top of which is fixed on the second surface and electrically connected to the chip through the metal line; and

An elevated plate, the top of the elevated plate is fixed on the second surface, a metal via hole connecting the top and bottom of the elevated plate is provided in the elevated plate, and the metal via hole electrically connected to the metal circuit;

The surface of the bottom of the first circuit device is flush with the surface of the bottom of the elevated plate.
The chip packaging structure according to claim 1, wherein,

The elevated plate is a ring structure, and the first circuit device is surrounded by the elevated plate.
The chip package structure according to claim 1 or 2, wherein,

The first circuit device is a chip, an electron tube, a capacitive device, a resistive device or an inductive device.
The chip packaging structure according to any one of claims 1-3, characterized in that,

The chip, the first circuit device and the elevated board are wrapped by a plastic encapsulation material.
The chip package structure according to any one of claims 1-4, characterized in that,

The first circuit device includes a first pin and a second pin;

The first pin is located on the top of the first circuit device, is fixed on the second surface, and is used for electrically connecting with the metal circuit;

The second pin is located at the bottom of the first circuit device.
The chip package structure according to any one of claims 1-5, characterized in that,

Welding pads connected to both ends of the metal vias are respectively provided on the top and the bottom of the elevated board.
The chip packaging structure according to any one of claims 1-6, characterized in that,

Metal side walls are formed on the sides of the elevated plate;

The metal sidewalls extend along the sides of the elevated plate to the top and bottom of the elevated plate and between the top and bottom of the elevated plate and the Metal via connection.
The chip packaging structure according to any one of claims 1-7, characterized in that,

The metal vias are filled with resin.
An electronic device, characterized in that it comprises a printed circuit board and the chip packaging structure according to any one of claims 1-8; the bottom of the elevated board is fixed on the printed circuit board, and passes through the The metal vias are electrically connected to the printed circuit board.
The electronic device according to claim 9, wherein the bottom of the first circuit device in the chip packaging structure is fixed on the printed circuit board and is electrically connected to the printed circuit board.