CN116343669A

CN116343669A - Pixel circuit and display panel

Info

Publication number: CN116343669A
Application number: CN202310340892.9A
Authority: CN
Inventors: 郭恩卿; 盖翠丽; 李俊峰; 彭兆基
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd
Priority date: 2023-03-31
Filing date: 2023-03-31
Publication date: 2023-06-27

Abstract

The invention discloses a pixel circuit and a display panel. The pixel circuit includes: the device comprises a driving module, a light emitting module, a first leakage suppression module, a second leakage suppression module, a first storage module and a threshold compensation module; the first leakage suppression module is connected between the control end of the driving module and the first node and is used for suppressing leakage of the control end of the driving module; the second leakage suppression module is connected between the second node and the first node and is used for suppressing the leakage of the control end of the driving module; the first storage module is connected with the first node and used for storing the voltage of the first node so as to reduce the pressure difference between the control end of the driving module and the first node; the threshold compensation module is connected between the first end of the driving module and the second node. According to the technical scheme, the influence of the electric leakage problem of the driving module on the display brightness is relieved, and therefore the display effect is improved.

Description

Pixel circuit and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit and a display panel.

Background

With the continuous development of display technology, performance requirements of display panels are increasing. The display panel includes a pixel circuit including a driving transistor for driving the light emitting device to emit light for display. The existing pixel circuit generally has the problem of larger leakage current, so that the grid voltage of the driving transistor is unstable, and the brightness of the light emitting device and the display effect of the display panel are affected.

Disclosure of Invention

The embodiment of the invention provides a pixel circuit and a display panel, which are used for relieving the influence of the leakage problem of the pixel circuit on display brightness, so that the display effect is improved.

In a first aspect, an embodiment of the present invention provides a pixel circuit, including:

the driving module is used for driving the light emitting module according to the voltage of the control end of the driving module;

the first leakage suppression module is connected between the control end of the driving module and the first node and is used for suppressing leakage of the control end of the driving module;

the second leakage suppression module is connected between the second node and the first node and is used for suppressing the leakage of the control end of the driving module;

the first storage module is connected with the first node and is used for storing the voltage of the first node so as to reduce the pressure difference between the control end of the driving module and the first node;

and the threshold compensation module is connected between the first end of the driving module and the second node and is used for compensating the threshold voltage of the driving module.

Optionally, a first end of the first memory module is connected to the first node, and a second end of the first memory module is connected to a fixed voltage;

Preferably, the first initialization module is connected between an initialization signal line and the second node, and is used for writing the voltage on the initialization signal line into the control end of the driving module;

preferably, the second end of the first memory module is connected with the initialization signal line, the initialization signal line is connected with an initialization voltage, and the initialization voltage is multiplexed into the fixed voltage;

preferably, the pixel circuit further includes a second initialization module connected between the initialization signal line and the first terminal of the light emitting module, the second initialization module being configured to write a voltage on the initialization signal line to the first terminal of the light emitting module;

preferably, the initialization signal line includes a first initialization signal line and a second initialization signal line, the first initialization signal line is connected to a first initialization voltage, the second initialization signal line is connected to a second initialization voltage, the first initialization module is connected to the first initialization signal line, and the second initialization module is connected to the second initialization signal line; the second end of the first memory module is connected with the first initialization signal line, the first initialization voltage is multiplexed into the fixed voltage, or the second end of the first memory module is connected with the second initialization signal line, and the second initialization voltage is multiplexed into the fixed voltage;

Preferably, the first power line is connected to a first power voltage, the second end of the first memory module is connected to the first power line, and the first power voltage is multiplexed to the fixed voltage.

Optionally, the pixel circuit further includes a data writing module, a first end of the data writing module is connected to the data line, and a second end of the data writing module is connected to the second end of the driving module;

the control end of the first initialization module is connected with a first scanning line, the control end of the threshold compensation module and the control end of the data writing module are connected with a second scanning line, and the control end of the first leakage suppression module and the control end of the second leakage suppression module are both connected with a leakage control signal line;

the first initialization module is conducted in an initialization stage in response to a signal on the first scanning line, and the first leakage suppression module and the second leakage suppression module are conducted in the initialization stage in response to a signal on the leakage control signal line so as to write voltage on the initialization signal line into a control end of the driving module;

the data writing module and the threshold compensation module are conducted in the data writing stage in response to the signals on the second scanning line, and the first leakage suppression module and the second leakage suppression module are conducted in the data writing stage in response to the signals on the leakage control signal line so as to write the voltage on the data line into the control end of the driving module and compensate the threshold voltage of the driving module;

The first leakage suppression module and the second leakage suppression module are turned off in a light-emitting stage in response to signals on the leakage control signal line so as to suppress leakage of a control end of the driving module;

preferably, the pixel circuit further comprises a second initialization module and a light-emitting control module, wherein a control end of the second initialization module is connected with a third scanning line, a control end of the light-emitting control module is connected with a light-emitting control signal line, and the light-emitting control module is connected between the first power line and the light-emitting module;

the first leakage suppression module and the second leakage suppression module are turned off in a black insertion stage in response to signals on the leakage control signal line, the light-emitting control module is turned off in the black insertion stage in response to voltages on the light-emitting control signal line, and the second initialization module is turned on in the black insertion stage in response to voltages on the third scanning line so as to write the voltages on the initialization signal line into the first end of the light-emitting module.

Optionally, the leakage control signal line is configured to: respectively inputting pulse signals in an initialization stage and a data writing stage in a display frame;

the second scan line is configured to: inputting pulse signals in a data writing stage in a display frame;

Preferably, in a display frame, the signal waveform input by the second scan line is the same as the signal waveform input by the leakage control signal line, the pulse signal timing input by the second scan line is later than the pulse signal timing input by the leakage control signal line, and the first pulse signal input by the second scan line overlaps with the second pulse signal timing input by the leakage control signal line.

Optionally, the first scan line is configured to: inputting pulse signals in an initialization stage in a display frame;

preferably, in a display frame, the signal waveform input by the first scan line is the same as the signal waveform input by the leakage control signal line, the pulse signal timing input by the first scan line is earlier than the pulse signal timing input by the leakage control signal line, and the second pulse signal input by the first scan line overlaps with the first pulse signal timing input by the leakage control signal line.

Optionally, the pixel circuit further includes a coupling module, a first end of the coupling module is connected to the first node, a second end of the coupling module is connected to a jump voltage, and the coupling module is used for coupling the jump voltage to the first node so as to reduce a voltage difference between a control end of the driving module and the first node in a light emitting stage;

Preferably, the pixel circuit further comprises a light emitting control module, a control end of the light emitting control module is connected with a light emitting control signal line, the light emitting control module is turned on or off in response to the voltage on the light emitting control signal line, a second end of the coupling module is connected with the light emitting control signal line, and the voltage on the light emitting control signal line is multiplexed into the jump voltage.

In a second aspect, an embodiment of the present invention provides a display panel, including a substrate, a leakage control signal line, a switching portion, and the pixel circuit of the first aspect, where the leakage control signal line, the switching portion, and the pixel circuit are all located on the substrate;

the driving module comprises a driving transistor, the first leakage suppression module comprises a first transistor, the second leakage suppression module comprises a second transistor, and the grid electrode of the first transistor and the grid electrode of the second transistor are connected with the leakage control signal line;

the first transistor is connected between the grid electrode of the driving transistor and the second transistor, the semiconductor layer of the first transistor is connected with the grid electrode of the driving transistor through the switching part, the electric leakage control signal line is positioned on the first metal layer, the switching part is positioned on the second metal layer, and the vertical projection of the electric leakage control signal line on the substrate overlaps with the vertical projection of the switching part on the substrate so as to couple the grid voltage of the driving transistor through the voltage on the electric leakage control signal line.

Optionally, the second metal layer is located on a side of the semiconductor layer of the first transistor away from the substrate, and a perpendicular projection of the adaptor portion on the substrate overlaps with a perpendicular projection of the semiconductor layer of the first transistor on the substrate.

Optionally, the semiconductor layer of the first transistor and the semiconductor layer of the second transistor are located on the same side of the semiconductor layer of the driving transistor along a first direction, the leakage control signal line extends along a second direction, a vertical projection of the semiconductor layer of the first transistor on the substrate and a vertical projection of the semiconductor layer of the second transistor on the substrate overlap with a vertical projection of the leakage control signal line on the substrate, and the first direction intersects with the second direction.

Optionally, the threshold compensation module includes a third transistor, a first pole of the first transistor is connected to the gate of the driving transistor, a second pole of the first transistor is connected to the first pole of the second transistor, the third transistor is connected between the first pole of the driving transistor and the second pole of the second transistor, the pixel circuit further includes a fourth transistor, a gate of the fourth transistor is connected to the leakage control signal line, and the fourth transistor is connected between the second transistor and the third transistor;

The semiconductor layer of the fourth transistor is positioned on the same side of the semiconductor layer of the driving transistor as the semiconductor layer of the first transistor and the semiconductor layer of the second transistor, and the vertical projection of the semiconductor layer of the fourth transistor on the substrate is overlapped with the vertical projection of the electric leakage control signal line on the substrate;

preferably, the semiconductor layer of the first transistor, the semiconductor layer of the second transistor, and the semiconductor layer of the fourth transistor are arranged in this order along the second direction.

Optionally, the pixel circuit further includes a data writing module and a fifth transistor, wherein a gate of the fifth transistor is connected to the leakage control signal line, and the fifth transistor is connected between the data line and the data writing module;

the semiconductor layer of the fifth transistor is positioned on the same side of the semiconductor layer of the driving transistor as the semiconductor layer of the first transistor and the semiconductor layer of the second transistor, and the vertical projection of the semiconductor layer of the fifth transistor on the substrate is overlapped with the vertical projection of the electric leakage control signal line on the substrate;

preferably, the semiconductor layer of the first transistor, the semiconductor layer of the second transistor, and the semiconductor layer of the fifth transistor are arranged in this order along the second direction.

Optionally, the first storage module includes a first capacitor, a first polar plate of the first capacitor is connected to the first node, and a second polar plate of the first capacitor is connected to a fixed voltage;

the second electrode plate of the first capacitor is positioned on a third metal layer, the third metal layer is positioned between the first metal layer and the second metal layer, the display panel further comprises a semiconductor part, the semiconductor part is arranged on the same layer as the semiconductor layer of the first transistor and the semiconductor layer of the second transistor, the semiconductor part is electrically connected with the semiconductor layer of the first transistor and the semiconductor layer of the second transistor, the vertical projection of the second electrode plate of the first capacitor on the substrate overlaps with the vertical projection of the semiconductor part on the substrate, and the semiconductor part is used as a first electrode plate of the first capacitor;

preferably, the initialization signal line is located in the third metal layer, the initialization signal line is connected to an initialization voltage, the initialization voltage is multiplexed to the fixed voltage, a vertical projection of the initialization signal line on the substrate overlaps with a vertical projection of the semiconductor portion on the substrate, and the initialization signal line is multiplexed to a second polar plate of the first capacitor.

In a third aspect, embodiments of the present invention provide a display panel having a display area and a non-display area, the display panel including a first scan circuit group and a plurality of rows of the pixel circuits according to the first aspect;

the pixel circuits are positioned in the display area, the first scanning circuit group is positioned in the non-display area, the first scanning circuit group comprises a plurality of cascaded first scanning circuits, each first scanning circuit generates scanning signals with sequential backward movement step by step, and the output end of each first scanning circuit is connected with at least one row of pixel circuits so as to provide the scanning signals for the pixel circuits;

in the pixel circuits in the same row, a control end of the threshold compensation module is connected with an output end of a first scanning circuit, a control end of the first leakage suppression module and a control end of the second leakage suppression module are connected with an output end of another first scanning circuit, and the first scanning circuit connected with the control end of the first leakage suppression module and the control end of the second leakage suppression module is located before the first scanning circuit connected with the control end of the threshold compensation module.

Optionally, the display panel further includes a second scan line and a leakage control signal line;

the control end of the first leakage suppression module and the control end of the second leakage suppression module in the pixel circuit in the ith row are connected with the output end of the first scanning circuit through the leakage control signal line, the control end of the threshold compensation module in the pixel circuit in the ith row is connected with the output end of the (i+2) th scanning circuit through the second scanning line, and i is larger than or equal to 1 and smaller than or equal to the total line number of the pixel circuit.

Optionally, in the pixel circuits in the same row, the control end of the first initializing module, the control end of the threshold compensating module and the control end of the first leakage suppressing module are respectively connected with different output ends of the first scanning circuits, and the first scanning circuit connected with the control end of the first initializing module is located before the first scanning circuit connected with the control end of the first leakage suppressing module and the control end of the second leakage suppressing module;

preferably, the display panel further includes a first scan line, the control end of the first initialization module in the pixel circuit of the ith row is connected to the output end of the first scan circuit through the first scan line, the control end of the first leakage suppression module in the pixel circuit of the ith row and the control end of the second leakage suppression module are connected to the output end of the i+2 th scan circuit through a leakage control signal line, the control end of the threshold compensation module in the pixel circuit of the ith row is connected to the output end of the i+4 th scan circuit through a second scan line.

Optionally, the display panel further includes a second scan circuit group and a first scan line, where the second scan circuit group is located in the non-display area, the second scan circuit group includes a plurality of cascaded second scan circuits, and each second scan circuit generates a scan signal with a sequential backward movement in sequence step by step;

the output end of the j-th second scanning circuit is connected with the control end of the first initializing module in the pixel circuits of the 2j-1 row and the 2j row through the first scanning line so as to provide the scanning signals for the control end of the first initializing module in the corresponding pixel circuit;

or, the output end of the j-th second scanning circuit is connected with the control end of the first initializing module in the j-th row of pixel circuits through the first scanning line so as to provide the scanning signal for the control end of the first initializing module in the corresponding pixel circuit;

wherein j is greater than or equal to 1 and less than or equal to the total number of the second scan circuits.

Optionally, the pixel circuit further includes a light emitting control module, the display panel further includes a light emitting control signal generating circuit group and a light emitting control signal line, the light emitting control signal generating circuit group is located in the non-display area, the light emitting control signal generating circuit group includes a plurality of cascaded light emitting control signal generating circuits, and each of the light emitting control signal generating circuits generates a light emitting control signal with a time sequence sequentially shifted backward step by step;

The output end of the kth light-emitting control signal generation circuit is connected with the control end of the light-emitting control module in the pixel circuits of the 2k-1 row and the 2k row through the light-emitting control signal line so as to provide the light-emitting control signal for the control end of the light-emitting control module in the corresponding pixel circuit;

or, the output end of the kth light-emitting control signal generating circuit is connected with the control end of the light-emitting control module in the pixel circuit of the kth row through the light-emitting control signal line so as to provide the light-emitting control signal for the control end of the light-emitting control module in the corresponding pixel circuit;

wherein k is greater than or equal to 1 and less than or equal to the total number of the light emission control signal generation circuits.

Optionally, the second scanning circuit group and the light emission control signal generation circuit group are located in the non-display region on the same side of the display region;

the display panel further includes a first clock signal line and a second clock signal line, and in the case where the number of the pixel circuits connected to each of the light emission control signal generating circuits is the same as the number of the pixel circuits connected to each of the second scanning circuits, the second scanning circuits and the light emission control signal generating circuits are both connected to the first clock signal line and the second clock signal line so that the second scanning circuits generate the scanning signals in response to signals on the first clock signal line and the second clock signal line, and the light emission control signal generating circuits generate the light emission control signals in response to signals on the first clock signal line and the second clock signal line;

Preferably, the first clock signal line and the second clock signal line have the same extending direction, the second scan circuit group is located at one side of the first clock signal line and the second clock signal line, and the light emission control signal generation circuit group is located at the other side of the first clock signal line and the second clock signal line.

According to the pixel circuit and the display panel provided by the embodiment of the invention, the first leakage suppression module is arranged between the control end of the driving module of the pixel circuit and the first node, the second leakage suppression module is arranged between the second node and the first node, the threshold compensation module is arranged between the first end of the driving module and the second node, and the first initialization module is arranged between the initialization signal line and the second node, so that the conductive paths between the control end of the driving module and the threshold compensation module and the conductive paths between the control end of the driving module and the initialization signal line are blocked in a light-emitting stage, and the leakage problem of the driving module is relieved. Through setting up the voltage of first storage module storage first node, can reduce the differential pressure of drive module's control end and first node, also reduce the differential pressure at first electric leakage suppression module both ends promptly to reduce the electric leakage of first electric leakage suppression module, thereby further alleviate drive module's electric leakage problem, help promoting drive module's control end voltage's stability, with the influence of weakening drive module's electric leakage problem to display brightness, thereby promote the display effect.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a driving timing diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention;

Fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

fig. 9 is a top view of a display panel according to an embodiment of the present invention;

fig. 10 is a cross-sectional view of the display panel of fig. 9 taken along a section line BB';

fig. 11 is a cross-sectional view of the display panel of fig. 9 taken along a section line CC';

FIG. 12 is a top view of another display panel according to an embodiment of the present invention;

fig. 13 is a cross-sectional view of the display panel of fig. 12 taken along section line DD';

fig. 14 is a sectional view of the display panel of fig. 12 taken along section line EE';

fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 16 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 18 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention;

FIG. 19 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention;

fig. 20 is a schematic structural diagram of another display panel according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As described in the background art, the existing pixel circuit generally has a problem of large leakage current, which causes unstable gate voltage of the driving transistor, thereby affecting brightness of the light emitting device and display effect of the display panel. In view of the above, the embodiment of the invention provides a pixel circuit to alleviate the influence of the leakage problem of the pixel circuit on the display brightness, thereby improving the display effect.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 1, the pixel circuit includes: the driving module 110, the light emitting module 120, the first leakage suppressing module 130, the second leakage suppressing module 140, the first storage module 150, the threshold compensating module 160, and the first initializing module 170.

The driving module 110 and the light emitting module 120 are connected between the first power line VDD and the second power line VSS, and the driving module 110 is configured to drive the light emitting module 120 according to the voltage of the control terminal G. The first leakage suppression module 130 is connected between the control terminal G of the driving module 110 and the first node N1, and is configured to suppress leakage of the control terminal G of the driving module 110. The second leakage suppression module 140 is connected between the second node N2 and the first node N1, and is configured to suppress leakage at the control terminal G of the driving module 110; the first storage module 150 is connected to the first node N1, and is configured to store a voltage of the first node N1 to reduce a voltage difference between the control terminal G of the driving module 110 and the first node N1. The threshold compensation module 160 is connected between the first end of the driving module 110 and the second node N2, and is used for compensating the threshold voltage of the driving module 110. The first initialization module 170 is connected between the initialization signal line Vref and the second node N2, and is configured to write a voltage on the initialization signal line Vref into the control terminal G of the driving module 110.

Specifically, the first power line VDD is connected to a first power voltage, the second power line VSS is connected to a second power voltage, the first power voltage is greater than the second power voltage, the first power voltage may be positive voltage, and the second power voltage may be negative voltage or 0V. The initialization signal line Vref is connected to an initialization voltage. The working phase of the pixel circuit at least comprises: an initialization phase, a data writing phase and a light emitting phase.

In the initialization stage, the first leakage suppression module 130, the second leakage suppression module 140 and the first initialization module 170 are controlled to be turned on, so that an initialization voltage on the initialization signal line Vref is sequentially transmitted to the control terminal G of the driving module 110 through the first initialization module 170, the second leakage suppression module 140 and the first leakage suppression module 130, and the voltage of the control terminal G of the driving module 110 is initialized to weaken the influence of the residual charge at the control terminal G of the driving module 110 on the display effect, and control the driving module 110 to be turned on.

In the data writing stage, the first leakage suppression module 130, the second leakage suppression module 140 and the threshold compensation module 160 are controlled to be turned on, and the data voltage is controlled to be sequentially transmitted to the control terminal G of the driving module 110 via the driving module 110, the threshold compensation module 160, the second node N2, the second leakage suppression module 140, the first node N1 and the first leakage suppression module 130, so that the voltage of the control terminal G of the driving module 110 is related to both the data voltage and the threshold voltage of the driving module 110, so that the threshold voltage of the driving module 110 is compensated while the data voltage is written into the control terminal G of the driving module 110. The first storage module 150 can store the voltage of the first node N1 to approach the voltage of the control terminal G of the driving module 110 and the first node N1 to reduce the voltage difference between the control terminal G of the driving module 110 and the first node N1.

In the light emitting stage, a discharging path is formed between the first power line VDD and the second power line VSS, and the first leakage suppressing module 130 and the second leakage suppressing module 140 are controlled to be turned off, so that the driving module 110 can generate a driving current according to the voltage of the control terminal G thereof, thereby driving the light emitting module 120 to emit light with corresponding brightness.

Since the first leakage suppressing module 130 and the second leakage suppressing module 140 are connected between the control terminal G of the driving module 110 and the threshold compensating module 160 and between the control terminal G of the driving module 110 and the first initializing module 170, in the light emitting stage, by controlling the first leakage suppressing module 130 and the second leakage suppressing module 140 to be turned off, it is helpful to block the conductive path between the control terminal G of the driving module 110 and the threshold compensating module 160 and to block the conductive path between the control terminal G of the driving module 110 and the initializing signal line Vref, so as to alleviate the leakage problem of the driving module 110. Meanwhile, the voltage of the first node N1 is stored in the first storage module 150, so that the voltage difference between the control terminal G of the driving module 110 and the first node N1, that is, the voltage difference between the two ends of the first leakage suppression module 130 can be reduced, so as to reduce the leakage current of the first leakage suppression module 130, further alleviate the leakage problem of the driving module 110, and maintain the voltage of the control terminal G of the driving module 110 stable.

In summary, according to the technical scheme of the embodiment of the invention, the first leakage suppression module is arranged between the control end of the driving module and the first node, the second leakage suppression module is arranged between the second node and the first node, the threshold compensation module is arranged between the first end of the driving module and the second node, and the first initialization module is arranged between the initialization signal line and the second node, so that the conductive path between the control end of the driving module and the threshold compensation module and the conductive path between the control end of the driving module and the initialization signal line are blocked in the light-emitting stage, and the leakage problem of the driving module is relieved. Through setting up the voltage of first storage module storage first node, can reduce the differential pressure of drive module's control end and first node, also reduce the differential pressure at first electric leakage suppression module both ends promptly to reduce the electric leakage of first electric leakage suppression module, thereby further alleviate drive module's electric leakage problem, help promoting drive module's control end voltage's stability, with the influence of weakening drive module's electric leakage problem to display brightness, thereby promote the display effect.

With continued reference to fig. 1, optionally, the pixel circuit further includes a Data writing module 180, a first end of the Data writing module 180 is connected to the Data line Data, and a second end of the Data writing module 180 is connected to the second end of the driving module 110. The Data line Data is connected to a Data voltage, and the Data writing module 180 is configured to write the Data voltage on the Data line Data into the control terminal G of the driving module 110.

With continued reference to fig. 1, alternatively, the first terminal of the first memory module 150 is connected to the first node N1, and the second terminal of the first memory module 150 is connected to a fixed voltage, which may be any constant voltage. In one embodiment, the second terminal of the first memory module 150 is connected to the initialization signal line Vref, and the initialization voltage accessed by the initialization signal line Vref is multiplexed to a fixed voltage.

Fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 2, the pixel circuit optionally further includes a second initialization module 190, the second initialization module 190 being connected between the initialization signal line and the first terminal of the light emitting module 120, the second initialization module 190 being configured to write a voltage on the initialization signal line to the first terminal of the light emitting module 120.

In one embodiment, the first initialization module 170 and the second initialization module 190 may be connected to the same initialization signal line, so as to reduce the number of signal lines in the display panel, which is beneficial to simplifying the layout of the signal lines in the display panel. In another embodiment, the initialization signal lines specifically include a first initialization signal line Vref1 and a second initialization signal line Vref2, the first initialization signal line Vref1 is connected to a first initialization voltage, the second initialization signal line Vref2 is connected to a second initialization voltage, the first initialization module 170 is connected to the first initialization signal line Vref1, and the second initialization module 190 is connected to the second initialization signal line Vref2. The advantage of this arrangement is that the magnitude of the first initializing voltage for initializing the control terminal G of the driving module 110 and the magnitude of the second initializing voltage for initializing the first terminal of the light emitting module 120 can be respectively adjusted to select appropriate voltage values for initializing the voltages of the control terminal G of the driving module 110 and the first terminal of the light emitting module 120, respectively, which is helpful for improving the display effect.

In this embodiment, the second end of the first memory module 150 may be connected to the first initialization signal line Vref1 to multiplex the first initialization voltage into a fixed voltage. Alternatively, the second terminal of the first memory module 150 may be connected to the second initialization signal line Vref2 to multiplex the second initialization voltage into a fixed voltage. Alternatively, the second terminal of the first memory module 150 may be further connected to the first power line VDD to multiplex the first power voltage accessed by the first power line VDD into a fixed voltage. By multiplexing the first initialization voltage, the second initialization voltage or the first power supply voltage to the fixed voltage to which the first memory module 150 is connected, no additional signal lines are required to be provided in the display panel to provide the fixed voltage to the first memory module 150, so that the number of signal lines in the display panel is reduced, and the layout of the signal lines in the display panel is simplified.

With continued reference to fig. 2, the pixel circuit further includes a second storage module 210, a first end of the second storage module 210 is connected to the control end G of the driving module 110, a second end of the second storage module 210 is connected to a fixed voltage, and the second storage module 210 is configured to store the voltage of the control end G of the driving module 110. The fixed voltage connected to the second terminal of the second memory module 210 may be any constant voltage, for example, a first initialization voltage, a second initialization voltage, or a first power voltage, and fig. 2 schematically illustrates a case where the second terminal of the second memory module 210 is connected to the first power line VDD and the second terminal of the second memory module 210 is connected to the first power voltage.

The pixel circuit further includes a light emitting control module 220, a control end of the light emitting control module 220 is connected to a light emitting control signal line EM, the light emitting control module 220 is connected between the first power line VDD and the light emitting module 120, and the light emitting control module 220 is configured to be turned on or off in response to a signal on the light emitting control signal line EM. The number of the light emitting control modules 220 includes 2, wherein one light emitting control module 220 is connected between the first power line VDD and the driving module 110, and the other light emitting control module 220 is connected between the driving module 110 and the light emitting module 120.

With continued reference to fig. 2, further, a control end of the first initialization module 170 is connected to the first scan line S1, a control end of the threshold compensation module 160 and a control end of the data writing module 180 are connected to the second scan line S2, and a control end of the first leakage suppression module 130 and a control end of the second leakage suppression module 140 are both connected to the leakage control signal line EMB.

The first initialization module 170 is turned on in response to the signal on the first scan line S1 during the initialization phase, and the first leakage suppression module 130 and the second leakage suppression module 140 are turned on in response to the signal on the leakage control signal line EMB during the initialization phase, so as to write the voltage on the initialization signal line Vref into the control terminal G of the driving module 110.

The Data writing module 180 and the threshold compensation module 160 are turned on in response to the signal on the second scan line S2 during the Data writing phase, and the first leakage suppressing module 130 and the second leakage suppressing module 140 are turned on in response to the signal on the leakage control signal line EMB during the Data writing phase to write the voltage on the Data line Data into the control terminal G of the driving module 110, and store the voltage of the control terminal G of the driving module 110 through the second storage module 210, and compensate the threshold voltage of the driving module 110 at the same time.

The first leakage suppression module 130 and the second leakage suppression module 140 are turned off in response to the signal on the leakage control signal line EMB during the light emitting phase to suppress leakage of the control terminal G of the driving module 110.

Fig. 3 is a schematic diagram of a driving timing of a pixel circuit according to an embodiment of the present invention, where the driving timing is suitable for driving the pixel circuit shown in fig. 1 and 2 to operate. The following is a description with reference to fig. 2 and 3. Optionally, the leakage control signal line EMB is configured to: pulse signals are respectively input in an initialization stage and a data writing stage in a display frame. The second scan line S2 is configured to: the pulse signal is input in a data writing stage within a display frame. The first scan line S1 is configured to: pulse signals are input in an initialization stage within a display frame.

Specifically, the pulse signals input from the leakage control signal line EMB, the first scanning line S1, and the second scanning line S2 are pulse signals required for controlling the conduction of the modules connected to the respective signal lines. Illustratively, when the on-levels of the first leakage suppressing module 130, the second leakage suppressing module 140, the threshold compensating module 160, the first initializing module 170, and the data writing module 180 are controlled to be low, the pulse signals input to the leakage control signal line EMB, the first scan line S1, and the second scan line S2 are low. In this way, the first leakage suppression module 130, the second leakage suppression module 140 and the first initialization module 170 can be controlled to be turned on in the initialization stage, so that the voltage on the initialization signal line Vref is written into the control terminal G of the driving module 110, the voltage of the control terminal G of the driving module 110 is initialized, the driving module 110 is turned on, and the first leakage suppression module 130, the second leakage suppression module 140, the threshold compensation module 160, the Data writing module 180 and the threshold compensation module 160 are controlled to be turned on in the Data writing stage, so that the voltage on the Data line Data is written into the control terminal G of the driving module 110, and the threshold voltage of the driving module 110 is compensated.

It can be understood that the level for controlling the conduction of each module in the pixel circuit may be either a low level or a high level, and when the level for controlling the conduction of each module is a high level, the pulse signals input by the leakage control signal line EMB, the first scan line S1 and the second scan line S2 may be high-level pulse signals, and the corresponding working principle may be understood by referring to the above embodiments and will not be described again.

In an embodiment, referring to fig. 2 and 3, in a display frame, a signal waveform input by the second scan line S2 is the same as a signal waveform input by the leakage control signal line EMB, a pulse signal timing input by the second scan line S2 is later than a pulse signal timing input by the leakage control signal line EMB, and a first pulse signal input by the second scan line S2 overlaps a timing of a second pulse signal input by the leakage control signal line EMB.

In an exemplary embodiment, in a display frame, the signals input by the second scan line S2 and the leakage control signal line EMB include two low-level pulse signals with the same time interval, the first low-level pulse signal input by the second scan line S2 overlaps with the time sequence of the second low-level pulse signal input by the leakage control signal line EMB, and the time interval corresponding to the time sequence overlapping of the pulse signals of the second scan line S2 and the leakage control signal line EMB is the time interval corresponding to the data writing stage of the pixel circuit. Because the waveforms of the signals input by the second scan line S2 and the leakage control signal line EMB are the same, the difference between the two is that the pulse signals are different in time sequence, so that the same group of cascaded scan circuits can be used for providing signals for the second scan line S2 and the leakage control signal line EMB, and the scan circuit for providing signals for the leakage control signal line EMB is positioned in front of the scan circuit for providing signals for the second scan line S2, so that the time sequence of the pulse signals input by the second scan line S2 is later than the time sequence of the pulse signals input by the leakage control signal line EMB, two groups of cascaded scan circuits are not required to be respectively provided for the second scan line S2 and the leakage control signal line EMB, which is beneficial to reducing the space occupied by the scan circuit in the display panel, thereby realizing narrow frame design.

Fig. 4 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention, where the driving timing is suitable for driving the pixel circuit shown in fig. 1 and 2 to operate. The following is a description with reference to fig. 2 and 4. Optionally, the control terminal of the second initialization module 190 is connected to the third scan line S3, the first leakage suppression module 130 and the second leakage suppression module 140 are turned off in the black insertion stage in response to the signal on the leakage control signal line EMB, the light emitting control module 220 is turned off in the black insertion stage in response to the voltage on the light emitting control signal line EM, and the second initialization module 190 is turned on in the black insertion stage in response to the voltage on the third scan line S3 to write the voltage on the initialization signal line (e.g., the second initialization signal line Vref 2) into the first terminal of the light emitting module 120.

Illustratively, in the black insertion stage in each display frame, a level signal, such as a high level signal, for controlling the light emission control module 220 to turn off is provided to the light emission control signal line EM to control the conductive path between the first power line VDD and the second power line VSS to be disconnected, a level signal, such as a high level signal, for controlling the first leakage suppressing module 130 and the second leakage suppressing module 140 to turn off is provided to the leakage control signal line EMB to block the leakage path of the control terminal G of the driving module 110, so that the voltage of the control terminal G of the driving module 110 remains stable, a signal, such as a low level pulse signal, for controlling the second initializing module 190 to turn on is provided to the third scanning line S3 to write the voltage on the second initializing signal line Vref2 to the first terminal of the light emitting module 120 through the second initializing module 190, the voltage of the first terminal of the light emitting module 120 is initialized, the current of the light emitting module 120 is rapidly reduced, and the light emitting module 120 is controlled to stop light emission, so that the display panel can fully display black images.

Alternatively, the first scan line S1 and the third scan line S3 are configured to input pulse signals having the same waveform and timing. The advantage of this arrangement is that the same scanning circuit can be used to provide the same signal for the first scanning line S1 and the third scanning line S3, and two groups of cascaded scanning circuits are not required to be separately arranged to provide signals for the first scanning line S1 and the third scanning line S3, so that the space occupied by the scanning circuits in the display panel is reduced, and the narrow frame design is realized.

Referring to fig. 2, on the basis of the above embodiments, the driving module 110 includes the driving transistor DT, the light emitting module 120 includes the light emitting device D1, the first leakage suppressing module 130 includes the first transistor T1, the second leakage suppressing module 140 includes the second transistor T2, the threshold compensating module 160 includes the third transistor T3, the first initializing module 170 includes the sixth transistor T6, the data writing module 180 includes the seventh transistor T7, the second initializing module 190 includes the eighth transistor T8, the light emitting control module 220 includes the ninth transistor T9 and the tenth transistor T10, the first storing module 150 includes the first capacitor C1, and the second storing module 210 includes the second capacitor C2.

The gate of the first transistor T1 and the gate of the second transistor T2 are connected to the leakage control signal line EMB, the first pole of the first transistor T1 is connected to the gate of the driving transistor DT, the second pole of the first transistor T1 is connected to the first pole of the second transistor T2, and the first transistor T1 and the second transistor T2 are connected to the first node N1. The gate of the third transistor T3 is connected to the second scan line S2, the first pole of the third transistor T3 is connected to the first pole of the driving transistor DT, the second pole of the third transistor T3 is connected to the second pole of the second transistor T2, and the second transistor T2 and the third transistor T3 are connected to the second node N2. The gate of the sixth transistor T6 is connected to the first scan line S1, the first pole of the sixth transistor T6 is connected to the first initialization signal line Vref1, and the second pole of the sixth transistor T6 is connected to the second node N2. The gate of the seventh transistor T7 is connected to the second scan line S2, the first pole of the seventh transistor T7 is connected to the Data line Data, and the second pole of the seventh transistor T7 is connected to the second pole of the driving transistor DT. The gate of the eighth transistor T8 is connected to the third scan line S3, the first electrode of the eighth transistor T8 is connected to the second initialization signal line Vref2, and the second electrode of the eighth transistor T8 is connected to the first electrode (e.g., anode) of the light emitting device D1. The gates of the ninth transistor T9 and the tenth transistor T10 are connected to the emission control signal line EM, and the ninth transistor T9, the driving transistor DT, the tenth transistor T10, and the light emitting device D1 are sequentially connected between the first power line VDD and the second power line VSS. The first plate of the first capacitor C1 is connected to the first node N1, and the second plate of the first capacitor C1 is connected to a fixed voltage, for example, the second plate of the first capacitor C1 may be connected to the first power line VDD, the first initialization signal line Vref1 or the second initialization signal line Vref2, so as to be connected to a fixed voltage on a corresponding signal line. The first plate of the second capacitor C2 is connected to the gate of the driving transistor DT, and the second plate of the second capacitor C2 is connected to a fixed voltage, for example, the second plate of the second capacitor C2 may be connected to the first power line VDD to be connected to the first power voltage.

Among them, the Light Emitting device D1 includes an Organic Light-Emitting Diode (OLED), a Micro-scale Light Emitting Diode (Micro-LED), and the like. The transistors in the pixel circuit may be P-type transistors or N-type transistors. In the case where each module in the pixel circuit is constituted by only one transistor, the gate of the transistor may serve as the control terminal of the corresponding module, the first pole of the transistor may serve as the first terminal of the corresponding module, the second pole of the transistor may serve as the second terminal of the corresponding module, and one of the first pole and the second pole of the transistor is the source, and the other is the drain.

The operation principle of the pixel circuit will be described below with reference to fig. 2 to 4, taking P-type transistors as examples of each transistor in the pixel circuit.

Illustratively, in the first stage T1, the emission control signal line EM inputs a low level signal, the ninth transistor T9, the tenth transistor T10, and the driving transistor DT are turned on, and the remaining transistors are turned off, and the driving transistor DT generates a driving current according to its gate voltage to drive the light emitting device D1 to emit light.

In the second stage T2, the emission control signal line EM inputs a high level signal, and the ninth transistor T9 and the tenth transistor T10 are turned off.

In the third stage T3, the first scan line S1, the third scan line S3, and the leakage control signal line EMB input low level signals, the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned on, and the first initialization voltage on the first initialization signal line Vref1 is sequentially transmitted to the gate of the driving transistor DT through the sixth transistor T6, the second transistor T2, and the first transistor T1, so as to initialize the gate voltage of the driving transistor DT, to reduce the influence of the residual charge on the gate of the driving transistor DT on the display effect, and to control the driving transistor DT to be turned on. The eighth transistor T8 is turned on, and the second initialization voltage on the second initialization signal line Vref2 is transmitted to the first electrode of the light emitting device D1 through the eighth transistor T8, and the voltage of the first electrode of the light emitting device D1 is initialized, so as to reduce the influence of the residual charge of the first electrode of the light emitting device D1 on the display effect.

Subsequently, the signal input from the leakage control signal line EMB transitions from a low level signal to a high level signal, and both the first transistor T1 and the second transistor T2 are turned off.

The fourth stage T4 is a data writing stage, and in the fourth stage T4, the first scan line S1 and the third scan line S3 input high level signals, and the sixth transistor T6 and the eighth transistor T8 are turned off. The second scan line S2 and the leakage control signal line EMB input low level signals, the first transistor T1, the second transistor T2, the third transistor T3 and the seventh transistor T7 are turned on, the Data voltage on the Data line Data is written into the gate of the driving transistor DT sequentially through the seventh transistor T7, the driving transistor DT, the third transistor T3, the second node N2, the second transistor T2, the first node N1 and the first transistor T1, so that the gate voltage of the driving transistor DT is related to the Data voltage and the threshold voltage of the driving transistor DT, and simultaneously, the voltage of the first node N1 is stored through the first capacitor C1 and the gate voltage of the driving transistor DT is stored through the second capacitor C2.

In the fifth stage T5, when the light emission control signal line EM, the first scan line S1, the second scan line S2, the third scan line S3, and the leakage control signal line EMB all input high level signals, the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned off. When the second scan line S2 inputs a low level, the third transistor T3 and the seventh transistor T7 are turned on, and at this time, since the first transistor T1 and the second transistor T2 are turned off, the gate voltage of the driving transistor DT is not affected.

In the sixth stage T6, the light emission control signal line EM receives a low level signal, the ninth transistor T9, the tenth transistor T10, and the driving transistor DT are turned on, the remaining transistors are turned off, and the driving transistor DT generates a driving current according to its gate voltage, thereby driving the light emitting device D1 to emit light. Since the gate voltage of the driving transistor DT is related to the data voltage and the threshold voltage of the driving transistor DT, the influence of the threshold voltage of the driving transistor DT on the driving current is eliminated, thereby realizing the threshold voltage compensation of the driving transistor DT to improve the display uniformity. Since the first transistor T1 and the second transistor T2 are turned off, the conduction path between the driving transistor DT and the third transistor T3 is blocked, and the conduction path between the driving transistor DT and the first initialization signal line Vref1 is blocked, so that the leakage current channel of the gate of the driving transistor DT is reduced, and the leakage current of the gate of the driving transistor DT is reduced. Because the first capacitor C1 stores the voltage of the first node N1, the voltage difference between two poles of the first transistor T1 is smaller, so as to reduce the leakage current of the first transistor T1, thereby further alleviating the leakage problem of the driving transistor DT, keeping the gate voltage of the driving transistor DT stable, reducing the influence of the leakage problem of the driving transistor DT on the brightness of the light emitting device D1, improving the flicker phenomenon of the display panel, and enhancing the display effect.

The seventh stage T7 is a black insertion stage, and in the seventh stage T7, the signal input from the emission control signal line EM transitions from a low level signal to a high level signal, and the ninth transistor T9 and the tenth transistor T10 are turned off. When the first scan line S1 and the third scan line S3 input a low level signal, the sixth transistor T6 and the eighth transistor T8 are turned on, the second initialization voltage on the second initialization signal line Vref2 is transmitted to the first electrode of the light emitting device D1 through the eighth transistor T8, the voltage of the first electrode of the light emitting device D1 is initialized, the current of the light emitting device D1 is rapidly reduced, and the light emitting device D1 is controlled to stop emitting light, so that the display panel can sufficiently display a black picture. Meanwhile, since the first transistor T1 and the second transistor T2 are turned off, the voltage on the first initialization signal line Vref1 cannot be transmitted to the gate of the driving transistor DT, so that the gate voltage of the driving transistor DT is maintained, and the voltage difference between the two electrodes of the first transistor T1 is smaller, so that the leakage current of the first transistor T1 can be reduced, so as to maintain the stability of the gate voltage of the driving transistor DT.

In the eighth stage t8, the emission control signal line EM receives a low-level signal, and the first scan line S1, the second scan line S2, the third scan line S3, and the leakage control signal line EMB each receive a high-level signal. The ninth transistor T9, tenth transistor T10, and driving transistor DT are turned on, and the remaining transistors are turned off, and the driving transistor DT generates a driving current according to a voltage held by its gate to drive the light emitting device D1 to emit light.

According to the technical scheme of the embodiment, the seventh stage t7 (namely the black inserting stage) and the eighth stage t8 (namely the other light emitting stage) are added after the sixth stage t6 (namely the light emitting stage) in each display frame, which is equivalent to increasing the light emitting times of the light emitting device D1 in each display frame, the refreshing frequency of the display panel is improved in visual effect, the actual refreshing frequency is kept unchanged, and meanwhile, the conversion of the brightness component with lower frequency and which is sensitive to human eyes into the brightness component with higher frequency and which is insensitive to human eyes is facilitated, so that the flicker phenomenon of the display panel under the condition of lower refreshing frequency is improved.

Referring to fig. 2 to 4, alternatively, when the refresh frequency of the current display frame is lower than the preset frequency, the frequency of the pulse signal input by the third scan line S3 is configured to be an integer multiple of the refresh frequency of the current display frame, the frequency of the pulse signals input by the second scan line S2 and the leakage control signal line EMB are both configured to be the same as the refresh frequency of the current display frame, the frequency of the pulse signal input by the emission control signal line EM is configured to be an integer multiple of the refresh frequency of the current display frame, and the frequency of the pulse signals input by the third scan line S3 and the emission control signal line EM are the same.

The preset frequency is a lower frequency, and specific values of the preset frequency can be set according to requirements. For example, the preset frequency may be a frequency below 60 Hz. The refresh frequency of the current display frame refers to the actual refresh frequency of the current display frame, i.e., the frequency at which the gate of the driving transistor DT writes the data voltage. Since the pulse signals input from the second scan line S2 and the leakage control signal line EMB come just before the sixth stage t6, the frequency of the pulse signals input from the second scan line S2 and the leakage control signal line EMB can be configured to be the same as the refresh frequency of the current display frame. Since the pulse signals input to the third scan line S3 come before the sixth stage t6 and the seventh stage t7, respectively, and the pulse signals input to the emission control signal line EM come in the sixth stage t6 and the eighth stage t8, respectively, the frequencies of the pulse signals input to the third scan line S3 and the emission control signal line EM can be each configured to be an integer multiple of the refresh frequency of the current display frame, and the frequencies of the pulse signals input to the third scan line S3 and the emission control signal line EM are the same.

Fig. 5 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention, where the driving timing is suitable for driving the pixel circuit shown in fig. 1 and 2 to operate. In another embodiment, referring to fig. 2 and 5, in a display frame, the signal waveform input by the first scan line S1 is the same as the signal waveform input by the leakage control signal line EMB, the pulse signal timing input by the first scan line S1 is earlier than the pulse signal timing input by the leakage control signal line EMB, and the second pulse signal input by the first scan line S1 overlaps with the first pulse signal timing input by the leakage control signal line EMB.

In an exemplary embodiment, in a display frame, the signals input by the first scan line S1 and the leakage control signal line EMB include two low-level pulse signals with the same time interval, the second low-level pulse signal input by the first scan line S1 overlaps with the time sequence of the first low-level pulse signal input by the leakage control signal line EMB, and the time interval corresponding to the time sequence overlapping of the pulse signals of the first scan line S1 and the leakage control signal line EMB is the time interval corresponding to the initialization stage of the pixel circuit. Because the waveforms of the signals input by the first scan line S1 and the leakage control signal line EMB are the same, the difference between the waveforms is only that the pulse signals are different in time sequence, so that the same group of cascaded scan circuits can be used for providing signals for the first scan line S1 and the leakage control signal line EMB, and the scan circuit for providing signals for the first scan line S1 is positioned before the scan circuit for providing signals for the leakage control signal line EMB, so that the time sequence of the pulse signals input by the first scan line S1 is earlier than the time sequence of the pulse signals input by the leakage control signal line EMB, two groups of cascaded scan circuits are not required to be respectively provided for the first scan line S1 and the leakage control signal line EMB, which is beneficial to reducing the space occupied by the scan circuit in the display panel, thereby realizing narrow frame design.

Further, in a display frame, waveforms of signals input by the first scan line S1, the second scan line S2, and the leakage control signal line EMB are the same, a pulse signal timing input by the first scan line S1 is earlier than a pulse signal timing input by the leakage control signal line EMB, a pulse signal timing input by the leakage control signal line EMB is earlier than a pulse signal timing input by the second scan line S2, a second pulse signal input by the first scan line S1 overlaps a timing of a first pulse signal input by the leakage control signal line EMB, and a second pulse signal input by the leakage control signal line EMB overlaps a timing of a first pulse signal input by the second scan line S2, that is, pulse timings of the leakage control signal line EMB and the first scan line S1 overlap in a third phase t3 (i.e., an initialization phase), and a pulse timing of the leakage control signal line EMB and the second scan line S2 overlap in a fourth phase t4 (i.e., a data writing phase). The advantage of this arrangement is that the same set of cascaded scan circuits can be used to provide signals to the first scan line S1, the second scan line S2 and the leakage control signal line EMB, and the scan circuit providing signals to the first scan line S1 is located before the scan circuit providing signals to the leakage control signal line EMB, and the scan circuit providing signals to the second scan line S2 is located before the scan circuit providing signals to the first scan line S1, the second scan line S2 and the leakage control signal line EMB, so as to meet the signal and time requirements of the first scan line S1, the second scan line S2 and the leakage control signal line EMB, and three sets of cascaded scan circuits are not required to provide signals to the first scan line S1, the second scan line S2 and the leakage control signal line EMB respectively, which is beneficial to reducing the space occupied by the scan circuits in the display panel, thereby realizing a narrow frame design.

The driving timing driving pixel circuit shown in fig. 5 and fig. 3 operates in a similar manner, and can be understood with reference to the above embodiment, and will not be described herein.

Fig. 6 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention, where the driving timing is suitable for driving the pixel circuit shown in fig. 1 and 2 to operate. Referring to fig. 2 and 6, in a seventh stage T7 (i.e., black insertion stage), the light emission control signal line EM receives a high level signal, and the first scan line S1, the second scan line S2, the third scan line S3, and the leakage control signal line EMB each receive a high level signal, and the ninth transistor T9 and the tenth transistor T10 are controlled to be turned off, so that the light emitting device D1 can be controlled to stop light emission in the black insertion stage, and the display panel can display a black screen. In this embodiment, when the refresh frequency of the current display frame is lower than the preset frequency, the frequency of the pulse signal input by the light emission control signal line EM is configured to be an integer multiple of the refresh frequency of the current display frame, and the frequencies of the pulse signals input by the first scan line S1, the second scan line S2, and the third scan line S3 are all configured to be the same as the refresh frequency of the current display frame.

Fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 7, the pixel circuit further includes a coupling module 230, a first end of the coupling module 230 is connected to the first node N1, a second end of the coupling module 230 is connected to the jump voltage, and the coupling module 230 is used for coupling the jump voltage to the first node N1 to reduce a voltage difference between the control end G of the driving module 110 and the first node N1 during the light emitting period.

Specifically, the second terminal of the coupling module 230 is connected to the second terminal of the second terminal. When the leakage control signal line EMB connected to the gates of the first transistor T1 and the second transistor T2 has a level jump, the voltage of the first node N1 is coupled, so as to increase the voltage difference between the control terminal G of the driving module 110 and the first node N1. The coupling module 230 couples the jump voltage to the first node N1, so that the voltage of the first node N1 can be adjusted to reduce the voltage difference between the control terminal G of the driving module 110 and the first node N1 during the light emitting phase, thereby reducing the leakage current of the first transistor T1 and maintaining the stability of the voltage of the control terminal G of the driving module 110.

In one embodiment, a second terminal of the coupling module 230 may be connected to the emission control signal line EM, and the voltage on the emission control signal line EM is multiplexed into the transition voltage. The driving timing shown in fig. 5 is also suitable for driving the pixel circuit in fig. 7 to operate, for example, when the fourth stage T4 is finished, the signal input by the leakage control signal line EMB jumps from a low level signal to a high level signal, so as to couple the voltage of the first node N1, so that the voltage of the first node N1 is higher than the gate voltage of the driving transistor DT, and when the sixth stage T6 (i.e. the light emitting stage) is started, the signal input by the light emitting control signal line EM jumps from a high level signal to a low level signal, and the coupling module 230 can couple the voltage of the first node N1 according to the voltage jump at the second end thereof to pull down the voltage of the first node N1, so as to reduce the voltage difference between the gate of the driving transistor DT and the first node N1, and reduce the leakage current of the first transistor T1, so as to maintain the stability of the voltage of the control end G of the driving module 110.

In practical applications, the jump voltage accessed by the second end of the coupling module 230 is not limited to the voltage on the emission control signal line EM, and the jump voltage may be any voltage that makes a level jump at the beginning of the sixth stage t6, and the level jump trend of the jump voltage is opposite to the level jump trend of the leakage control signal line EMB at the end of the fourth stage t 4.

With continued reference to fig. 7, further, the coupling module 230 includes a third capacitor C3, a first plate of the third capacitor C3 is connected to the first node N1, and a second plate of the third capacitor C3 is connected to the jump voltage, for example, the second plate of the third capacitor C3 may be connected to the emission control signal line EM to multiplex the voltage on the emission control signal line EM into the jump voltage.

With continued reference to fig. 7, the pixel circuit optionally further includes a fourth transistor T4, a gate of the fourth transistor T4 is connected to the leakage control signal line EMB, and the fourth transistor T4 is connected between the second node N2 and the third transistor T3. By providing the fourth transistor T4 between the second node N2 and the third transistor T3, the fourth transistor T4 can be turned off in response to the signal on the leakage control signal line EMB during the light emitting period, thereby further blocking the leakage path between the gate of the driving transistor DT and the third transistor T3, helping to maintain the gate voltage of the driving transistor DT stable.

Fig. 8 is a schematic diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 8, in another embodiment, the third transistor T3 may also be connected between the first pole of the driving transistor DT and the first node N1. In the light emitting stage, by controlling the first transistor T1 and the second transistor T2 to be turned off in response to the signal on the drain control signal line EMB, the drain path between the gate of the driving transistor DT and the third transistor T3 can be blocked by the first transistor T1, and the drain path between the gate of the driving transistor DT and the first initialization signal line Vref1 can be blocked by the first transistor T1 and the second transistor T2, helping to maintain the gate voltage of the driving transistor DT stable.

With continued reference to fig. 8, further, the pixel circuit further includes a fifth transistor T5, a gate of the fifth transistor T5 is connected to the leakage control signal line EMB, and the fifth transistor T5 is connected between the Data line Data and the Data writing module 180. The driving timings shown in fig. 5 and 6 are also suitable for driving the pixel circuit in fig. 8, and for example, in the fourth stage T4 (i.e. the Data writing stage) described with reference to fig. 5, 6 and 8, the fifth transistor T5 is turned on in response to the low level signal on the leakage control signal line EMB, so that the Data voltage on the Data line Data can be transmitted to the Data writing module 180 through the fifth transistor T5, and the Data writing module 180 is not affected to write the Data voltage to the control terminal G of the driving module 110. In the seventh phase T7 (i.e. black insertion phase), the fifth transistor T5 is turned off in response to the low level signal on the leakage control signal line EMB to avoid the Data voltage on the Data line Data from being transmitted to the Data writing module 180, thereby avoiding affecting the voltage of the control terminal G of the driving module 110.

Based on the same inventive concept, the embodiment of the invention also provides a display panel, which comprises the pixel circuit in any embodiment, so that the display panel has corresponding functional modules and beneficial effects in the pixel circuit.

Fig. 9 is a top view of a display panel according to an embodiment of the present invention, in which only a part of the structure of the display panel is shown. Fig. 10 is a cross-sectional view of the display panel of fig. 9 taken along a section line BB'. Fig. 11 is a cross-sectional view of the display panel of fig. 9 taken along the section line CC'. Referring to fig. 2 and fig. 9 to fig. 11, the display panel includes a substrate 10, a leakage control signal line EMB, a switching portion 310, and a pixel circuit according to any of the above embodiments, wherein the leakage control signal line EMB, the switching portion 310, and the pixel circuit are all disposed on the substrate 10.

The driving module 110 includes a driving transistor DT, the first leakage suppressing module 130 includes a first transistor T1, and the second leakage suppressing module 140 includes a second transistor T2, and a gate of the first transistor T1 and a gate of the second transistor T2 are connected to a leakage control signal line EMB. The first transistor T1 is connected between the gate of the driving transistor DT and the second transistor T2, the semiconductor layer 20b of the first transistor T1 is connected to the gate of the driving transistor DT through the junction 310, the leakage control signal line EMB is located in the first metal layer 30, the junction 310 is located in the second metal layer 40, and the vertical projection of the leakage control signal line EMB on the substrate 10 overlaps with the vertical projection of the junction 310 on the substrate 10, so as to couple the gate voltage of the driving transistor DT through the voltage on the leakage control signal line EMB.

Specifically, the display panel may be an organic light emitting diode OLED display panel or a Micro-scale light emitting diode Micro-LED display panel, or the like. The substrate 10 may provide cushioning, protection, or support for the display panel. The substrate 10 may be a flexible substrate, and the material of the flexible substrate may be Polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or the like, or may be a mixture of the above materials. The substrate 10 may be a hard substrate made of a material such as glass. The display panel further includes a semiconductor layer 20 on one side of the substrate 10, including the semiconductor layer of each thin film transistor in the pixel circuit. The first metal layer 30 is located at a side of the semiconductor layer 20 away from the substrate 10, and the gate electrodes of the thin film transistors in the pixel circuit are all located in the first metal layer 30, and the first metal layer 30 and the second metal layer 40 are disposed in different layers.

Fig. 9 shows regions where semiconductor layers of the transistors are located in reference numerals of the transistors in the pixel circuit. The vertical projection of the leakage control signal line EMB on the substrate 10 overlaps with the vertical projection of the semiconductor layer 20b of the first transistor T1 on the substrate 10, the semiconductor layer 20b of the first transistor T1 on one side of the leakage control signal line EMB includes a source region of the first transistor T1, the semiconductor layer 20b of the first transistor T1 on the other side of the leakage control signal line EMB includes a drain region of the first transistor T1, the semiconductor layer 20b of the first transistor T1 on one side of the leakage control signal line EMB is connected to the semiconductor layer 20c of the second transistor T2, the semiconductor layer 20b of the first transistor T1 on the other side of the leakage control signal line EMB is connected to the gate of the driving transistor DT through the transfer portion 310, so that the first transistor T1 is connected between the gate of the driving transistor DT and the second transistor T2, and the semiconductor layer 20b of the first transistor T1 and the gate of the driving transistor DT are electrically connected through the transfer portion 310.

By providing that the vertical projection of the leakage control signal line EMB on the substrate 10 overlaps with the vertical projection of the switching part 310 on the substrate 10, the gate voltage of the driving transistor DT to which the switching part 310 is connected can be coupled when the voltage on the leakage control signal line EMB jumps. For example, before the pixel circuit enters the light emitting stage, when the signal on the leakage control signal line EMB transitions from a low level signal to a high level signal, the leakage control signal line EMB can couple the gate voltage of the driving transistor DT to raise the gate voltage of the driving transistor DT, thereby compensating for the voltage loss of the gate of the driving transistor DT due to the leakage to ensure the display effect.

Referring to fig. 2 and fig. 9 to fig. 11, optionally, the second metal layer 40 is located on a side of the semiconductor layer 20b of the first transistor T1 away from the substrate 10, and the vertical projection of the adaptor 310 on the substrate 10 overlaps with the vertical projection of the semiconductor layer 20b of the first transistor T1 on the substrate 10. The advantage of this arrangement is that the transfer portion 310 can cover at least a part of the area of the semiconductor layer 20b of the first transistor T1, so that the semiconductor layer 20b of the first transistor T1 is shielded by the transfer portion 310, which is helpful to reduce the leakage current of the first transistor T1, thereby improving the stability of the gate voltage of the driving transistor DT.

Further, the first metal layer 30 is located on a side of the semiconductor layer 20b of the first transistor T1 away from the substrate 10, the second metal layer 40 is located on a side of the first metal layer 30 away from the substrate 10, for example, the source/drain of the driving transistor DT is located on the second metal layer 40, and the junction 310 may be disposed on the same layer as the source/drain of the driving transistor DT.

Referring to fig. 2, 9 to 11, alternatively, in a first direction X, the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2 are located on the same side of the semiconductor layer 20a of the driving transistor DT, the leakage control signal line EMB extends in a second direction Y, and a vertical projection of the semiconductor layer 20b of the first transistor T1 on the substrate 10 and a vertical projection of the semiconductor layer 20c of the second transistor T2 on the substrate 10 overlap with a vertical projection of the leakage control signal line EMB on the substrate 10, and the first direction X intersects with the second direction Y. In this way, by providing one leakage control signal line EMB extending in the same direction and overlapping the semiconductor layer 20 on the same side as the semiconductor layer 20a of the driving transistor DT, the first transistor T1 and the second transistor T2 can be formed simultaneously, which contributes to simplifying the layout structure of the pixel circuit.

Referring to fig. 7 and 9 to 11, optionally, the threshold compensation module 160 includes a third transistor T3, the pixel circuit further includes a fourth transistor T4, a gate of the fourth transistor T4 is connected to the leakage control signal line EMB, and the fourth transistor T4 is connected between the second transistor T2 and the third transistor T3. The semiconductor layer 20d of the fourth transistor T4 is located on the same side of the semiconductor layer 20a of the driving transistor DT as the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2, and the vertical projection of the semiconductor layer 20d of the fourth transistor T4 on the substrate 10 overlaps with the vertical projection of the leakage control signal line EMB on the substrate 10. By providing one leakage control signal line EMB extending in the same direction, overlapping with the semiconductor layer 20 on the same side as the semiconductor layer 20a of the driving transistor DT, the first transistor T1, the second transistor T2, and the fourth transistor T4 can be formed at the same time, which helps to simplify the layout structure of the pixel circuit.

Further, the semiconductor layer 20b of the first transistor T1, the semiconductor layer 20c of the second transistor T2, and the semiconductor layer 20d of the fourth transistor T4 are sequentially arranged in the second direction Y to facilitate connection between the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4.

Referring to fig. 7 and fig. 9 to fig. 11, optionally, the first storage module 150 includes a first capacitor C1, a first plate C11 of the first capacitor C1 is connected to the first node N1, and a second plate C12 of the first capacitor C1 is connected to a fixed voltage. The second plate C12 of the first capacitor C1 is located in the third metal layer 50, the third metal layer 50 is located between the first metal layer 30 and the second metal layer 40, the display panel further includes a semiconductor portion 20f, the semiconductor portion 20f is disposed in the same layer as the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20C of the second transistor T2, and the semiconductor portion 20f is electrically connected to the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20C of the second transistor T2, and a vertical projection of the second plate C12 of the first capacitor C1 on the substrate 10 overlaps a vertical projection of the semiconductor portion 20f on the substrate 10, and the semiconductor portion 20f serves as the first plate C11 of the first capacitor C1.

Since the semiconductor portion 20f is electrically connected to the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20C of the second transistor T2, by using the semiconductor portion 20f in the semiconductor layer 20 as the first electrode plate C11 of the first capacitor C1, the first capacitor C1 can be electrically connected to the first transistor T1 and the second transistor T2, a metal structure is not required to be provided in the first metal layer 30 as the first electrode plate C11 of the first capacitor C1, and the first electrode plate C11 of the first capacitor C1 is not required to be electrically connected to the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20C of the second transistor T2 by punching, which contributes to simplifying the manufacturing process of the display panel.

Further, the first initializing signal line Vref1 is located in the third metal layer 50, the first initializing signal line Vref1 is connected to a first initializing voltage, the first initializing voltage is multiplexed to a fixed voltage connected to the second plate C12 of the first capacitor C1, the vertical projection of the first initializing signal line Vref1 on the substrate 10 overlaps with the vertical projection of the semiconductor portion 20f on the substrate 10, and the first initializing signal line Vref1 is multiplexed to the second plate C12 of the first capacitor C1. The advantage of this arrangement is that the first capacitor C1 can be formed using the first initialization signal line Vref1 and the semiconductor section 20f, without providing the first initialization signal line Vref1 and the second plate C12 of the first capacitor C1, respectively, which contributes to saving the wiring space of the display panel.

Further, the second storage module 210 includes a second capacitor C2, a first plate C21 of the second capacitor C2 is connected to the gate of the driving transistor DT, and a second plate C22 of the second capacitor C2 is connected to a fixed voltage. The first plate C21 of the second capacitor C2 is located in the first metal layer 30, and the second plate C22 of the second capacitor C2 is located in the third metal layer 50.

Fig. 12 is a top view of another display panel provided in an embodiment of the present invention, in which only a part of the structure of the display panel is shown. Fig. 13 is a cross-sectional view of the display panel of fig. 12 taken along line DD'. Fig. 14 is a sectional view of the display panel of fig. 12 taken along section line EE'.

Referring to fig. 8, 12 to 14, the pixel circuit optionally further includes a fifth transistor T5, a gate of the fifth transistor T5 is connected to the leakage control signal line EMB, and the fifth transistor T5 is connected between the Data line Data and the Data writing module 180. The semiconductor layer 20e of the fifth transistor T5 is located on the same side of the semiconductor layer 20a of the driving transistor DT as the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2, and a vertical projection of the semiconductor layer 20e of the fifth transistor T5 on the substrate 10 overlaps a vertical projection of the leakage control signal line EMB on the substrate 10. By providing one leakage control signal line EMB extending in the same direction, overlapping with the semiconductor layer 20 on the same side as the semiconductor layer 20a of the driving transistor DT, the first transistor T1, the second transistor T2, and the fifth transistor T5 can be formed at the same time, which helps to simplify the layout structure of the pixel circuit.

Further, the semiconductor layer 20b of the first transistor T1, the semiconductor layer 20c of the second transistor T2, and the semiconductor layer 20e of the fifth transistor T5 are sequentially arranged in the second direction Y so as to facilitate electrical connection between the transistors.

In this embodiment, the semiconductor portion 20f may be used as the first plate C11 of the first capacitor C1, the second plate C12 of the first capacitor C1 is located on the third metal layer 50, and the first power line VDD is electrically connected to the second plate C12 of the first capacitor C1, so that the first power voltage input by the first power line VDD is used as the fixed voltage to which the second plate C12 of the first capacitor C1 is connected.

Based on the same inventive concept, the embodiment of the invention also provides a display panel, which comprises the pixel circuit in any embodiment, so that the display panel has corresponding functional modules and beneficial effects in the pixel circuit. Fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Referring to fig. 15, the display panel has a display area AA and a non-display area NAA, and includes a first scanning circuit group and a plurality of rows of the pixel circuits 100 in any of the above-described embodiments. The pixel circuits 100 are located in the display area AA, the first scanning circuit group is located in the non-display area NAA, the first scanning circuit group includes a plurality of cascaded first scanning circuits 200, each first scanning circuit 200 generates a scanning signal with a time sequence shifted backward in sequence step by step, and an output terminal OUT of each first scanning circuit 200 is connected to at least one row of pixel circuits 100 to provide the scanning signal to the pixel circuits 100.

In the pixel circuits 100 of the same row, the control terminal of the threshold compensation module 160 is connected to the output terminal OUT of one first scan circuit 200, the control terminal of the first leakage suppression module 130 and the control terminal of the second leakage suppression module 140 are connected to the output terminal OUT of the other first scan circuit 200, and the first scan circuit 200, in which the control terminal of the first leakage suppression module 130 and the control terminal of the second leakage suppression module 140 are connected, is located before the first scan circuit 200, in which the control terminal of the threshold compensation module 160 is connected.

Specifically, the start signal terminal SIN1 of the 1 st first scan circuit 200 in the first scan circuit group is connected to the first start signal line 410, and the first start signal line 410 inputs a first start signal, which is a pulse signal. The first scanning circuit 200 is configured to shift back the timing of the pulse signal input from the initial signal terminal SIN1 to obtain a scanning signal, and provide the scanning signal to the corresponding pixel circuit 100 through the output terminal OUT. In each adjacent two-stage first scan circuit 200, the output terminal OUT of the previous first scan circuit 200 is connected to the start signal terminal SIN1 of the next first scan circuit 200, so that the scan signal output by the previous first scan circuit 200 is used as the start signal of the next first scan circuit 200, so that each first scan circuit 200 in the first scan circuit group can output the scan signal with the time sequence shifted backward in sequence step by step.

Referring to fig. 2, 3 and 15, specifically, the display panel further includes a second scan line S2 and a leakage control signal line EMB, and in the pixel circuits 100 of the same row: the control end of the threshold compensation module 160 of each pixel circuit 100 is connected to the output end OUT of one first scan circuit 200 through the second scan line S2, the control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140 of each pixel circuit 100 are connected to the output end OUT of the other first scan circuit 200 through the leakage control signal line EMB, and the first scan circuit 200, in which the control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140 are connected, is located before the first scan circuit 200, in which the control end of the threshold compensation module 160 is connected.

The advantage of this arrangement is that the scan signal can be provided to the leakage control signal line EMB connected to the same row of pixel circuits 100 through one first scan circuit 200 in the first scan circuit group, and the scan signal can be provided to the second scan line S2 connected to the row of pixel circuits 100 through the other first scan circuit 200 located behind the first scan circuit 200, so that the pulse signal with the same waveform is provided to the second scan line S2 and the leakage control signal line EMB in a display frame, and the pulse signal timing input by the second scan line S2 is later than the pulse signal timing input by the leakage control signal line EMB, so that the leakage control signal line EMB can respectively input the pulse signal in an initialization stage and a data writing stage in a display frame, and the second scan line S2 can input the pulse signal in a data writing stage to satisfy the operation timing requirement of the pixel circuits.

The two first scanning circuits 200 in the first scanning circuit group respectively provide scanning signals for the leakage control signal line EMB and the second scanning line S2 connected with the same row of pixel circuits 100, so that the two scanning circuit groups do not need to be arranged in the display panel to respectively provide scanning signals for the leakage control signal line EMB and the second scanning line S2, which is beneficial to reducing the space occupied by the scanning circuits in the display panel, and therefore, the narrow frame design is realized.

With reference to fig. 2, 3 and 15, further, the control terminal of the first leakage suppressing module 130 and the control terminal of the second leakage suppressing module 140 in the ith row of pixel circuits 100 are connected to the output terminal OUT of the ith first scan circuit 200 through the leakage control signal line EMB, and the control terminal of the threshold compensating module 160 in the ith row of pixel circuits 100 is connected to the output terminal OUT of the (i+2) th first scan circuit 200 through the second scan line S2. Where i is greater than or equal to 1 and less than or equal to the total number of rows of the pixel circuit 100.

In fig. 15, only 4 rows of pixel circuits 100 in the display panel and 5 first scan circuits 200 in the first scan circuit group are shown, and in practical application, the display panel may include a plurality of rows of pixel circuits 100, and the first scan circuit group may include a plurality of first scan circuits 200. The control terminal of the first leakage suppression module 130 and the control terminal of the second leakage suppression module 140 in the 1 st row of pixel circuits 100 are connected to the output terminal OUT of the 1 st first scan circuit 200 through the leakage control signal line EMB, the control terminal of the threshold compensation module 160 in the 1 st row of pixel circuits 100 is connected to the output terminal OUT of the 3 rd first scan circuit 200 through the second scan line S2, the control terminal of the first leakage suppression module 130 and the control terminal of the second leakage suppression module 140 in the 2 nd row of pixel circuits 100 are connected to the output terminal OUT of the 2 nd first scan circuit 200 through the leakage control signal line EMB, the control terminal of the threshold compensation module 160 in the 2 nd row of pixel circuits 100 is connected to the output terminal OUT of the 4 th first scan circuit 200 through the second scan line S2, and the like, so that the first scan circuits 200 connected to the control terminals of the first leakage suppression module 130, the second leakage suppression module 140 and the threshold compensation module 160 in each row of pixel circuits 100 can be determined.

Fig. 3 shows signals input from the leakage control signal line EMB and the second scan line S2 connected to the pixel circuits 100 of the 2n-1 th and 2 n-th rows, where n is greater than or equal to 1 and 2n is less than or equal to the total number of rows of the pixel circuits 100. Illustratively, the 2n-1 th first scan circuit 200 outputs the scan signal S (2 n-1), and supplies the scan signal S (2 n-1) to the leakage control signal line EMB connected to the 2n-1 th row pixel circuit 100 to control the first leakage suppressing module 130 and the second leakage suppressing module 140 to operate. The 2n+1-th first scan circuit 200 outputs a scan signal S (2n+1), and supplies the scan signal S (2n+1) to the second scan line S2 connected to the 2 n-1-th row pixel circuit 100 to control the threshold compensation module 160 to operate, so that the first pulse signal input by the second scan line S2 corresponding to the 2 n-1-th row pixel circuit 100 overlaps with the timing sequence of the second pulse signal input by the leakage control signal line EMB to satisfy the operation timing sequence requirement of the 2 n-1-th row pixel circuit 100.

Similarly, the 2n-th first scan circuit 200 outputs the scan signal S (2 n), and supplies the scan signal S (2 n) to the leakage control signal line EMB connected to the 2 n-th row pixel circuit 100 to control the first leakage suppression module 130 and the second leakage suppression module 140 to operate, and the 2n+2-th first scan circuit 200 outputs the scan signal S (2n+2), and supplies the scan signal S (2n+2) to the second scan line S2 connected to the 2 n-th row pixel circuit 100 to control the threshold compensation module 160 to operate, so that the first pulse signal input by the second scan line S2 corresponding to the 2 n-th row pixel circuit 100 overlaps the timing of the second pulse signal input by the leakage control signal line EMB to satisfy the operation timing requirement of the 2 n-th row pixel circuit 100.

On the basis of the above-described embodiment, as shown in fig. 15, the number of the first scanning circuit groups may be 1, and each of the first scanning circuits 200 in the first scanning circuit group is located in the non-display area NAA on the display area AA side in the row direction in which the pixel circuits 100 are arranged. In another embodiment, the number of the first scan circuit groups may be 2, and along the row direction of the pixel circuit 100, each first scan circuit 200 in one first scan circuit group is located in the non-display area NAA on one side of the display area AA, and each first scan circuit 200 in the other first scan circuit group is located in the non-display area NAA on the other side of the display area AA, so as to supply scan signals to the corresponding second scan line S2 or the leakage control signal line EMB through the first scan circuits 200 on both sides at the same time, which helps to avoid the voltage drop on the second scan line S2 or the leakage control signal line EMB from affecting the display effect.

Fig. 16 is a schematic structural diagram of another display panel according to an embodiment of the invention. Referring to fig. 16, optionally, the display panel further includes a second scan circuit group, where the second scan circuit group is located in the non-display area NAA, and the second scan circuit group includes a plurality of cascaded second scan circuits 300, and each second scan circuit 300 generates a scan signal with a sequential backward sequence step by step. Specifically, the start signal terminal SIN2 of the 1 st second scan circuit 300 in the second scan circuit group is connected to the second start signal line 420, and the second start signal line 420 inputs a second start signal, where the second start signal is a pulse signal. The second scanning circuit 300 is configured to shift back the timing of the pulse signal input from the initial signal terminal SIN2 to obtain a scanning signal, and provide the scanning signal to the corresponding pixel circuit 100 through the output terminal OUT. In each two adjacent second scan circuits 300, the output terminal OUT of the previous second scan circuit 300 is connected to the start signal terminal SIN2 of the next second scan circuit 300, so that the scan signal output by the previous second scan circuit 300 is used as the start signal of the next second scan circuit 300, so that each second scan circuit 300 in the second scan circuit group can output the scan signal with the time sequence shifted backward in sequence step by step.

In conjunction with fig. 2, 3 and 16, further, the display panel further includes a first scan line S1. In one embodiment, the output terminal OUT of the j-th second scan circuit 300 may be configured to connect the control terminals of the first initialization modules 170 in the pixel circuits 100 of the 2j-1 and 2 j-th rows through the first scan line S1 to provide the scan signal to the control terminals of the first initialization modules 170 in the corresponding pixel circuits 100. Wherein j is greater than or equal to 1 and less than or equal to the total number of second scan circuits 300.

In fig. 16, only 4 rows of pixel circuits 100 in the display panel and 2 second scan circuits 300 in the second scan circuit group are shown, and in practical application, the display panel may include a plurality of rows of pixel circuits 100, and the second scan circuit group may include a plurality of second scan circuits 300. The output terminal OUT of the 1 st second scan circuit 300 is connected to the control terminal of the first initialization module 170 in the 1 st row and the 2 nd row of pixel circuits 100 through the first scan line S1 to provide a scan signal to the control terminal of the first initialization module 170 in the corresponding pixel circuit 100. The output terminal OUT of the 2 nd second scan circuit 300 is connected to the control terminal of the first initialization module 170 in the 3 rd and 4 th row pixel circuits 100 through the first scan line S1 to supply a scan signal to the control terminal of the first initialization module 170 in the corresponding pixel circuit 100. Similarly, the second scan circuit 300 connected to the control terminal of the first initialization module 170 in each row of pixel circuits 100 can be determined, which is not listed.

Fig. 3 illustrates signals input from the first Scan line S1 connected to the 2n-1 th and 2 n-th pixel circuits 100, and illustratively, the n-th second Scan circuit 300 outputs a Scan signal Scan (n) and supplies the Scan signal Scan (n) to the first Scan line S1 connected to the 2n-1 th and 2 n-th pixel circuits 100 to control the first initialization module 170 to operate. The advantage of this arrangement is that two rows of pixel circuits 100 can be driven to operate by one second scanning circuit 300, which is beneficial to reducing the number of second scanning circuits 300, thereby reducing the space occupied by the second scanning circuits 300 in the display panel, and realizing a narrow frame design.

Referring to fig. 2, 3 and 16, further, the pixel circuit 100 further includes a light emission control module 220, the display panel further includes a light emission control signal generating circuit group, the light emission control signal generating circuit group is located in the non-display area NAA, the light emission control signal generating circuit group includes a plurality of cascaded light emission control signal generating circuits 400, and each light emission control signal generating circuit 400 generates a light emission control signal with a sequential sequentially backward step by step. Specifically, the start signal terminal EIN of the 1 st light emission control signal generation circuit 400 in the light emission control signal generation circuit group is connected to the third start signal line 430, and the third start signal line 430 inputs a third start signal, which is a pulse signal. The light emission control signal generating circuit 400 is configured to shift back the timing of the pulse signal input from the start signal terminal EIN to obtain a light emission control signal, and provide the light emission control signal to the corresponding pixel circuit 100 through the output terminal OUT. In each adjacent two-stage light emission control signal generation circuit 400, the output terminal OUT of the previous light emission control signal generation circuit 400 is connected to the start signal terminal EIN of the next light emission control signal generation circuit 400, so that the scan signal output by the previous light emission control signal generation circuit 400 is used as the start signal of the next light emission control signal generation circuit 400, and each light emission control signal generation circuit 400 in the light emission control signal generation circuit group can output the light emission control signals with sequentially backward time sequences step by step.

In conjunction with fig. 2, 3 and 16, further, the display panel further includes a light emission control signal line EM. In one embodiment, the output terminal OUT of the kth light emission control signal generation circuit 400 may be provided to connect the control terminals of the light emission control modules 220 in the 2k-1 th and 2 k-th row pixel circuits 100 through the light emission control signal line EM to supply the light emission control signals to the control terminals of the light emission control modules 220 in the corresponding pixel circuits 100. Wherein k is greater than or equal to 1 and less than or equal to the total number of the light emission control signal generation circuits 400.

Only 2 light emission control signal generation circuits 400 among the light emission control signal generation circuit group are shown in fig. 16, and in practical application, the light emission control signal generation circuit group may include a plurality of light emission control signal generation circuits 400. The output terminal OUT of the 1 st light emission control signal generation circuit 400 is connected to the control terminal of the light emission control module 220 in the 1 st and 2 nd row pixel circuits 100 through the light emission control signal line EM to provide a light emission control signal to the control terminal of the light emission control module 220 in the corresponding pixel circuit 100. The output terminal OUT of the 2 nd light emission control signal generation circuit 400 is connected to the control terminal of the light emission control module 220 in the 3 rd and 4 th row pixel circuits 100 through the light emission control signal line EM to supply a light emission control signal to the control terminal of the light emission control module 220 in the corresponding pixel circuit 100. Similarly, the light emission control signal generation circuit 400 connected to the control terminal of the light emission control module 220 in each row of the pixel circuits 100 can be determined, which is not illustrated.

Fig. 3 shows signals input from the emission control signal lines EM connected to the 2n-1 th and 2 n-th row pixel circuits 100, and the n-th emission control signal generation circuit 400 outputs an emission control signal E (n) and supplies the emission control signal E (n) to the emission control signal lines EM connected to the 2n-1 th and 2 n-th row pixel circuits 100 to control the operation of the emission control module 220, for example. The advantage of this arrangement is that two rows of pixel circuits 100 can be driven to operate by one light emission control signal generating circuit 400, which is advantageous in reducing the number of light emission control signal generating circuits 400, thereby reducing the space occupied by the light emission control signal generating circuits 400 in the display panel, and realizing a narrow frame design.

Referring to fig. 16, the second scan circuit group and the light emission control signal generation circuit group are optionally located in the non-display area NAA on the same side of the display area AA on the basis of the above-described embodiments. The display panel further includes a first clock signal line 440 and a second clock signal line 450, and in the case where the number of pixel circuits 100 connected to each of the light emission control signal generating circuits 400 is the same as the number of pixel circuits 100 connected to each of the second scan circuits 300, the second scan circuits 300 and the light emission control signal generating circuits 400 are both connected to the first clock signal line 440 and the second clock signal line 450 so that the second scan circuits 300 generate scan signals in response to signals on the first clock signal line 440 and the second clock signal line 450, and the light emission control signal generating circuits 400 generate light emission control signals in response to signals on the first clock signal line 440 and the second clock signal line 450.

Specifically, the first clock signal line 440 inputs a first clock signal, the second clock signal line 450 inputs a second clock signal, the first clock signal and the second clock signal are each a clock signal in which a high level and a low level alternate, and pulse timings of the first clock signal and the second clock signal are different. In the case that each second scanning circuit 300 is used for driving two rows of pixel circuits 100 to operate, and each light emission control signal generating circuit 400 is used for driving two rows of pixel circuits 100 to operate, the frequencies of the scanning signals generated by the second scanning circuits 300 and the frequencies of the light emission control signals generated by the light emission control signal generating circuits 400 are the same, by setting the scanning signals generated by the second scanning circuits 300 in response to the signals on the first clock signal line 440 and the second clock signal line 450, the light emission control signal generating circuits 400 in response to the signals on the first clock signal line 440 and the second clock signal line 450 generate the light emission control signals, so that the second scanning circuit group and the light emission control signal generating circuit group can share the first clock signal line 440 and the second clock signal line 450, and the corresponding clock signal lines do not need to be set for the second scanning circuit group and the light emission control signal generating circuit group respectively, which is beneficial to reducing the number of signal lines in the display panel, so as to realize the narrow frame design.

Further, the extending directions of the first clock signal line 440 and the second clock signal line 450 are the same, the second scan circuit group is located at one side of the first clock signal line 440 and the second clock signal line 450, and the light emission control signal generating circuit group is located at the other side of the first clock signal line 440 and the second clock signal line 450, so that the second scan circuits 300 in the second scan circuit group and the light emission control signal generating circuits 400 in the light emission control signal generating circuit group are respectively disposed at both sides of the first clock signal line 440 and the second clock signal line 450, so that the arrangement of each second scan circuit 300 and each light emission control signal generating circuit 400 does not affect each other, which is helpful for simplifying the manufacturing process of the display panel.

On the basis of the above-described embodiment, as shown in fig. 16, the number of the second scanning circuit groups may be 1, and each of the second scanning circuits 300 in the second scanning circuit group is located in the non-display area NAA on the display area AA side in the row direction in which the pixel circuits 100 are arranged. In another embodiment, the number of the second scan circuit groups may be 2, and along the row direction of the pixel circuit 100, each second scan circuit 300 in one second scan circuit group is located in the non-display area NAA on one side of the display area AA, and each second scan circuit 300 in the other second scan circuit group is located in the non-display area NAA on the other side of the display area AA, so that the scan signals are simultaneously supplied to the corresponding first scan lines S1 through the second scan circuits 300 on both sides, so as to help avoid the voltage drop on the first scan lines S1 from affecting the display effect.

The number of the light emission control signal generation circuit groups may be 1, and each of the light emission control signal generation circuits 400 in the light emission control signal generation circuit groups is located in the non-display area NAA on the display area AA side along the row direction in which the pixel circuits 100 are arranged. In another embodiment, the number of the light emission control signal generating circuit groups may be 2, and each light emission control signal generating circuit 400 in one light emission control signal generating circuit group is located in the non-display area NAA on one side of the display area AA, and each light emission control signal generating circuit 400 in the other light emission control signal generating circuit group is located in the non-display area NAA on the other side of the display area AA, so that the scan signals are simultaneously supplied to the corresponding light emission control signal lines EM through the light emission control signal generating circuits 400 on both sides, which helps to avoid the voltage drop on the light emission control signal lines EM from affecting the display effect.

When the number of the second scan circuit group and the light emission control signal generation circuit group is 2, the second scan circuit group and the light emission control signal generation circuit group located on the same side of the display panel may be provided to share one first clock signal line 440 and one second clock signal line 450, and the second scan circuit 300 in the second scan circuit group and the light emission control signal generation circuit 400 in the light emission control signal generation circuit group are provided on both sides of the first clock signal line 440 and the second clock signal line 450, respectively.

FIG. 17 is a schematic diagram of another display panel according to an embodiment of the present invention; FIG. 18 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention; fig. 19 is a schematic diagram of a driving timing of another pixel circuit according to an embodiment of the present invention. In another embodiment, referring to fig. 2 and 17 to 19, the output terminal OUT of the j-th second scanning circuit 300 may be further configured to be connected to the control terminal of the first initializing module 170 in the j-th row of pixel circuits 100 through the first scanning line S1 to provide a scanning signal to the control terminal of the first initializing module 170 in the corresponding pixel circuit 100. Wherein j is greater than or equal to 1 and less than or equal to the total number of second scan circuits 300.

Only 4 second scan circuits 300 of the second scan circuit group are shown in fig. 17, and in practical applications, the second scan circuit group may include a plurality of second scan circuits 300. The output terminal OUT of the 1 st second scan circuit 300 is connected to the control terminal of the first initialization module 170 in the 1 st row of pixel circuits 100 through the first scan line S1 to provide a scan signal to the control terminal of the first initialization module 170 in the corresponding pixel circuit 100. The output terminal OUT of the 2 nd second scan circuit 300 is connected to the control terminal of the first initialization module 170 in the 2 nd row of pixel circuits 100 through the first scan line S1 to supply a scan signal to the control terminal of the first initialization module 170 in the corresponding pixel circuit 100. Similarly, the second scan circuit 300 connected to the control terminal of the first initialization module 170 in each row of pixel circuits 100 can be determined, which is not listed.

The signals input from the first Scan line S1 connected to the 2n-1 th and 2 n-th row pixel circuits 100 are shown in fig. 18 and 19, and the 2n-1 th second Scan circuit 300 outputs a Scan signal Scan (2 n-1) and supplies the Scan signal Scan (2 n-1) to the first Scan line S1 connected to the 2n-1 th row pixel circuit 100 to control the first initialization module 170 to operate, for example. The 2 n-th second Scan circuit 300 outputs a Scan signal Scan (2 n), and supplies the Scan signal Scan (2 n) to the first Scan line S1 connected to the 2 n-th row pixel circuit 100 to control the first initialization module 170 to operate. The principle of operation of the driving timing driving pixel circuit shown in fig. 18 and 19 is similar to that of the driving timing driving pixel circuit shown in fig. 3 and 4, and can be understood with reference to the above embodiment, and will not be repeated here.

Referring to fig. 17, in the present embodiment, the first scan circuit 200 is connected to the third clock signal line 460 and the fourth clock signal line 470, and the first scan circuit 200 generates a scan signal in response to signals on the third clock signal line 460 and the fourth clock signal line 470. The third clock signal line 460 inputs a third clock signal, the fourth clock signal line 470 inputs a fourth clock signal, the third clock signal and the fourth clock signal are each a clock signal in which a high level and a low level alternate, and pulse timings of the third clock signal and the fourth clock signal are different. The second scan circuit 300 is connected to the fifth clock signal line 480 and the sixth clock signal line 490, and the second scan circuit 300 generates a scan signal in response to signals on the fifth clock signal line 480 and the sixth clock signal line 490. The fifth clock signal line 480 inputs a fifth clock signal, the sixth clock signal line 490 inputs a sixth clock signal, the fifth clock signal and the sixth clock signal are each clock signals of which high level and low level are alternately changed, and pulse timings of the fifth clock signal and the sixth clock signal are different. The light emission control signal generation circuit 400 is connected to the first clock signal line 440 and the second clock signal line 450, and the light emission control signal generation circuit 400 generates a light emission control signal in response to signals on the first clock signal line 440 and the second clock signal line 450.

In another embodiment, the output terminal OUT of the kth light emission control signal generation circuit 400 may be further provided, and the control terminal of the light emission control module 220 in the kth row of pixel circuits 100 may be connected through the light emission control signal line EM to provide the light emission control signal to the control terminal of the light emission control module 220 in the corresponding pixel circuit 100. Wherein k is greater than or equal to 1 and less than or equal to the total number of the light emission control signal generation circuits 400. That is, each light-emitting control signal generating circuit 400 drives one row of pixel circuits 100 to operate, and the specific principle is not described again.

Fig. 20 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 2, 5 and 20, optionally, in the same row of pixel circuits 100, the control end of the first initialization module 170, the control end of the threshold compensation module 160 and the control end of the first leakage suppression module 130 are respectively connected to the output ends OUT of different first scan circuits 200, and the first scan circuit 200 connected to the control end of the first initialization module 170 is located before the first scan circuit 200 connected to the control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140, and the first scan circuit 200 connected to the control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140 is located before the first scan circuit 200 connected to the control end of the threshold compensation module 160.

The advantage of this arrangement is that the three first scan circuits 200 in the first scan circuit group can respectively provide scan signals to the leakage control signal line EMB, the first scan line S1 and the second scan line S2 connected to the same row of pixel circuits 100, so that in a display frame, pulse signals with the same waveforms are provided to the leakage control signal line EMB, the first scan line S1 and the second scan line S2, and the pulse signal timing input by the first scan line S1 is earlier than the pulse signal timing input by the leakage control signal line EMB, and the pulse signal timing input by the leakage control signal line EMB is earlier than the pulse signal timing input by the second scan line S2, so that the first scan line S1 can input pulse signals in an initialization stage and the leakage control signal line EMB can respectively input pulse signals in a data writing stage, and the second scan line S2 can input pulse signals in a data writing stage, so as to meet the working timing requirement of the pixel circuits.

The three first scan circuits 200 in the first scan circuit group respectively provide scan signals to the leakage control signal line EMB, the first scan line S1 and the second scan line S2 connected to the same row of pixel circuits 100, so that the three scan circuit groups do not need to be arranged in the display panel to respectively provide scan signals to the leakage control signal line EMB, the first scan line S1 and the second scan line S2, which is beneficial to reducing the space occupied by the scan circuits in the display panel, thereby realizing narrow frame design.

With reference to fig. 2, 5 and 20, further, the control terminal of the first initialization module 170 in the ith row of pixel circuits 100 is connected to the output terminal OUT of the ith first scan circuit 200 through the first scan line S1, the control terminal of the first leakage suppression module 130 and the control terminal of the second leakage suppression module 140 in the ith row of pixel circuits 100 are connected to the output terminal OUT of the i+2th first scan circuit 200 through the leakage control signal line EMB, and the control terminal of the threshold compensation module 160 in the ith row of pixel circuits 100 is connected to the output terminal OUT of the i+4th first scan circuit 200 through the second scan line S2, wherein i is greater than or equal to 1 and less than or equal to the total number of rows of the pixel circuits 100.

Only 5 first scan circuits 200 of the first scan circuit group are shown in fig. 20, and in practical application, the first scan circuit group may include a plurality of first scan circuits 200. The control terminal of the first initialization module 170 in the 1 st row of pixel circuits 100 is connected to the output terminal OUT of the 1 st first scan circuit 200 through the first scan line S1, the control terminal of the first leakage suppression module 130 and the control terminal of the second leakage suppression module 140 in the 1 st row of pixel circuits 100 are connected to the output terminal OUT of the 3 rd first scan circuit 200 through the leakage control signal line EMB, and the control terminal of the threshold compensation module 160 in the 1 st row of pixel circuits 100 is connected to the output terminal OUT of the 5 th first scan circuit 200 through the second scan line S2. The control terminal of the first initializing module 170 in the 2 nd row of pixel circuits 100 is connected to the output terminal OUT of the 2 nd first scanning circuit 200 through the first scanning line S1, the control terminal of the first leakage suppressing module 130 and the control terminal of the second leakage suppressing module 140 in the 2 nd row of pixel circuits 100 are connected to the output terminal OUT of the 4 th first scanning circuit 200 through the leakage control signal line EMB, the control terminal of the threshold compensating module 160 in the 2 nd row of pixel circuits 100 is connected to the output terminal OUT of the 6 th first scanning circuit 200 (not shown in the figure) through the second scanning line S2, and so on, it is possible to determine the first scanning circuits 200 to which the control terminals of the first leakage suppressing module 130, the second leakage suppressing module 140, the threshold compensating module 160 and the first initializing module 170 in each row of pixel circuits 100 are connected, which are not listed one by one.

Fig. 5 shows signals input from the leakage control signal line EMB, the first scan line S1, and the second scan line S2, which are connected to the pixel circuits 100 of the 2n-1 th row and the 2 n-2 th row, where n is greater than or equal to 1 and 2n is less than or equal to the total number of rows of the pixel circuits 100. Illustratively, the 2n-1 th first scan circuit 200 outputs the scan signal S (2 n-1), and supplies the scan signal S (2 n-1) to the first scan line S1 connected to the 2n-1 th row pixel circuit 100 to control the first initialization module 170 to operate. The 2n+1 th first scan circuit 200 outputs a scan signal S (2n+1), and supplies the scan signal S (2n+1) to the leakage control signal line EMB connected to the 2n-1 th row pixel circuit 100 to control the first leakage suppression module 130 and the second leakage suppression module 140 to operate. The 2n+3 th first scan circuit 200 outputs a scan signal S (2n+3), and supplies the scan signal S (2n+3) to the second scan line S2 connected to the 2n-1 st row pixel circuit 100 to control the threshold compensation module 160 to operate such that the second pulse signal input to the first scan line S1 corresponding to the 2n-1 st row pixel circuit 100 overlaps with the timing of the first pulse signal input to the leakage control signal line EMB, and the second pulse signal input to the leakage control signal line EMB overlaps with the timing of the first pulse signal input to the second scan line S2 to satisfy the operation timing requirement of the 2n-1 st row pixel circuit 100.

Similarly, the 2 n-th first scanning circuit 200 outputs a scanning signal S (2 n), and supplies the scanning signal S (2 n) to the first scanning line S1 connected to the 2 n-th row pixel circuit 100 to control the first initialization module 170 to operate. The 2n+2 th first scan circuit 200 outputs a scan signal S (2n+2), and supplies the scan signal S (2n+2) to the leakage control signal line EMB connected to the 2n row pixel circuit 100 to control the first leakage suppressing module 130 and the second leakage suppressing module 140 to operate. The 2n+4 th first scan circuit 200 outputs a scan signal S (2n+4), and supplies the scan signal S (2n+4) to the second scan line S2 connected to the 2 n-th row pixel circuit 100 to control the threshold compensation module 160 to operate, so that the second pulse signal input by the first scan line S1 corresponding to the 2 n-th row pixel circuit 100 overlaps with the timing of the first pulse signal input by the leakage control signal line EMB, and the second pulse signal input by the leakage control signal line EMB overlaps with the timing of the first pulse signal input by the second scan line S2 to satisfy the operation timing requirement of the 2 n-th row pixel circuit 100.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A pixel circuit, comprising:

the first storage module is connected with the first node and used for storing the voltage of the first node so as to reduce the voltage difference between the control end of the driving module and the first node;

2. The pixel circuit of claim 1, wherein a first end of the first memory module is connected to the first node, and a second end of the first memory module is connected to a fixed voltage;

preferably, the pixel circuit further includes a first initialization module connected between an initialization signal line and the second node, for writing a voltage on the initialization signal line into a control terminal of the driving module;

3. The pixel circuit according to claim 1 or 2, further comprising a data writing module, a first end of the data writing module being connected to a data line, a second end of the data writing module being connected to a second end of the driving module;

4. A pixel circuit according to claim 3, wherein the leakage control signal line is configured to: respectively inputting pulse signals in an initialization stage and a data writing stage in a display frame;

preferably, in a display frame, the signal waveform input by the second scan line is the same as the signal waveform input by the leakage control signal line, the pulse signal timing input by the second scan line is later than the pulse signal timing input by the leakage control signal line, and the first pulse signal input by the second scan line overlaps with the second pulse signal timing input by the leakage control signal line;

preferably, the first scan line is configured to: inputting pulse signals in an initialization stage in a display frame;

preferably, in a display frame, a signal waveform input by the first scan line is the same as a signal waveform input by the leakage control signal line, a pulse signal timing input by the first scan line is earlier than a pulse signal timing input by the leakage control signal line, and a second pulse signal input by the first scan line overlaps with a first pulse signal timing input by the leakage control signal line;

preferably, the pixel circuit further includes a coupling module, a first end of the coupling module is connected to the first node, a second end of the coupling module is connected to a jump voltage, and the coupling module is used for coupling the jump voltage to the first node so as to reduce a voltage difference between a control end of the driving module and the first node in a light emitting stage;

5. A display panel, comprising a substrate, a leakage control signal line, a switching portion, and the pixel circuit of any one of claims 1-4, wherein the leakage control signal line, the switching portion, and the pixel circuit are all located on the substrate;

6. The display panel of claim 5, wherein the second metal layer is located on a side of the semiconductor layer of the first transistor away from the substrate, and wherein a vertical projection of the interposer on the substrate overlaps with a vertical projection of the semiconductor layer of the first transistor on the substrate;

preferably, the semiconductor layer of the first transistor and the semiconductor layer of the second transistor are located on the same side of the semiconductor layer of the driving transistor along a first direction, the leakage control signal line extends along a second direction, a vertical projection of the semiconductor layer of the first transistor on the substrate and a vertical projection of the semiconductor layer of the second transistor on the substrate overlap with a vertical projection of the leakage control signal line on the substrate, and the first direction intersects with the second direction;

preferably, the threshold compensation module includes a third transistor, a first pole of the first transistor is connected to a gate of the driving transistor, a second pole of the first transistor is connected to a first pole of the second transistor, the third transistor is connected between the first pole of the driving transistor and the second pole of the second transistor, the pixel circuit further includes a fourth transistor, a gate of the fourth transistor is connected to the leakage control signal line, and the fourth transistor is connected between the second transistor and the third transistor;

preferably, the semiconductor layer of the first transistor, the semiconductor layer of the second transistor, and the semiconductor layer of the fourth transistor are sequentially arranged along the second direction;

preferably, the pixel circuit further includes a data writing module and a fifth transistor, a gate of the fifth transistor is connected to the leakage control signal line, and the fifth transistor is connected between a data line and the data writing module;

7. The display panel according to claim 5 or 6, wherein the first storage module comprises a first capacitor, a first polar plate of the first capacitor is connected to the first node, and a second polar plate of the first capacitor is connected to a fixed voltage;

8. A display panel, characterized in that the display panel has a display area and a non-display area, the display panel comprising a first scanning circuit group and a plurality of rows of pixel circuits according to any one of claims 1-4;

9. The display panel according to claim 8, further comprising a second scan line and a leakage control signal line;

the control end of the first leakage suppression module and the control end of the second leakage suppression module in the pixel circuit in the ith row are connected with the output end of the first scanning circuit through the leakage control signal line, the control end of the threshold compensation module in the pixel circuit in the ith row is connected with the output end of the (i+2) th first scanning circuit through the second scanning line, wherein i is greater than or equal to 1 and less than or equal to the total row number of the pixel circuit;

preferably, in the pixel circuits in the same row, the control end of a first initializing module, the control end of the threshold compensation module and the control end of the first leakage suppression module are respectively connected with different output ends of the first scanning circuits, and the first scanning circuit connected with the control end of the first initializing module is located before the first scanning circuit connected with the control end of the first leakage suppression module and the control end of the second leakage suppression module;

10. The display panel according to claim 8 or 9, further comprising a second scan circuit group and a first scan line, wherein the second scan circuit group is located in the non-display area, the second scan circuit group comprises a plurality of cascaded second scan circuits, and each second scan circuit generates a scan signal with sequentially shifted timings step by step;

the output end of the j-th second scanning circuit is connected with the control end of a first initializing module in the pixel circuits of the 2j-1 row and the 2j row through the first scanning line so as to provide the scanning signals for the control end of the first initializing module in the corresponding pixel circuit;

wherein j is greater than or equal to 1 and less than or equal to the total number of the second scan circuits;

preferably, the pixel circuit further comprises a light-emitting control module, the display panel further comprises a light-emitting control signal generation circuit group and a light-emitting control signal line, the light-emitting control signal generation circuit group is located in the non-display area, the light-emitting control signal generation circuit group comprises a plurality of cascaded light-emitting control signal generation circuits, and each light-emitting control signal generation circuit generates a light-emitting control signal with time sequence sequentially shifted backwards step by step;

wherein k is greater than or equal to 1 and less than or equal to the total number of the light emission control signal generation circuits;

preferably, the second scanning circuit group and the light emission control signal generation circuit group are located in the non-display region on the same side as the display region;