CN116314509A - Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDF

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CN116314509A
CN116314509A CN202310573615.2A CN202310573615A CN116314509A CN 116314509 A CN116314509 A CN 116314509A CN 202310573615 A CN202310573615 A CN 202310573615A CN 116314509 A CN116314509 A CN 116314509A
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layer
inalgan
aln
emitting diode
nano
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张彩霞
印从飞
刘春杨
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Priority to CN202310864987.0A priority patent/CN116995163A/en
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
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    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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Abstract

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer comprises a substrate, and a nucleation layer, an intrinsic GaN layer, a first insertion layer, an N-GaN layer, a second insertion layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer which are sequentially arranged on the substrate; the first insertion layer comprises a first InAlGaN nano hole layer and a first AlN smooth layer which are sequentially stacked, and the second insertion layer comprises a second InAlGaN nano hole layer and a second AlN smooth layer which are sequentially stacked; the first InAlGaN nano-pore layer comprises a plurality of first nano-pores distributed in an array, and the second InAlGaN nano-pore layer comprises a plurality of nano-pores distributed in an array. By implementing the invention, the luminous efficiency of the light-emitting diode can be improved, the antistatic capability is improved, and the voltage distribution uniformity is improved.

Description

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
Currently, gaN-based light emitting diodes have been widely used in the field of solid state lighting as well as in the field of display, attracting more and more attention. The GaN-based light emitting diode has been industrially produced and has been used in backlight, illumination, landscape lamp, and the like.
The N-GaN layer provides electrons in the light emitting diode, which is a very important structure in the light emitting diode epitaxial wafer. The inventors found that the following problems exist:
(1) The growth temperature and the rotation speed of the intrinsic GaN layer are high, so that the accumulated stress and the warping of the intrinsic GaN layer are very large;
(2) The N-GaN layer has great accumulated stress and warping due to high N-type doping and high temperature, high rotating speed and high growing speed during growth, the N-type doping at the edge of the epitaxial wafer is difficult, and the N-type doping is less when the N-GaN layer is close to the edge of the epitaxial wafer, so that the voltage at the edge of the epitaxial wafer is obviously increased, and the voltage distribution uniformity of the epitaxial wafer is poor;
(3) The intrinsic GaN layer and the N-GaN layer have large warpage, so that the lattice quality and the surface flatness of the edge of the epitaxial wafer are poor, and the antistatic capability of the epitaxial wafer is influenced;
(4) The N-GaN layer has poor lattice quality, accumulated defects extend into the multiple quantum well layers to become carrier non-radiative recombination centers, and the luminous efficiency of the epitaxial wafer is affected;
(5) The electron moving speed provided by the N-GaN layer is high, the hole moving speed is low, so that electron holes in the light emitting region are not matched, the light emitting efficiency is affected, electrons easily enter the P-GaN layer, and the light emitting efficiency is further reduced.
Disclosure of Invention
The invention aims to solve the technical problem of providing a light-emitting diode epitaxial wafer and a preparation method thereof, which can reduce the stress and the warpage of the light-emitting diode epitaxial wafer, improve the luminous efficiency of the light-emitting diode, improve the antistatic capability and improve the voltage distribution uniformity.
The invention also solves the technical problems of providing a light-emitting diode which has high luminous efficiency, high antistatic capability and good voltage distribution uniformity.
In order to solve the problems, the invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate, and a nucleation layer, an intrinsic GaN layer, a first insertion layer, an N-GaN layer, a second insertion layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer which are sequentially arranged on the substrate; the first insertion layer comprises a first InAlGaN nanometer hole layer and a first AlN smooth layer which are sequentially stacked, and the second insertion layer comprises a second InAlGaN nanometer hole layer and a second AlN smooth layer which are sequentially stacked;
the first InAlGaN nano-hole layer comprises a plurality of first nano holes distributed in an array; the second InAlGaN nanohole layers comprise a plurality of second nanoholes distributed in an array.
As an improvement of the technical scheme, the first InAlGaN nano hole layer is obtained by etching the first InAlGaN layer, and the second InAlGaN nano hole layer is obtained by etching the second InAlGaN layer;
the thickness of the first InAlGaN layer and the second InAlGaN layer is 50nm-100nm.
As an improvement of the technical scheme, the diameter of the first nano holes is 20nm-200nm, and the distribution density of the first nano holes is 1 multiplied by 10 8 Individual/cm 2 -1×10 10 Individual/cm 2 ；
The diameter of the second nano holes is 20nm-200nm, and the distribution density of the second nano holes is 1 multiplied by 10 8 Individual/cm 2 -1×10 10 Individual/cm 2 。
As improvement of the technical scheme, the ratio of the In component In the first InAlGaN nano-pore layer to the ratio of the In component In the second InAlGaN nano-pore layer are respectively 0.1-0.2, and the ratio of the Al component is respectively 0.4-0.6.
As an improvement of the technical scheme, the ratio of the Al component in the first AlN smoothing layer to the ratio of the Al component in the second AlN smoothing layer are both 0.1-0.3.
As an improvement of the technical scheme, the thickness of the first AlN smoothing layer and the second AlN smoothing layer is 5nm-20nm.
Correspondingly, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
providing a substrate, and sequentially growing a nucleation layer, an intrinsic GaN layer, a first insertion layer, an N-GaN layer, a second insertion layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer on the substrate; the first insertion layer comprises a first InAlGaN nanometer hole layer and a first AlN smooth layer which are sequentially stacked, and the second insertion layer comprises a second InAlGaN nanometer hole layer and a second AlN smooth layer which are sequentially stacked;
the first InAlGaN nano-hole layer comprises a plurality of first nano holes distributed in an array; the second InAlGaN nanohole layers comprise a plurality of second nanoholes distributed in an array.
As an improvement of the technical scheme, the first InAlGaN nano hole layer is obtained by etching the first InAlGaN layer, and the second InAlGaN nano hole layer is obtained by etching the second InAlGaN layer;
the growth temperature of the first InAlGaN layer and the second InAlGaN layer is 950-1000 ℃, and the growth pressure is 100-300 torr.
As an improvement of the technical scheme, the growth temperature of the first AlN smoothing layer and the second AlN smoothing layer is 1050-1150 ℃ and the growth pressure is 50-150 torr.
Correspondingly, the invention also discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The implementation of the invention has the following beneficial effects:
1. in the LED epitaxial wafer, the nano gaps in the first InAlGaN nano hole layer enable the accumulated stress of the intrinsic GaN layer growing at high temperature and high speed to be well released, the warpage is relieved, and the nano holes intercept a plurality of screw dislocation, so that the lattice quality is improved; the first AlN smoothing layer can improve the surface flatness of the epitaxial wafer, improve the antistatic capacity, enable Si distribution of the N-GaN layer to be more uniform, and improve the voltage distribution uniformity; the AlN material has higher energy level, so that electron reflux can be blocked, electron hole pairs are increased, and the luminous efficiency is improved;
the nano gaps in the second InAlGaN nano hole layer can release the stress of the N-GaN layer, alleviate warpage, and avoid the reduction of luminous efficiency caused by the influence of stress accumulation on the multiple quantum well layers and the influence on the lattice quality of the multiple quantum well layers; the second AlN smoothing layer can improve the surface flatness of the epitaxial wafer, improve the antistatic capability, annihilate the defects formed by the N-GaN layer, avoid the defects from extending to the multiple quantum well layers, form non-radiative recombination and influence the luminous efficiency; the second AlN smoothing layer forms an electron barrier due to the high energy level, so that the balance of electron hole pairs in the multiple quantum well layer is improved, and the luminous efficiency is improved.
2. According to the invention, the first InAlGaN nano-pore layer and the second InAlGaN nano-pore layer are doped with high Al and low In, the Al-N bond energy is larger than Ga-N bond energy, and the lattice stability can be increased, but the high Al doping easily causes uneven distribution of Al atoms, so that the low In doping is adopted, in atoms can be used as a catalyst, the mobility of the Al atoms is increased, and the distribution uniformity of the Al atoms is improved.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
FIG. 2 is a schematic view of a first interposer in an embodiment of the present invention;
FIG. 3 is a schematic diagram of a second interposer in an embodiment of the present invention;
FIG. 4 is a schematic diagram showing the distribution positions of the first nano-holes according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing the distribution positions of the first nano-holes according to another embodiment of the present invention;
FIG. 6 is a schematic diagram showing the distribution position of the second nano-holes according to an embodiment of the present invention;
FIG. 7 is a schematic diagram showing the distribution position of the second nano-holes according to another embodiment of the present invention;
fig. 8 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1-7, the invention discloses a light emitting diode epitaxial wafer, which comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, a first insertion layer 4, an N-GaN layer 5, a second insertion layer 6, a multiple quantum well layer 7, an electron blocking layer 8 and a P-GaN layer 9 which are sequentially arranged on the substrate; the first insertion layer 4 includes a first InAlGaN nanohole layer 41 and a first AlN smoothing layer 42 stacked in order, and the second insertion layer 6 includes a second InAlGaN nanohole layer 61 and a second AlN smoothing layer 62 stacked in order; wherein the first InAlGaN nanohole layer 41 includes a plurality of first nanoholes 411 distributed in an array, and the second InAlGaN nanohole layer 61 includes a plurality of second nanoholes 611 distributed in an array.
The nano gaps in the first InAlGaN nano hole layer 41 enable the accumulated stress of the intrinsic GaN layer 3 grown at high temperature and high speed to be well released, the warpage is relieved, and the nano holes intercept a plurality of screw dislocation, so that the lattice quality is improved; the first AlN smoothing layer 42 can improve the surface flatness of the epitaxial wafer, improve the antistatic capacity, enable the Si distribution of the N-GaN layer 5 to be more uniform, and improve the voltage distribution uniformity; the AlN material has higher energy level, so that electron reflux can be blocked, electron hole pairs are increased, and the luminous efficiency is improved.
The nano gaps in the second InAlGaN nano hole layer 61 can release the stress of the N-GaN layer 5, relieve the warpage, and avoid the stress accumulation to the multiple quantum well layer 7, thereby influencing the lattice quality of the multiple quantum well layer 7 to reduce the luminous efficiency; the second AlN smoothing layer 62 can improve the surface flatness of the epitaxial wafer, improve the antistatic capability, annihilate the defects formed by the N-GaN layer 5, and avoid the defects from extending to the multiple quantum well layers 7 to form non-radiative recombination so as to influence the luminous efficiency; the second AlN smoothing layer 62 forms an electron barrier due to the high energy level, improves the balance of electron-hole pairs in the multiple quantum well layer 7, and improves the light emission efficiency.
Specifically, the first InAlGaN nanohole layer 41 may be obtained by using a nanoimprint technique or a photolithography technique on the first InAlGaN layer. Preferably, in one embodiment of the present invention, the first InAlGaN nanohole layer 41 is obtained by etching the first InAlGaN layer by using a photolithography technique, and the second InAlGaN nanohole layer 61 is obtained by etching the second InAlGaN layer by using a photolithography technique; the thicknesses of the first InAlGaN layer and the second InAlGaN layer are 40nm-120nm, and the thicknesses of the first InAlGaN layer and the second InAlGaN layer are in the range, so that the first InAlGaN nano hole layer 41 and the second InAlGaN nano hole layer 61 formed after etching play a good role in releasing stress and relieving warping. Preferably, the thickness of the first and second InAlGaN layers is 50nm to 100nm, and exemplary are 60nm, 70nm, 80nm, or 90nm, but not limited thereto.
Specifically, the cross sections of the first nanoholes 411 and the second nanoholes 611 are circular, triangular, quadrilateral, trapezoidal or polygonal (the number of sides is equal to or greater than 5), but not limited thereto. The nano holes with various cross-sectional shapes can release stress and relieve warpage. Preferably, the cross sections of the first nanoholes 411 and the second nanoholes 611 are circular, and based on this structure, uniform distribution of In atoms and Al atoms is facilitated. Specifically, the diameters of the first nano holes 411 and the second nano holes 611 are 20nm-250nm, if the diameters are less than 20nm, the effects of releasing stress and relieving warpage are difficult to be effectively achieved; if the diameter is more than 250nm, the effective filling is difficult, and the luminous efficiency is affected. Preferably, the diameters of the first nanoholes 411 and the second nanoholes 611 are 20nm to 200nm, and exemplary are 50nm, 70nm, 100nm, 120nm, 150nm, or 180nm, but are not limited thereto.
Specifically, the first nano-holes 411 are distributed in an array. Referring to fig. 4, a plurality of first nano holes 411 are distributed on the first InAlGaN nano hole layer 41 in a plurality of rows, wherein the spacing between adjacent first nano holes 411 is the same in each row of first nano holes 411, and the adjacent rows of first nano holesThe holes 411 are aligned in the same direction (Y direction in fig. 4), and the spacing between adjacent rows of first nanoholes 411 is the same (i.e., Y direction). Based on the structure, the first InAlGaN nano-pore layer 41 is favorable for playing the roles of well releasing stress and relieving warpage. Referring to fig. 5, in another embodiment of the present invention, a plurality of first nanopores 411 are distributed on the first InAlGaN nanopores 41 in multiple rows, and in each row of first nanopores 411, the spacing between adjacent first nanopores 411 is the same, and the first nanopores 411 between adjacent rows are distributed in a staggered manner. Based on the structure, the nano holes can better cut off screw dislocation. It should be noted that, the array distribution of the first nano-holes 411 of the present invention is not limited to the above embodiment, and one skilled in the art can adjust the distribution of the first nano-holes 411 according to the stress relief requirement. Specifically, the distribution density of the first nano-holes 411 is 1×10 8 Individual/cm 2 -1×10 10 Individual/cm 2 Exemplary is 2X 10 8 Individual/cm 2 、4×10 8 Individual/cm 2 、6×10 8 Individual/cm 2 、8×10 8 Individual/cm 2 、1×10 9 Individual/cm 2 、2×10 9 Individual/cm 2 、4×10 9 Individual/cm 2 、6×10 9 Individual/cm 2 Or 8X 10 9 Individual/cm 2 But is not limited thereto.
Accordingly, referring to fig. 6 and 7, the second nano-holes 611 are distributed in an array, and the distribution form thereof is the same as that of the first nano-holes 411, which will not be described herein.
Specifically, the ratio of In component In the first InAlGaN nanohole layer 41 and the second InAlGaN nanohole layer 61 is 0.1-0.2, and the ratio of al component is 0.4-0.6. The high Al doping and the low In doping are adopted, the Al-N bond energy is larger than Ga-N bond energy, and the lattice stability can be improved, but the high Al doping easily causes uneven distribution of Al atoms, so that the low In doping is adopted, in atoms can be used as a catalyst, the mobility of the Al atoms is increased, and the distribution uniformity of the Al atoms is improved. Illustratively, the In composition ratio of the first and second InAlGaN nanohole layers 41 and 61 is 0.12, 0.14, 0.16 or 0.18, but is not limited thereto. The ratio of Al component in the first InAlGaN nanohole layer 41 and the second InAlGaN nanohole layer 61 is 0.42, 0.44, 0.46, 0.48, 0.5, 0.52, 0.54, 0.56 or 0.58, but is not limited thereto.
Specifically, the first AlN smoothing layer 42 and the second AlN smoothing layer 62 each have an Al composition having a ratio of 0.1 to 0.35, and the Al composition is in this range, and the first AlN smoothing layer 42 and the second AlN smoothing layer 62 have a good lattice quality and a high flatness. Preferably, the Al component of the first AlN smoothing layer 42 and the second AlN smoothing layer 62 has a ratio of 0.1-0.3, and exemplary ones are 0.12, 0.14, 0.16, 0.18, 0.2, 0.22, 0.24, 0.26 or 0.28, but not limited thereto.
Specifically, the thicknesses of the first AlN smoothing layer 42 and the second AlN smoothing layer 62 are each 5nm to 25nm. If the thickness is more than 25nm, cracks are easy to generate; if the thickness is less than 5nm, it is difficult to achieve good flatness. The thicknesses of the first AlN smoothing layer 42 and the second AlN smoothing layer 62 are preferably 5nm to 20nm, and are exemplified by 8nm, 10nm, 12nm, 14nm, 16nm, or 18nm, but are not limited thereto.
Among them, the substrate 1 may be a sapphire substrate, a silicon carbide substrate, but is not limited thereto.
The nucleation layer 2 may be an AlN layer and/or an AlGaN layer, but is not limited thereto. The thickness of the nucleation layer 2 is 20nm to 100nm, and is exemplified by 30nm, 40nm, 50nm, 60nm, 70nm, 80nm or 90nm, but not limited thereto.
Among them, the intrinsic GaN layer 3 has a thickness of 300nm to 800nm, and exemplary are 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, or 750nm, but not limited thereto.
Wherein the doping element of the N-GaN layer 5 is Si, but is not limited thereto. The doping concentration of the N-GaN layer 5 is 5×10 18 cm -3 -1×10 19 cm -3 The thickness is 1 μm-3 μm.
The multiple quantum well layer 7 is an InGaN quantum well layer and a GaN quantum barrier layer which are alternately stacked, and the stacking period number is 3-15. The thickness of the single InGaN quantum well layer is 3nm-7nm, and the thickness of the single GaN quantum barrier layer is 6nm-15nm.
Wherein the electron blocking layer 8 is Al a Ga 1-a N layer (a=0.05 to 0.2) and In b Ga 1-b And the periodic structure with N layers (b=0.1-0.5) alternately grown has a period number of 3-15. The thickness of the electron blocking layer 8 is 20-100nm.
Wherein the doping element in the P-GaN layer 9 is Mg, but is not limited thereto. The doping concentration of Mg in the P-GaN layer 9 was 5×10 17 cm -3 -1×10 20 cm -3 . The thickness of the P-GaN layer 9 is 200nm to 300nm.
Correspondingly, referring to fig. 8, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
s100: providing a substrate;
specifically, the substrate is a sapphire substrate, a silicon carbide substrate, but is not limited thereto. A sapphire substrate is preferred.
Preferably, in one embodiment of the present invention, the substrate is loaded into MOCVD and annealed at 1000-1200 deg.C, 200-600 torr, hydrogen atmosphere for 5-8 min to remove impurities such as particles, oxides, etc. on the substrate surface.
S200: growing a nucleation layer on the substrate;
specifically, the MOCVD grown AlGaN layer may be used as the nucleation layer, or the PVD grown AlN layer may be used as the nucleation layer, but is not limited thereto. Preferably, the AlGaN layer is grown by MOCVD, the growth temperature is 500-700 ℃, and the growth pressure is 200-400 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
S300: growing an intrinsic GaN layer on the nucleation layer;
specifically, the intrinsic GaN layer is grown in MOCVD at 1100-1150 deg.c and 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S400: growing a first insertion layer on the intrinsic GaN layer;
specifically, growing the first insertion layer includes the steps of:
s410: growing a first InAlGaN nano-hole layer on the intrinsic GaN layer;
specifically, a first InAlGaN layer is grown in MOCVD, the growth temperature is 950-1000 ℃, the growth pressure is 100-500 torr, and NH is introduced into a MOCVD reaction chamber during growth 3 As N source, TMGa as Ga source, TMIn as In source, TMAL as Al source, and H 2 And N 2 As a carrier gas. Specifically, the first InAlGaN nanohole layer may be obtained by using a nanoimprint technique or a photolithography technique on the first InAlGaN layer. Preferably, in an embodiment of the present invention, the first InAlGaN nanohole layer is obtained by etching the first InAlGaN layer by using a photolithography technique.
S420: growing a first AlN smooth layer on the first InAlGaN nano hole layer;
specifically, the first AlN smoothing layer is grown in MOCVD under the same growth conditions as those of an AlN layer common in the art. Preferably, in one embodiment of the present invention, the growth temperature of the first AlN smoothing layer is 1050-1150 deg.C and the growth pressure is 50-150 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, TMAL is introduced as Al source, H is used 2 And N 2 As a carrier gas. The first AlN smoothing layer obtained based on such growth conditions is less prone to cracking and has good flatness.
S500: growing an N-GaN layer on the first insertion layer;
specifically, an N-GaN layer is grown in MOCVD at 1100-1150 deg.C under 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S600: growing a second insertion layer on the N-GaN layer;
specifically, a second InAlGaN nano-pore layer and a second AlN smooth layer are sequentially grown on the N-GaN layer and serve as a second insertion layer. Specifically, the conditions for growing the second InAlGaN nanohole layer are the same as the conditions for growing the first InAlGaN nanohole layer in step S410, and will not be described here again. Specifically, the conditions for growing the second AlN smoothing layer are the same as those for growing the first AlN smoothing layer in step S420, and will not be described here again.
S700: growing a multiple quantum well layer on the second insertion layer;
specifically, an InGaN quantum well layer and a GaN quantum barrier layer are periodically grown in MOCVD to form a multi-quantum well layer. Wherein the growth temperature of the InGaN quantum well layer is 700-800 ℃, the growth pressure is 100-500 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source. Wherein the growth temperature of the GaN quantum barrier layer is 800-900 ℃, the growth pressure is 100-500 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
S800: growing an electron blocking layer on the multiple quantum well layer;
wherein, in one embodiment of the invention, al is grown periodically in MOCVD a Ga 1-a N layer (a=0.05 to 0.2) and In b Ga 1-b N layers (b=0.1 to 0.5) until an electron blocking layer is obtained; the growth temperature of the two materials is 900-1000 ℃ and the growth pressure is 100-500 torr. Wherein Al is grown a Ga 1-a Introducing NH into MOCVD reaction chamber during N layer 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source, and TMAl was introduced as an Al source. Growth of In b Ga 1-b Introducing NH into MOCVD reaction chamber during N layer 3 As N source, N 2 As a carrier gas, TMGa was introduced as a Ga source, and TMIn was introduced as an In source.
S900: growing a P-GaN layer on the electron blocking layer;
specifically, the P-GaN layer is grown in MOCVD at 800-1000 deg.C and 100-300 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, let in CP 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
The invention is further illustrated by the following examples:
example 1
The embodiment provides a light emitting diode epitaxial wafer, referring to fig. 1-4 and 6, which comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, a first insertion layer 4, an N-GaN layer 5, a second insertion layer 6, a multiple quantum well layer 7, an electron blocking layer 8 and a P-GaN layer 9 which are sequentially arranged on the substrate 1.
Wherein the substrate 1 is a sapphire substrate, the nucleation layer 2 is an AlGaN layer, and the thickness of the AlGaN layer is 30nm. The thickness of the intrinsic GaN layer 3 is 400nm.
The first insertion layer 4 includes a first InAlGaN nanohole layer 41 and a first AlN smoothing layer 42 stacked in this order.
The first InAlGaN nanohole layer 41 is obtained by etching a first InAlGaN layer by using a photolithography technique, the thickness of the first InAlGaN layer is 70nm, the first InAlGaN nanohole layer 41 includes a plurality of first nanoholes 411 distributed in an array, the cross section of each first nanohole 411 is circular, the diameter of each first nanohole 411 is 100nm, the plurality of first nanoholes 411 are distributed on the first InAlGaN nanohole layer 41 in multiple rows, in each row of first nanoholes 411, the spacing between adjacent first nanoholes 411 is the same, the adjacent rows of first nanoholes 411 are aligned in the same direction (Y direction in fig. 4), and the spacing between adjacent rows of first nanoholes 411 is the same (i.e., Y direction). The distribution density of the first nano-holes 411 is 1×10 9 Individual/cm 2 . The first InAlGaN nanohole layer 41 has an In component of 0.1 and an al component of 0.5.
Wherein the ratio of the Al component in the first AlN smoothing layer 42 is 0.2, and the thickness of the first AlN smoothing layer 42 is 10nm.
The thickness of the N-GaN layer 5 was 2. Mu.m, the doping element was Si, and the doping concentration of Si was 1X 10 19 cm -3 。
The second insertion layer 6 includes a second InAlGaN nanohole layer 61 and a second AlN smoothing layer 62 sequentially stacked.
Wherein the second InAlGaN nano hole layer 61 is obtained by etching the second InAlGaN layer by adopting a photoetching technology, the thickness of the second InAlGaN layer is 70nm, and the first InAlGaN nano hole layer is formed by etching the second InAlGaN nano hole layer by adopting a photoetching technologyThe two InAlGaN nanohole layers 61 include a plurality of second nanoholes 611 distributed in an array, the cross section of each second nanohole 611 is circular, the diameter of each second nanohole 611 is 100nm, the plurality of second nanoholes 611 are distributed on the second InAlGaN nanohole layers 61 in multiple rows, in each row of second nanoholes 611, the spacing between adjacent second nanoholes 611 is the same, the adjacent rows of second nanoholes 611 are aligned in the same direction (Y direction in fig. 6), and the spacing between adjacent rows of second nanoholes 611 is the same (i.e. Y direction). The distribution density of the second nano-holes 611 is 1×10 9 Individual/cm 2 . The second InAlGaN nanohole layer 61 has an In component of 0.1 and an al component of 0.5.
Wherein the ratio of the Al component in the second AlN smoothing layer 62 was 0.2, and the thickness of the second AlN smoothing layer 62 was 10nm.
The multiple quantum well layer 7 is an InGaN quantum well layer and a GaN quantum barrier layer which are alternately stacked, and the number of stacked periods is 10. The thickness of the single InGaN quantum well layer was 3nm, and the thickness of the single GaN quantum barrier layer was 10nm.
Wherein the electron blocking layer 8 is Al a Ga 1-a N layers (a=0.1) and In b Ga 1-b N layers (b=0.2) alternately grow a periodic structure with a period of 10. Single Al a Ga 1-a The thickness of the N layer is 6nm, single In b Ga 1-b The thickness of the N layer was 6nm.
Wherein the doping element in the P-GaN layer 9 is Mg. The doping concentration of Mg in the P-GaN layer 9 was 1×10 19 cm -3 . The thickness of the P-GaN layer 9 was 240nm.
The preparation method for the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
loading the substrate into the MOCVD reaction chamber, at H 2 Pretreating for 7min in the atmosphere at 1100 ℃ under 400torr.
(2) Growing a nucleation layer on the substrate;
the AlGaN layer is grown by MOCVD, the growth temperature is 600 ℃, and the growth pressure is 300torr. During growth, the MOCVD reaction chamber is filled withNH 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
(3) Growing an intrinsic GaN layer on the nucleation layer;
wherein, the intrinsic GaN layer is grown in MOCVD, the growth temperature is 1120 ℃, and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source.
(4) Growing a first insertion layer on the intrinsic GaN layer;
specifically, growing the first insertion layer includes the steps of:
growing a first InAlGaN nano-pore layer on the intrinsic GaN layer;
specifically, a first InAlGaN layer is grown in MOCVD, the growth temperature is 980 ℃, the growth pressure is 300torr, and NH is introduced into a MOCVD reaction chamber during growth 3 As N source, TMGa as Ga source, TMIn as In source, TMAL as Al source, and H 2 And N 2 As a carrier gas. Specifically, the first InAlGaN layer is etched by adopting a photoetching technology, and then the first InAlGaN nano hole layer is obtained.
(ii) growing a first AlN smoothing layer on the first InAlGaN nanohole layer;
specifically, the first AlN smoothing layer was grown in MOCVD at 1100℃under a growth pressure of 100torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, TMAL is introduced as Al source, H is used 2 And N 2 As a carrier gas.
(5) Growing an N-GaN layer on the first insertion layer;
wherein, the N-GaN layer is grown in MOCVD, the growth temperature is 1140 ℃, and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, N 2 And H 2 As carrier gas, TMGa is introduced as Ga source, siH is introduced 4 As an N-type dopant source.
(6) Growing a second insertion layer on the N-GaN layer;
specifically, a second InAlGaN nano-pore layer and a second AlN smooth layer are sequentially grown on the N-GaN layer and serve as a second insertion layer. Specifically, the conditions for growing the second InAlGaN nanohole layer are the same as the conditions for growing the first InAlGaN nanohole layer in the step (4), and will not be described here again. Specifically, the conditions for growing the second AlN smoothing layer are the same as the conditions for growing the first AlN smoothing layer in step (4), and will not be described here.
(7) Growing a multiple quantum well layer on the second insertion layer;
specifically, an InGaN quantum well layer and a GaN quantum barrier layer are periodically grown in MOCVD to form a multi-quantum well layer. Wherein the growth temperature of the InGaN quantum well layer is 750 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source. Wherein, the growth temperature of the GaN quantum barrier layer is 850 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
(8) Growing an electron blocking layer on the multiple quantum well layer;
wherein Al is periodically grown in MOCVD a Ga 1-a N layer and In b Ga 1-b N layers until an electron blocking layer is obtained; both of them were grown at 950℃and at 300torr. Wherein Al is grown a Ga 1-a Introducing NH into MOCVD reaction chamber during N layer 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source, and TMAl was introduced as an Al source. Growth of In b Ga 1-b Introducing NH into MOCVD reaction chamber during N layer 3 As N source, N 2 As a carrier gas, TMGa was introduced as a Ga source, and TMIn was introduced as an In source.
(9) Growing a P-GaN layer on the electron blocking layer;
wherein, the P-GaN layer is grown in MOCVD, the growth temperature is 930 ℃, and the growth pressure is 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, N 2 And H 2 As carrier gas, TMGa is introduced as Ga source, CP is introduced 2 Mg is used as a P-type dopant source.
Example 2
The embodiment provides a light emitting diode epitaxial wafer, referring to fig. 1-3, 5 and 7, which comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, a first insertion layer 4, an N-GaN layer 5, a second insertion layer 6, a multiple quantum well layer 7, an electron blocking layer 8 and a P-GaN layer 9 which are sequentially arranged on the substrate 1.
Wherein the substrate 1 is a sapphire substrate, the nucleation layer 2 is an AlGaN layer, and the thickness of the AlGaN layer is 30nm. The thickness of the intrinsic GaN layer 3 is 400nm.
The first insertion layer 4 includes a first InAlGaN nanohole layer 41 and a first AlN smoothing layer 42 stacked in this order.
The first InAlGaN nanohole layer 41 is obtained by etching the first InAlGaN layer by using a photolithography technique, the thickness of the first InAlGaN layer is 70nm, the first InAlGaN nanohole layer 41 includes a plurality of first nanoholes 411 distributed in an array, the cross section of the first nanoholes 411 is circular, the diameter of the first nanoholes 411 is 100nm, the plurality of first nanoholes 411 are distributed on the first InAlGaN nanohole layer 41 in multiple rows, in each row of first nanoholes 411, the intervals between adjacent first nanoholes 411 are the same, and the first nanoholes 411 between adjacent rows are distributed in a staggered manner. The distribution density of the first nano-holes 411 is 1×10 9 Individual/cm 2 . The first InAlGaN nanohole layer 41 has an In component of 0.1 and an al component of 0.5.
Wherein the ratio of the Al component in the first AlN smoothing layer 42 is 0.2, and the thickness of the first AlN smoothing layer 42 is 10nm.
The thickness of the N-GaN layer 5 was 2. Mu.m, the doping element was Si, and the doping concentration of Si was 1X 10 19 cm -3 。
The second insertion layer 6 includes a second InAlGaN nanohole layer 61 and a second AlN smoothing layer 62 sequentially stacked.
Wherein the second InAlGaN nanohole layer 61 is obtained by etching the second InAlGaN layer by photolithography, the thickness of the second InAlGaN layer is 70nm, the second InAlGaN nanohole layer 61 includes a plurality of second nanoholes 611 distributed in an array, and the second nanoholesThe cross section of each hole 611 is circular, the diameter of each second nano hole 611 is 100nm, a plurality of second nano holes 611 are distributed on the second InAlGaN nano hole layer 61 in multiple rows, in each row of second nano holes 611, the distances between every two adjacent second nano holes 611 are the same, and the second nano holes 611 between every two adjacent rows are distributed in a staggered way. The distribution density of the second nano-holes 611 is 1×10 9 Individual/cm 2 . The second InAlGaN nanohole layer 61 has an In component of 0.1 and an al component of 0.5.
Wherein the ratio of the Al component in the second AlN smoothing layer 62 was 0.2, and the thickness of the second AlN smoothing layer 62 was 10nm.
The multiple quantum well layer 7 is an InGaN quantum well layer and a GaN quantum barrier layer which are alternately stacked, and the number of stacked periods is 10. The thickness of the single InGaN quantum well layer was 3nm, and the thickness of the single GaN quantum barrier layer was 10nm.
Wherein the electron blocking layer 8 is Al a Ga 1-a N layers (a=0.1) and In b Ga 1-b N layers (b=0.2) alternately grow a periodic structure with a period of 10. Single Al a Ga 1-a The thickness of the N layer is 6nm, single In b Ga 1-b The thickness of the N layer was 6nm.
Wherein the doping element in the P-GaN layer 9 is Mg. The doping concentration of Mg in the P-GaN layer 9 was 1×10 19 cm -3 . The thickness of the P-GaN layer 9 was 240nm.
The preparation method for the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
loading the substrate into the MOCVD reaction chamber, at H 2 Pretreating for 7min in the atmosphere at 1100 ℃ under 400torr.
(2) Growing a nucleation layer on the substrate;
the AlGaN layer is grown by MOCVD, the growth temperature is 600 ℃, and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
(3) Growing an intrinsic GaN layer on the nucleation layer;
wherein, the intrinsic GaN layer is grown in MOCVD, the growth temperature is 1120 ℃, and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source.
(4) Growing a first insertion layer on the intrinsic GaN layer;
specifically, growing the first insertion layer includes the steps of:
growing a first InAlGaN nano-pore layer on the intrinsic GaN layer;
specifically, a first InAlGaN layer is grown in MOCVD, the growth temperature is 980 ℃, the growth pressure is 300torr, and NH is introduced into a MOCVD reaction chamber during growth 3 As N source, TMGa as Ga source, TMIn as In source, TMAL as Al source, and H 2 And N 2 As a carrier gas. Specifically, the first InAlGaN layer is etched by adopting a photoetching technology, and then the first InAlGaN nano hole layer is obtained.
(ii) growing a first AlN smoothing layer on the first InAlGaN nanohole layer;
specifically, the first AlN smoothing layer was grown in MOCVD at 1100℃under a growth pressure of 100torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, TMAL is introduced as Al source, H is used 2 And N 2 As a carrier gas.
(5) Growing an N-GaN layer on the first insertion layer;
wherein, the N-GaN layer is grown in MOCVD, the growth temperature is 1140 ℃, and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, N 2 And H 2 As carrier gas, TMGa is introduced as Ga source, siH is introduced 4 As an N-type dopant source.
(6) Growing a second insertion layer on the N-GaN layer;
specifically, a second InAlGaN nano-pore layer and a second AlN smooth layer are sequentially grown on the N-GaN layer and serve as a second insertion layer. Specifically, the conditions for growing the second InAlGaN nanohole layer are the same as the conditions for growing the first InAlGaN nanohole layer in the step (4), and will not be described here again. Specifically, the conditions for growing the second AlN smoothing layer are the same as the conditions for growing the first AlN smoothing layer in step (4), and will not be described here.
(7) Growing a multiple quantum well layer on the second insertion layer;
specifically, an InGaN quantum well layer and a GaN quantum barrier layer are periodically grown in MOCVD to form a multi-quantum well layer. Wherein the growth temperature of the InGaN quantum well layer is 750 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source. Wherein, the growth temperature of the GaN quantum barrier layer is 850 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
(8) Growing an electron blocking layer on the multiple quantum well layer;
wherein Al is periodically grown in MOCVD a Ga 1-a N layer and In b Ga 1-b N layers until an electron blocking layer is obtained; both of them were grown at 950℃and at 300torr. Wherein Al is grown a Ga 1-a Introducing NH into MOCVD reaction chamber during N layer 3 As N source, N 2 And H 2 As a carrier gas, TMGa was introduced as a Ga source, and TMAl was introduced as an Al source. Growth of In b Ga 1-b Introducing NH into MOCVD reaction chamber during N layer 3 As N source, N 2 As a carrier gas, TMGa was introduced as a Ga source, and TMIn was introduced as an In source.
(9) Growing a P-GaN layer on the electron blocking layer;
wherein, the P-GaN layer is grown in MOCVD, the growth temperature is 930 ℃, and the growth pressure is 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, N 2 And H 2 As carrier gas, TMGa is introduced as Ga source, CP is introduced 2 Mg is used as a P-type dopant source.
Comparative example 1
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that the first insertion layer and the second insertion layer are not included, and accordingly, in the manufacturing method, the manufacturing steps of the above two layers are not included, and the rest is the same as example 1.
Comparative example 2
The present comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the first insertion layer is a first InAlGaN layer, excluding the second insertion layer, and accordingly, in the manufacturing method, the first InAlGaN layer is not etched, and the manufacturing steps of the first AlN smoothing layer and the second insertion layer are not included, and the rest is the same as embodiment 1.
Comparative example 3
The present comparative example provides a light emitting diode epitaxial wafer differing from example 1 in that the first insertion layer is a first InAlGaN layer and a first AlN smoothing layer laminated in this order, excluding the second insertion layer, and correspondingly, in the manufacturing method, the first InAlGaN layer is not etched, and also excluding the manufacturing step of the second insertion layer, and the rest is the same as example 1.
Comparative example 4
This comparative example provides a light emitting diode epitaxial wafer differing from example 1 in that the first AlN smoothing layer was not included in the first insertion layer, the second insertion layer was not included in the epitaxial wafer, and accordingly, in the manufacturing method, the manufacturing steps of the first AlN smoothing layer and the second insertion layer were not included, and the remainder was the same as example 1.
Comparative example 5
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that the second insertion layer is not included, and accordingly, in the manufacturing method, the step of manufacturing the layer is not included. The remainder was the same as in example 1.
Comparative example 6
The present comparative example provides a light emitting diode epitaxial wafer, which is different from example 1 in that the second insertion layer is a second InAlGaN layer, and accordingly, in the manufacturing method, the second InAlGaN layer is not etched, and the manufacturing step of the second AlN smoothing layer is not included, and the rest is the same as example 1.
Comparative example 7
The present comparative example provides a light emitting diode epitaxial wafer differing from example 1 in that the second insertion layer is a second InAlGaN layer and a second AlN smoothing layer laminated in this order, and accordingly, in the manufacturing method, the second InAlGaN layer is not etched, and the rest is the same as example 1.
Comparative example 8
This comparative example provides a light emitting diode epitaxial wafer differing from example 1 in that the second AlN smoothing layer was not included in the second insertion layer, and accordingly, in the production method, the production step of the second AlN smoothing layer was not included, and the remainder was the same as example 1.
The light emitting diode epitaxial wafers obtained in examples 1 to 2 and comparative examples 1 to 8 were tested as follows:
(1) Operating voltage: operating voltage testing was performed using a Keithley2450 digital source meter;
(2) Taking 20 epitaxial wafers prepared in each example and comparative example, respectively measuring the working voltage of the epitaxial wafers, and calculating the relative standard deviation of the epitaxial wafers to obtain working voltage uniformity;
(3) Brightness: preparing the epitaxial wafer into a chip with a vertical structure of 10mil multiplied by 24mil, and testing the luminous brightness of the chip;
(4) Antistatic ability test: antistatic performance test: testing the antistatic performance of the base chip by using an electrostatic instrument under an HBM (human body discharge model) model, wherein the test chip can bear the passing proportion of reverse 8000V static electricity;
(5) The epitaxial wafer was measured by an X-ray diffractometer.
The specific results are as follows:
Figure SMS_1
as can be seen from the table, when the epitaxial wafer in the conventional light emitting diode structure (comparative example 1) is replaced by the epitaxial wafer structure of the present invention, the brightness is increased from 191.1mW to 197.5mW, the antistatic capability is increased from 92.3% to 98.8%, the XRD (002) plane is reduced from 112 to 84, the XRD (102) plane is reduced from 160 to 130, the operating voltage is reduced from 3.21 to 3.1, and the operating voltage uniformity is improved from 0.15 to 0.01, which indicates that the epitaxial wafer structure of the present invention can reduce dislocation defects, improve lattice quality, increase luminous efficiency, improve antistatic capability, reduce operating voltage, and improve operating voltage uniformity.
In addition, as can be seen from the comparison of example 1 with comparative examples 2 to 8, it is difficult to effectively achieve the effects of reducing dislocation defects, improving lattice quality, improving brightness, improving antistatic ability, lowering operating voltage, and improving operating voltage uniformity when the epitaxial wafer structure in the present invention is changed.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, and a nucleation layer, an intrinsic GaN layer, a first insertion layer, an N-GaN layer, a second insertion layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer which are sequentially arranged on the substrate; the first insertion layer comprises a first InAlGaN nanometer hole layer and a first AlN smooth layer which are sequentially stacked, and the second insertion layer comprises a second InAlGaN nanometer hole layer and a second AlN smooth layer which are sequentially stacked;
the first InAlGaN nano-hole layer comprises a plurality of first nano holes distributed in an array; the second InAlGaN nanohole layers comprise a plurality of second nanoholes distributed in an array.
2. The light-emitting diode epitaxial wafer of claim 1, wherein the first InAlGaN nanohole layer is etched from a first InAlGaN layer, and the second InAlGaN nanohole layer is etched from a second InAlGaN layer;
the thickness of the first InAlGaN layer and the second InAlGaN layer is 50nm-100nm.
3. As claimed inThe led epitaxial wafer of claim 1, wherein the first nanoholes have a diameter of 20nm to 200nm and a distribution density of 1 x 10 8 Individual/cm 2 -1×10 10 Individual/cm 2 ；
The diameter of the second nano holes is 20nm-200nm, and the distribution density of the second nano holes is 1 multiplied by 10 8 Individual/cm 2 -1×10 10 Individual/cm 2 。
4. The light-emitting diode epitaxial wafer of claim 1, wherein the ratio of In component In the first InAlGaN nanohole layer to the ratio of al component In the second InAlGaN nanohole layer are both 0.1-0.2, and the ratio of al component is both 0.4-0.6.
5. The light-emitting diode epitaxial wafer of claim 1, wherein the first AlN smoothing layer and the second AlN smoothing layer each have an Al composition in a ratio of 0.1 to 0.3.
6. The light-emitting diode epitaxial wafer of claim 1, wherein the first AlN smoothing layer and the second AlN smoothing layer each have a thickness of 5nm to 20nm.
7. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 6, and is characterized by comprising the following steps:
providing a substrate, and sequentially growing a nucleation layer, an intrinsic GaN layer, a first insertion layer, an N-GaN layer, a second insertion layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer on the substrate; the first insertion layer comprises a first InAlGaN nanometer hole layer and a first AlN smooth layer which are sequentially stacked, and the second insertion layer comprises a second InAlGaN nanometer hole layer and a second AlN smooth layer which are sequentially stacked;
the first InAlGaN nano-hole layer comprises a plurality of first nano holes distributed in an array; the second InAlGaN nanohole layers comprise a plurality of second nanoholes distributed in an array.
8. The method for preparing a light-emitting diode epitaxial wafer according to claim 7, wherein the first InAlGaN nano hole layer is obtained by etching a first InAlGaN layer, and the second InAlGaN nano hole layer is obtained by etching a second InAlGaN layer;
the growth temperature of the first InAlGaN layer and the second InAlGaN layer is 950-1000 ℃, and the growth pressure is 100-300 torr.
9. The method for preparing an epitaxial wafer of a light-emitting diode according to claim 7, wherein the growth temperature of the first AlN smoothing layer and the second AlN smoothing layer is 1050-1150 ℃ and the growth pressure is 50-150 torr.
10. A light emitting diode comprising the light emitting diode epitaxial wafer according to any one of claims 1 to 6.
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