CN116314234B - Method for manufacturing semiconductor device and CMOS image sensor - Google Patents
Method for manufacturing semiconductor device and CMOS image sensor Download PDFInfo
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- CN116314234B CN116314234B CN202310582464.7A CN202310582464A CN116314234B CN 116314234 B CN116314234 B CN 116314234B CN 202310582464 A CN202310582464 A CN 202310582464A CN 116314234 B CN116314234 B CN 116314234B
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 119
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 70
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 70
- 238000005530 etching Methods 0.000 claims abstract description 39
- 230000008569 process Effects 0.000 claims abstract description 38
- 230000001681 protective effect Effects 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000011049 filling Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 229910052755 nonmetal Inorganic materials 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 217
- 230000000903 blocking effect Effects 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
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- 238000005859 coupling reaction Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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Abstract
The application provides a manufacturing method of a semiconductor device and a CMOS image sensor, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a first device, a second device, a first barrier layer and a dielectric layer, the first barrier layer is positioned on the exposed surface of the second device, and the dielectric layer is positioned on the exposed surfaces of the first device, the substrate and the first barrier layer; removing part of the dielectric layer to form a first groove and a second groove in the dielectric layer, wherein the first groove exposes the first device, and the second groove exposes the first barrier layer; forming a protection structure covering the first groove, and removing the exposed first barrier layer through the second groove to expose part of the second device; and etching to remove the protective structure, and performing post-etching treatment on the substrate from which the protective structure is removed to obtain the semiconductor device. The method solves the problem that the metal silicide device is damaged in the process of forming the contact holes of the metal silicide device and the nonmetal silicide device.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device and a CMOS image sensor.
Background
The 55CIS (55 nm CMOS image sensor) has two regions, i.e., salicide region and Non-Salicide region, respectively, wherein the Non-Salicide device on the Non-Salicide region has one more barrier layer than the Salicide device on the Salicide region, so that the contact hole of the Salicide device is etched too much during the formation of the contact hole penetrating to the Salicide device and the Non-Salicide device, thereby damaging the Salicide device.
The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.
Disclosure of Invention
The main objective of the present application is to provide a method for manufacturing a semiconductor device and a CMOS image sensor, so as to solve the problem that the metal silicide device is damaged during the process of forming the contact holes of the metal silicide device and the non-metal silicide device in the prior art.
According to an aspect of an embodiment of the present invention, there is provided a method for manufacturing a semiconductor, including: providing a substrate, wherein the substrate comprises a substrate, a first device, a second device, a first barrier layer and a dielectric layer, the first device and the second device are arranged on the substrate at intervals, the first device is a device obtained through self-aligned silicide process treatment, the second device is a device obtained through no self-aligned silicide process treatment, the first barrier layer is positioned on the exposed surface of the second device, and the dielectric layer is positioned on the exposed surfaces of the first device, the substrate and the first barrier layer; removing part of the dielectric layer to form a first groove and a second groove which are positioned in the dielectric layer, wherein the first groove exposes part of the first device, and the second groove exposes part of the first barrier layer; forming a protection structure covering the first groove, and removing the exposed first barrier layer through the second groove to expose part of the second device; and etching to remove the protection structure, and performing post-etching treatment on the substrate from which the protection structure is removed to obtain the semiconductor device.
Optionally, providing a substrate, comprising: providing the substrate, wherein the substrate comprises a first device region and a second device region which are arranged at intervals; forming a first gate structure on the first device region, a first source region and a first drain region on both sides of the first gate structure, and forming a second gate structure on the second device region, a second source region and a second drain region on both sides of the second gate structure, the second source region and the second drain region forming the second device; forming the first barrier layer on the exposed surface of the second device, and processing the substrate with the first barrier layer by adopting a self-aligned silicide process to form a first silicide layer on the surface of the first source region away from the substrate, a second silicide layer on the surface of the first drain region away from the substrate and a third silicide layer on the surface of the first gate structure away from the substrate, wherein the first gate structure, the first source region, the first drain region, the first silicide layer, the second silicide layer and the third silicide layer form the first device; and sequentially stacking a second barrier layer and the dielectric layer on the exposed surfaces of the substrate, the first device and the first barrier layer to obtain the substrate.
Optionally, the first barrier layer covering only the second source region is a first barrier structure, the first barrier layer covering only the second gate structure is a second barrier structure, the first barrier layer covering only the second drain region is a third barrier structure, and removing a portion of the dielectric layer to form a first trench and a second trench in the dielectric layer, including: forming a patterned first mask layer on the surface of the dielectric layer away from the first barrier layer; sequentially etching the dielectric layer and the second barrier layer by taking the patterned first mask layer as a mask to form a first sub-groove, a second sub-groove, a third sub-groove, a fourth sub-groove, a fifth sub-groove and a sixth sub-groove which are positioned in the dielectric layer and the second barrier layer, wherein the first sub-groove exposes part of the surface of the first silicide layer, the second sub-groove exposes part of the surface of the third silicide layer, the third sub-groove exposes part of the surface of the second silicide layer, the fourth sub-groove exposes part of the first barrier structure, the fifth sub-groove exposes part of the second barrier structure, the sixth sub-groove exposes part of the third barrier structure, and the first sub-groove, the second sub-groove and the third sub-groove form the first groove, the fourth sub-groove and the sixth sub-groove form the second groove; and removing the patterned first mask layer.
Optionally, forming a protection structure covering the first trench, and removing the exposed first barrier layer through the second trench to expose a portion of the second device, including: filling photoresist in the first sub-groove, the second sub-groove and the third sub-groove to form the protection structure; and etching the substrate with the protective structure along the fourth sub-groove, the fifth sub-groove and the sixth sub-groove to remove the exposed first barrier layer so that part of the surfaces of the second source electrode region, the second drain electrode region and the second grid electrode structure are exposed.
Optionally, forming a first gate structure on the first device region and forming a second gate structure on the second device region includes: sequentially stacking a gate oxide layer and a polysilicon layer on the substrate; forming a patterned second mask layer on the surface of the polysilicon layer far away from the gate oxide layer; sequentially etching the polysilicon layer and the gate oxide layer by taking the patterned second mask layer as a mask to form a first gate part and a first gate oxide part on the first device region, and a second gate part and a second gate oxide part on the second device region, wherein the first gate part and the first gate oxide part form the first gate structure, and the second gate part and the second gate oxide part form the second gate structure; and removing the patterned second mask layer.
Optionally, etching to remove the protection structure includes: and etching and removing the protective structure by adopting a plasma etching method.
Optionally, after obtaining the semiconductor device, the method further comprises: and filling conductive materials in the first groove and the third groove respectively, wherein the first groove filled with the conductive materials forms a first contact hole, the second groove filled with the conductive materials forms a second contact hole, and the third groove is the second groove after the exposed first barrier layer is removed.
Optionally, the material of the first blocking layer includes TEOS oxide, and the material of the dielectric layer includes silicon oxide.
Optionally, the material of the second barrier layer comprises silicon nitride.
According to another aspect of the embodiment of the present invention, there is also provided a CMOS image sensor including: the semiconductor device manufactured by any manufacturing method.
In the embodiment of the invention, as the second device is provided with one more first barrier layer than the first device, in the process of forming the contact holes penetrating through the first device and the second device, part of the dielectric layer is firstly removed, the first groove exposing the first device and the second groove exposing the first barrier layer are formed, the exposed first barrier layer is continuously removed after the protective structure is filled in the first groove, so that the second device is exposed, the protective structure protects the first device from being damaged in the process of etching the first barrier layer, the problem that the first barrier layer is removed and the first device is damaged in the process of exposing the second device is avoided, meanwhile, the first device and the second device can be exposed, the contact holes can be formed conveniently and successfully, and the high manufacturing yield of the semiconductor device is ensured. And, the post-etching treatment is carried out after the protective structure is etched and removed, so that the oxide thin layer formed on the exposed surface of the second device in the removing process can be removed, and the contact Kong Zu value of the whole semiconductor device is ensured to be lower.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 shows a flow diagram of a method of fabricating a semiconductor device according to an embodiment of the present application;
fig. 2 to 5 respectively show structural schematic diagrams obtained after each process step of the manufacturing method of the semiconductor device according to the embodiment of the present application;
fig. 6 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present application;
fig. 7 shows a schematic structural diagram of a semiconductor device according to another embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. a substrate; 11. a first device; 12. a second device; 13. a first barrier layer; 14. a dielectric layer; 15. a first gate portion; 16. a third silicide layer; 17. a second gate portion; 19. a first source region; 20. a first drain region; 21. a second source region; 22. a second drain region; 23. a first silicide layer; 24. a second silicide layer; 25. a second barrier layer; 26. a first trench; 27. a second trench; 28. a first mask layer; 29. a first sub-trench; 30. a second sub-trench; 31. a third sub-trench; 32. a fourth sub-trench; 33. a fifth sub-trench; 34. a sixth sub-trench; 35. a carbon coating; 36. a dielectric antireflective coating; 37. a bottom antireflective coating; 38. a photoresist layer; 39. a protective structure; 40. a seventh sub-trench; 41. an eighth sub-trench; 42. a ninth sub-trench; 43. a third trench; 44. a first contact hole; 45. a second contact hole; 46. a dielectric structure; 47. a first gate oxide portion; 48. a second gate oxide portion; 49. an isolation structure; 50. a first side wall; 51. and a second side wall.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in order to solve the problem that the process of forming the contact holes of the metal silicide device and the non-metal silicide device damages the metal silicide device, in an exemplary embodiment of the present application, a method for manufacturing a semiconductor device and a CMOS image sensor are provided.
According to an embodiment of the application, a method for manufacturing a semiconductor device is provided.
Fig. 1 is a flowchart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, as shown in fig. 2, providing a base, where the base includes a substrate 10, a first device 11, a second device 12, a first barrier layer 13, and a dielectric layer 14, where the first device 11 and the second device 12 are disposed on the substrate 10 at intervals, the first device 11 is a device obtained by performing a salicide process, the second device 12 is a device obtained by not performing a salicide process, the first barrier layer 13 is located on an exposed surface of the second device 12, and the dielectric layer 14 is located on exposed surfaces of the first device 11, the substrate 10, and the first barrier layer 13;
the substrate may be manufactured by any suitable process by a person skilled in the art, in order to further ensure that the manufacturing process of the substrate is simpler, and further ensure that the substrate is easier to obtain, according to a specific embodiment of the present application, the providing a substrate includes: providing the substrate 10, wherein the substrate 10 comprises a first device region and a second device region which are arranged at intervals; forming a first gate structure on the first device 11 region, a first source region 19 and a first drain region 20 on both sides of the first gate structure, and forming a second gate structure on the second device region, a second source region 21 and a second drain region 22 on both sides of the second gate structure, the second source region 21 and the second drain region 22 forming the second device 12; forming the first barrier layer 13 on the exposed surface of the second device 12, and processing the substrate 10 with the first barrier layer 13 formed thereon by a salicide process to form a first silicide layer 23 on the surface of the first source region 19 remote from the substrate 10, a second silicide layer 24 on the surface of the first drain region 20 remote from the substrate 10, and a third silicide layer 16 on the surface of the first gate structure remote from the substrate 10, the first gate structure, the first source region 19, the first drain region 20, the first silicide layer 23, the second silicide layer 24, and the third silicide layer 16 constituting the first device 11; and sequentially stacking a second barrier layer 25 and the dielectric layer 14 on the exposed surfaces of the substrate 10, the first device 11 and the first barrier layer 13 to obtain the base.
In the embodiment, the first gate structure, the first source region 19 and the first drain region 20 are formed in the first device region, the second device 12 including the second gate structure, the second source region 21 and the second drain region 22 is formed in the second device region, the first barrier layer 13 is formed on the exposed surface of the second device 12, and the self-aligned silicide process is performed on the substrate 10 formed with the first barrier layer 13, so that the second device 12 is covered by the first barrier layer 13, and therefore, the metal silicide film is formed only on the surfaces of the first gate structure, the first source region 19 and the first drain region 20, so as to obtain the first silicide layer 23, the second silicide layer 24 and the third silicide layer 16, and form the first device 11, which can ensure that the on-resistance of the first device is smaller than that of the second device.
It should be noted that the first device region is a Salicide area corresponding to a peripheral region of the CMOS image sensor, and the second device region is a Non-Salicide area corresponding to a pixel region of the CMOS image sensor. The first device is a metal silicide device, and the second device is a non-metal silicide device.
In addition, the substrate includes, in addition to the first device region and the second device region that are disposed at intervals, an isolation structure 49, as shown in fig. 2, where the isolation structure 49 is located between the first device region and the second device region. The isolation structure 49 may be a shallow trench isolation.
In practical applications, the surface of the dielectric layer 14 facing away from the substrate 10 is planar.
In an embodiment of the present application, forming a first gate structure on the first device 11 region and forming a second gate structure on the second device region includes: a gate oxide layer (not shown) and a polysilicon layer are sequentially stacked on the substrate 10; forming a patterned second mask layer on the surface of the polysilicon layer far away from the gate oxide layer; sequentially etching the polysilicon layer and the gate oxide layer by using the patterned second mask layer as a mask to form the first gate oxide portion 47 and the first gate electrode portion 15 on the first device region, and form the second gate oxide portion 48 and the second gate electrode portion 17 on the second device region; removing the patterned second mask layer, and forming a sidewall material on the exposed surfaces of the first gate oxide 47, the first gate oxide 15, the second gate oxide 48 and the second gate oxide 17; the sidewall material is etched by an anisotropic etching method to form a first sidewall 50 on the sidewalls of the first gate oxide portion 47 and the first gate portion 15, and a second sidewall 51 on the sidewalls of the second gate oxide portion 48 and the second gate portion 17, as shown in fig. 2, where the first gate portion 15, the first gate oxide portion 47 and the first sidewall 50 form the first gate structure, and the second gate portion 17, the second gate oxide portion 48 and the second sidewall 51 form the second gate structure. In the embodiment, the gate oxide layer, the polysilicon layer and the patterned second mask layer are stacked on the substrate, and then the polysilicon layer and the gate oxide layer are sequentially etched by taking the second mask layer as a mask, so that the first gate electrode part, the second gate electrode part, the first gate oxide part and the second gate oxide part can be formed simultaneously by one photomask, the process of forming the substrate is further ensured to be easier to realize, and the manufacturing cost is lower.
Of course, in the process of forming the first gate structure and the second gate structure, the first gate structure and the second gate structure may be formed by etching two masks respectively.
In the practical application process, the second mask layer may be a single-layer film structure or a multi-layer film structure.
Step S102, as shown in fig. 4, removing a portion of the dielectric layer 14 to form a first trench 26 and a second trench 27 in the dielectric layer 14, where the first trench 26 exposes a portion of the first device 11 and the second trench 27 exposes a portion of the first barrier layer 13;
specifically, the first barrier layer 13 covering only the second source region 21 is a first barrier structure, the first barrier layer 13 covering only the second gate structure is a second barrier structure, the first barrier layer 13 covering only the second drain region 22 is a third barrier structure, and a portion of the dielectric layer 14 is removed to form a first trench 26 and a second trench 27 in the dielectric layer 14, including: as shown in fig. 3, a patterned first mask layer 28 is formed on the surface of the dielectric layer 14 remote from the first barrier layer 13; as shown in fig. 3 and fig. 4, the patterned first mask layer 28 is used as a mask, the dielectric layer 14 and the second barrier layer 25 are sequentially etched, so as to form a first sub-trench 29, a second sub-trench 30, a third sub-trench 31, a fourth sub-trench 32, a fifth sub-trench 33 and a sixth sub-trench 34 in the dielectric layer 14 and the second barrier layer 25, wherein the first sub-trench 29 exposes a part of the surface of the first silicide layer 23, the second sub-trench 30 exposes a part of the surface of the third silicide layer 16, the third sub-trench 31 exposes a part of the surface of the second silicide layer 24, the fourth sub-trench 32 exposes a part of the first barrier structure, the fifth sub-trench 33 exposes a part of the second barrier structure, the sixth sub-trench 34 exposes a part of the third barrier structure, and the first sub-trench 29, the second sub-trench 30 and the fourth sub-trench 26 and the fourth sub-trench 34 constitute the remaining dielectric layer 46; the patterned first mask layer 28 is removed.
Any suitable material may be selected by those skilled in the art to form the first blocking layer 13, the second blocking layer 25 and the dielectric layer 14, and in the embodiment of the present application, the material of the first blocking layer 13 includes TEOS oxide and the material of the dielectric layer 14 includes silicon oxide. The material of the second barrier layer 25 comprises silicon nitride. Because the oxide and the silicon nitride and the TEOS oxide and the silicon nitride have higher selection ratios, the semiconductor device can be accurately stopped on the surface of the first device and the surface of the first barrier layer 13 in the process of etching to form the first sub-groove, the second sub-groove, the third sub-groove, the fourth sub-groove, the fifth sub-groove and the sixth sub-groove, and the problem that the device on the semiconductor is damaged by overetching is further avoided.
The materials of the first silicide layer 23, the second silicide layer 24 and the third silicide layer 16 may be the same or different, and the materials of the first silicide layer 23, the second silicide layer 24 and the third silicide layer 16 respectively include metal silicide, and in this embodiment of the present application, the materials of the first silicide layer 23, the second silicide layer 24 and the third silicide layer 16 are all nickel silicide. Of course, the materials of the first silicide layer 23, the second silicide layer 24, and the third silicide layer 16 are not limited to nickel silicide, and may be other metal silicide materials.
In yet another embodiment, the material of the first barrier layer 13 is TEOS oxide, the material of the dielectric layer 14 is silicon oxide, and the material of the second barrier layer 25 is silicon nitride. The materials of the first gate portion 15 and the second gate portion 17 are polysilicon, respectively.
The first mask layer 28 may be a single-layer film structure or a multi-layer film structure, and in this embodiment of the present application, as shown in fig. 3, the first mask layer 28 is a multi-layer film structure, and is respectively a carbon coating 35, a dielectric anti-reflection coating 36, a bottom anti-reflection coating 37, and a photoresist layer 38 sequentially stacked along a direction away from the dielectric layer 14.
Step S103, forming a protection structure 39 covering the first trench 26, and then removing the exposed first barrier layer 13 through the second trench 27, so that a portion of the second device 12 is exposed;
by forming the protective structure for covering the first groove, the problem of over etching the first device in the process of removing the first barrier layer is avoided, the high manufacturing yield of the semiconductor device is ensured, and the semiconductor device with high quality can be obtained.
According to yet another specific embodiment of the present application, forming the protection structure 39 covering the first trench 26, and then removing the exposed first barrier layer 13 through the second trench 27, so that a portion of the second device 12 is exposed, includes: as shown in fig. 5, photoresist is filled in the first sub-trench 29, the second sub-trench 30 and the third sub-trench 31 to form the protection structure 39; etching the substrate with the protection structure 39 along the fourth sub-trench 32, the fifth sub-trench 33 and the sixth sub-trench 34 to remove the exposed first barrier layer 13, so that part of the surfaces of the second source region 21, the second drain region 22 and the second gate structure are exposed, wherein the fourth sub-trench 32 with the exposed first barrier layer 13 removed forms a seventh sub-trench 40, the fifth sub-trench 33 with the exposed first barrier layer 13 removed forms an eighth sub-trench 41, the sixth sub-trench 34 with the exposed first barrier layer 13 removed forms a ninth sub-trench 42, and the seventh sub-trench 40, the eighth sub-trench 41 and the ninth sub-trench 42 form a third trench 43.
Specifically, as shown in fig. 5, the first sub-trench 29, the second sub-trench 30, and the third sub-trench 31 are filled with photoresist, so as to form the protection structure 39, which includes: forming a photoresist material layer on the exposed surface of the dielectric structure 46 in which the first trench 26 and the second trench 27 are formed, wherein the photoresist material layer fills the first trench and the second trench and covers the exposed surface of the dielectric structure 46; one of the following is performed: exposing the photoresist material layer filled in the second trench in the case that the photoresist material layer is a positive photoresist so that the unexposed photoresist material layer remains, forming the protection structure 39; in the case where the photoresist material layer is negative photoresist, the photoresist material layer other than the photoresist material layer filled in the second trench is exposed, so that only the photoresist material layer in the second trench is removed, forming the protective structure 39.
Step S104, as shown in fig. 5 and fig. 6, is to etch and remove the protection structure 39, and perform post-etching treatment on the substrate from which the protection structure 39 is removed, thereby obtaining a semiconductor device.
In a specific embodiment, etching to remove the protection structure 39 includes: the protective structure 39 is etched away using a plasma etch. In this embodiment, the protection structure 39 is etched and removed by a plasma etching method, so that the pollution to the etched semiconductor device is small, the etching residues are less, and the etching rate is high.
In addition, as shown in fig. 6, after the semiconductor device is obtained, the method further includes: as shown in fig. 6 and fig. 7, the first trench 26 and the third trench 43 are filled with a conductive material, the first trench 26 filled with the conductive material forms a first contact hole 44, the second trench 27 filled with the conductive material forms a second contact hole 45, and the third trench 43 is the second trench 27 from which the exposed first barrier layer is removed. And the first groove and the third groove are filled with conductive materials to form contact holes, so that the electrical extraction of the first device and the second device is realized.
Specifically, filling the first trench 26 and the third trench 43 with a conductive material includes: filling the first, second, third, seventh, eighth, and ninth sub-trenches 29, 30, 31, 40, 41, 42 with the conductive material filling the first, second, seventh, eighth, and ninth sub-trenches 29, 30, 31, 40, 41, 42; the conductive material overlying the surface of the dielectric layer 14 is removed.
The method for manufacturing the semiconductor device comprises the steps of firstly providing a substrate comprising a substrate 10, a first device 11 obtained through self-aligned silicide process treatment, a second device 12 obtained through non-self-aligned silicide process treatment, a first barrier layer 13 and a dielectric layer 14, wherein the first device 11 and the second device 12 are arranged on the substrate 10 at intervals, the first barrier layer 13 is positioned on the exposed surface of the second device 12, and the dielectric layer 14 is positioned on the exposed surfaces of the first device 11, the substrate 10 and the first barrier layer 13; thereafter, removing a portion of the dielectric layer 14 to form a first trench 26 extending into the dielectric layer 14 and exposing the first device 11, and a second trench 27 extending into the dielectric layer 14 and exposing the second device 12; then forming a protection structure 39 covering the first trench 26, and then removing the exposed first barrier layer 13 through the second trench 27; finally, the protective structure 39 is removed by etching and post-etching treatment is performed, so that the semiconductor device is obtained. Because the second device 12 has more one layer of first barrier layer 13 than the first device 11, in the process of forming the contact hole penetrating to the first device 11 and the second device 12, firstly, part of the dielectric layer 14 is removed, the first groove 26 exposing the first device 11 and the second groove 27 exposing the first barrier layer 13 are formed, the exposed first barrier layer 13 is continuously removed after the protective structure 39 is filled in the first groove 26, so that the second device 12 is exposed, the protective structure 39 protects the first device 11 from being damaged in the process of etching the first barrier layer 13, the problem that the first device 11 is damaged in the process of removing the first barrier layer 13 and exposing the second device 12 is avoided, meanwhile, the first device 11 and the second device 12 can be exposed, the contact hole can be formed conveniently and successfully, and the high manufacturing yield of the semiconductor device is ensured. And, the post-etching treatment is performed after the protective structure 39 is etched and removed, so that the oxide thin layer formed on the exposed surface of the second device 12 in the removing process can be removed, and the contact Kong Zu value of the whole semiconductor device is low.
According to another exemplary embodiment of the present application, there is also provided a CMOS image sensor including: the semiconductor device manufactured by any manufacturing method.
The CMOS image sensor includes a semiconductor device manufactured by the method, because the second device 12 has more than one layer of the first barrier layer 13 than the first device 11, in the process of forming a contact hole penetrating to the first device 11 and the second device 12, part of the dielectric layer 14 is removed first, the first trench 26 exposing the first device 11 and the second trench 27 exposing the first barrier layer 13 are formed, the exposed first barrier layer 13 is continuously removed after the first trench 26 is filled with the protective structure 39, so that the second device 12 is exposed, the protective structure 39 protects the first device 11 from being damaged in the process of etching the first barrier layer 13, the problem that the first device 11 is damaged in the process of removing the first barrier layer 13 and exposing the second device 12 is avoided, meanwhile, the first device 11 and the second device 12 can be exposed, the contact hole can be formed successfully and conveniently and subsequently, the high manufacturing yield of the CMOS image sensor is ensured, and the high manufacturing yield of the CMOS image sensor is ensured. And, the present application performs post-etching treatment after etching to remove the protective structure 39, so that the oxide thin layer formed on the exposed surface of the second device 12 in the removal process can be removed, thereby ensuring that the contact Kong Zu value of the whole semiconductor device is lower, and ensuring that the performance of the CMOS image sensor is better.
In the embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a part of the detailed description of some embodiment, reference may be made to the related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed technology content may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, for example, may be a logic function division, and may be implemented in another manner, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
From the above description, it can be seen that the embodiments described herein achieve the following technical effects:
the manufacturing method of the semiconductor device comprises the steps of firstly providing a substrate, a first device obtained through self-aligned silicide process treatment, a second device obtained through non-self-aligned silicide process treatment, a first blocking layer and a substrate of a dielectric layer, wherein the first device and the second device are arranged on the substrate at intervals, the first blocking layer is positioned on the exposed surface of the second device, and the dielectric layer is positioned on the exposed surfaces of the first device, the substrate and the first blocking layer; then, removing part of the dielectric layer to form a first groove which extends into the dielectric layer and exposes the first device and a second groove which extends into the dielectric layer and exposes the second device; then forming a protection structure covering the first groove, and removing the exposed first barrier layer through the second groove; and finally, etching to remove the protective structure and performing post-etching treatment to obtain the semiconductor device. Because the second device has more one deck first barrier layer than first device, this application is in the in-process that forms the contact hole that runs through to first device and second device, gets rid of partial dielectric layer earlier, forms the first slot of exposing first device and exposes the second slot of first barrier layer, fills protection architecture in the first slot and continues again to get rid of naked first barrier layer for the second device is naked, and the in-process of etching first barrier layer protection architecture protects first device not damaged, has avoided getting rid of first barrier layer, makes the problem of the naked in-process of second device damage first device excessively, has guaranteed simultaneously that first device and second device can both be naked, and the convenience can successfully form the contact hole afterwards, has guaranteed that the preparation yield of semiconductor device is higher. And, the post-etching treatment is carried out after the protective structure is etched and removed, so that the oxide thin layer formed on the exposed surface of the second device in the removing process can be removed, and the contact Kong Zu value of the whole semiconductor device is ensured to be lower.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (8)
1. A method of fabricating a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a substrate, a first device, a second device, a first barrier layer and a dielectric layer, the first device and the second device are arranged on the substrate at intervals, the first device is a device obtained through self-aligned silicide process treatment, the second device is a device obtained through no self-aligned silicide process treatment, the first barrier layer is positioned on the exposed surface of the second device, and the dielectric layer is positioned on the exposed surfaces of the first device, the substrate and the first barrier layer;
removing part of the dielectric layer to form a first groove and a second groove which are positioned in the dielectric layer, wherein the first groove exposes part of the first device, and the second groove exposes part of the first barrier layer;
forming a protection structure covering the first groove, and removing the exposed first barrier layer through the second groove to expose part of the second device;
etching to remove the protective structure, and performing post-etching treatment on the substrate from which the protective structure is removed to obtain a semiconductor device,
providing a substrate comprising:
providing the substrate, wherein the substrate comprises a first device region and a second device region which are arranged at intervals;
forming a first gate structure on the first device region, a first source region and a first drain region on both sides of the first gate structure, and forming a second gate structure on the second device region, a second source region and a second drain region on both sides of the second gate structure, the second source region and the second drain region forming the second device;
forming the first barrier layer on the exposed surface of the second device, and processing the substrate with the first barrier layer by adopting a self-aligned silicide process to form a first silicide layer on the surface of the first source region away from the substrate, a second silicide layer on the surface of the first drain region away from the substrate and a third silicide layer on the surface of the first gate structure away from the substrate, wherein the first gate structure, the first source region, the first drain region, the first silicide layer, the second silicide layer and the third silicide layer form the first device;
sequentially stacking a second barrier layer and the dielectric layer on the exposed surfaces of the substrate, the first device and the first barrier layer to obtain the substrate,
the first barrier layer covering only the second source region is a first barrier structure, the first barrier layer covering only the second gate structure is a second barrier structure, the first barrier layer covering only the second drain region is a third barrier structure, and a portion of the dielectric layer is removed to form a first trench and a second trench in the dielectric layer, comprising:
forming a patterned first mask layer on the surface of the dielectric layer away from the first barrier layer;
sequentially etching the dielectric layer and the second barrier layer by taking the patterned first mask layer as a mask to form a first sub-groove, a second sub-groove, a third sub-groove, a fourth sub-groove, a fifth sub-groove and a sixth sub-groove which are positioned in the dielectric layer and the second barrier layer, wherein the first sub-groove exposes part of the surface of the first silicide layer, the second sub-groove exposes part of the surface of the third silicide layer, the third sub-groove exposes part of the surface of the second silicide layer, the fourth sub-groove exposes part of the first barrier structure, the fifth sub-groove exposes part of the second barrier structure, the sixth sub-groove exposes part of the third barrier structure, and the first sub-groove, the second sub-groove and the third sub-groove form the first groove, the fourth sub-groove and the sixth sub-groove form the second groove;
and removing the patterned first mask layer.
2. The method of claim 1, wherein forming a protective structure overlying the first trench, and thereafter removing the exposed first barrier layer through the second trench to expose portions of the second device, comprises:
filling photoresist in the first sub-groove, the second sub-groove and the third sub-groove to form the protection structure;
and etching the substrate with the protective structure along the fourth sub-groove, the fifth sub-groove and the sixth sub-groove to remove the exposed first barrier layer so that part of the surfaces of the second source electrode region, the second drain electrode region and the second grid electrode structure are exposed.
3. The method of claim 1, wherein forming a first gate structure over the first device region and forming a second gate structure over the second device region comprises:
sequentially stacking a gate oxide layer and a polysilicon layer on the substrate;
forming a patterned second mask layer on the surface of the polysilicon layer far away from the gate oxide layer;
sequentially etching the polysilicon layer and the gate oxide layer by taking the patterned second mask layer as a mask to form a first gate part and a first gate oxide part on the first device region, and a second gate part and a second gate oxide part on the second device region, wherein the first gate part and the first gate oxide part form the first gate structure, and the second gate part and the second gate oxide part form the second gate structure;
and removing the patterned second mask layer.
4. A method according to any one of claims 1 to 3, wherein etching away the protective structure comprises:
and etching and removing the protective structure by adopting a plasma etching method.
5. A method according to any one of claims 1 to 3, characterized in that after obtaining the semiconductor device, the method further comprises:
and filling conductive materials in the first groove and the third groove respectively, wherein the first groove filled with the conductive materials forms a first contact hole, the second groove filled with the conductive materials forms a second contact hole, and the third groove is the second groove after the exposed first barrier layer is removed.
6. A method according to any of claims 1 to 3, wherein the material of the first barrier layer comprises TEOS oxide and the material of the dielectric layer comprises silicon oxide.
7. A method according to any of claims 1 to 3, wherein the material of the second barrier layer comprises silicon nitride.
8. A CMOS image sensor, comprising: a semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 7.
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