CN113496941A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
- Publication number
- CN113496941A CN113496941A CN202010191214.7A CN202010191214A CN113496941A CN 113496941 A CN113496941 A CN 113496941A CN 202010191214 A CN202010191214 A CN 202010191214A CN 113496941 A CN113496941 A CN 113496941A
- Authority
- CN
- China
- Prior art keywords
- mask layer
- initial
- mask
- layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 33
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 230000002829 reductive effect Effects 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 27
- 239000002019 doping agent Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 230000036961 partial effect Effects 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000001000 micrograph Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000007654 immersion Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method for forming a semiconductor structure, which comprises the following steps: implanting doping ions into the second initial top mask layer to form a doped region in the second initial top mask layer; etching to remove the second initial top mask layer outside the doped region, and enabling the doped region to form a second top mask layer; etching the second initial bottom mask layer by taking the second top mask layer as a mask to form a second bottom mask layer by the second initial bottom mask layer; and after reducing the widths of the second bottom mask layer and the second top mask layer, etching the first initial mask structure by taking the second bottom mask layer and the second top mask layer as masks, so that the first initial mask structure forms a first mask structure. By adopting the scheme, the line width of the graph of the first mask structure is reduced. And the first mask structure is used as a mask for etching the substrate, so that the size of a pattern formed in the substrate is reduced, and the requirements of the process are met. Thus, the performance of the semiconductor device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor structure.
Background
In order to comply with the development of morgan's law, semiconductor devices have been developed to 7 nm process nodes. In the current semiconductor devices with smaller device sizes, for example, Fin-Field-Effect transistors (finfets), contact multi-pitch (CPP) of 57 nm and high-density Static Random-Access Memory (SRAM) of 0.027 square micron have become the most popular and widespread applications.
The formation of the mask structure is the most difficult step in the semiconductor manufacturing process. Although the immersion multi-patterning lithography technique is adopted in the prior art, there are some mask patterns that cannot meet the standard in size, especially mask patterns with a 30 nm width of the patterned structure of the mask structure.
If the photolithography technique is not developed any further, the minimum limit of the width of the patterned structure of the mask structure formed by the current immersion multi-patterning photolithography technique is 40 nm, and even after the subsequent etching process, the final width is only 38 nm at the minimum, which is still far from the target size. The width of the patterned structure of the mask structure exceeds 30 nm, which may result in that the semiconductor device cannot be scaled down as desired, and the volume of the semiconductor device is large, which may affect the performance and market share of the semiconductor device.
Disclosure of Invention
The invention aims to solve the problem of poor performance of a semiconductor device caused by the fact that the width of a patterning structure of a mask structure is wide in the prior art. The invention provides a method for forming a mask pattern, which can reduce the line width of a pattern of a mask structure, further reduce the size of the pattern formed in a substrate and further improve the performance of a semiconductor device.
In order to solve the above technical problem, an embodiment of the present invention discloses a method for forming a semiconductor structure, including:
providing a substrate;
forming a first initial mask structure and a second initial mask structure on the first initial mask structure on the substrate, the second initial mask structure comprising a second initial lower mask layer and a second initial upper mask layer on the second initial lower mask layer;
implanting doping ions into a partial region of the second initial top mask layer to form a doped region in the second initial top mask layer;
etching the second initial top mask layer except the doped region, and enabling the doped region to form a second top mask layer;
etching the second initial bottom mask layer by taking the second top mask layer as a mask so as to form a second bottom mask layer by the second initial bottom mask layer;
reducing the width of the second bottom mask layer and the second top mask layer;
and after the widths of the second bottom mask layer and the second top mask layer are reduced, etching the first initial mask structure by taking the second bottom mask layer and the second top mask layer as masks, so that the first initial mask structure forms a first mask structure.
Optionally, the material of the second initial bottom mask layer includes silicon oxide, and the material of the second initial top mask layer includes an amorphous silicon layer.
Optionally, the first initial mask structure comprises a first initial lower mask layer and a first initial upper mask layer located on the first initial lower mask layer; the material of the first initial top mask layer and the material of the second initial bottom mask layer are different.
Optionally, the first initial underlying mask layer and the second initial underlying mask layer are made of the same material; the second initial top mask layer and the first initial top mask layer are the same material.
Optionally, the method for etching the first initial mask structure by using the second bottom mask layer and the second top mask layer as masks includes: etching the first initial top mask layer by using the second bottom mask layer and the second top mask layer as masks to form the first initial top mask layer; and etching and removing the first initial bottom mask layer at the side part of the first top mask layer to form the first initial bottom mask layer on the first initial bottom mask layer.
Optionally, the process of reducing the widths of the second bottom mask layer and the second top mask layer is a lateral etching process.
Optionally, the lateral etching process includes an isotropic wet etching process or an isotropic dry etching process.
Optionally, the method for implanting the dopant ions into the second initial top mask layer includes: forming a patterned structure on the second initial top-level mask layer; implanting the dopant ions into the second initial top-level mask layer using the patterned structure as a mask; and removing the patterned structure after the doping ions are implanted into the second initial top mask layer.
Optionally, the doped regions include a first doped region to an nth doped region, and the first doped region to the nth doped region are separated from each other;
and implanting the doping ions into the second initial top mask layer by adopting a plurality of ion implantation processes to form the doping regions.
Optionally, providing the substrate comprises: a substrate; a plurality of gate structures located on the substrate; source and drain regions located at two sides of the gate structure; a dielectric layer which is positioned on the substrate and covers the grid structure and the source drain region; the first mask structure covers a part of the dielectric layer on the source drain region;
the method for forming the semiconductor structure further comprises the following steps: after the first mask structure is formed, plug grooves are formed in the dielectric layer between the grid structures, partial source and drain regions are exposed out of the plug grooves, and the plug grooves are divided by the first mask structure in the extending direction of the grid structures.
By adopting the technical scheme, the pattern of the second top mask layer formed by the doping region is transferred to the second bottom mask layer, and then the widths of the second bottom mask layer and the second top mask layer are reduced, so that the line width of the pattern of the first mask structure is reduced when the pattern is further transferred to the first mask structure. And the first mask structure is used as a mask for etching the substrate, so that the size of a pattern formed in the substrate is reduced, and the requirements of the process are met. Accordingly, the performance of the semiconductor structure is improved correspondingly.
Drawings
Fig. 1 to fig. 2 are schematic flow charts illustrating a conventional method for forming a semiconductor structure;
FIGS. 3 to 4 are scanning electron micrographs of a conventional semiconductor structure;
FIG. 5 is a schematic flow chart diagram illustrating a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 6 to 11 are schematic structural diagrams formed by steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 12 is a scanning electron microscope image of a semiconductor structure according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure. While the invention will be described in conjunction with the preferred embodiments, it is not intended that features of the invention be limited to these embodiments. On the contrary, the invention is described in connection with the embodiments for the purpose of covering alternatives or modifications that may be extended based on the claims of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The invention may be practiced without these particulars. Moreover, some of the specific details have been left out of the description in order to avoid obscuring or obscuring the focus of the present invention. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
It should be noted that in this specification, like reference numerals and letters refer to like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.
In the description of the present embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that are conventionally placed when the products of the present invention are used, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements indicated must have specific orientations, be configured in specific orientations, and operate, and thus, should not be construed as limiting the present invention.
The terms "first," "second," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present embodiment, it should be further noted that, unless explicitly stated or limited otherwise, the terms "disposed," "connected," and "connected" are to be interpreted broadly, e.g., as a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present embodiment can be understood in specific cases by those of ordinary skill in the art.
As described in the background art, the conventional mask structure has a wide patterning structure, which results in a large size and poor performance of the semiconductor device. Specifically, a schematic structure diagram of a method for forming a semiconductor structure is shown in fig. 1 to 2.
First, referring to fig. 1, a substrate 01 is provided, an initial mask layer 02 is formed on the substrate 01, and a patterned structure 03 is formed on the initial mask layer 02.
With continued reference to fig. 1, dopant ions are implanted into the initial mask layer 02 using the patterned structure 03 as a mask, forming doped regions 04 in the initial mask layer 02.
Referring to fig. 2, patterned structure 03 is removed, initial masking layer 02 is etched away outside of doped region 04, and doped region 04 is formed into masking structure 05.
The scanning electron microscope image of the semiconductor structure formed through the above process in the cross section direction is specifically shown in fig. 3, and the scanning electron microscope image in the top view direction is shown in fig. 4, which shows that the line width of the pattern of the mask structure formed in the prior art is large, which causes the size of the pattern formed in the substrate to be large, and further affects the performance of the semiconductor device.
To solve the above problems, embodiments of the present invention provide a method for forming a semiconductor structure. Referring to the flowchart of the method for forming a semiconductor structure shown in fig. 5, the method for forming a semiconductor structure provided in this embodiment includes the following steps:
step S1: providing a substrate;
step S2: forming a first initial mask structure and a second initial mask structure on the first initial mask structure on the substrate, the second initial mask structure including a second initial lower mask layer and a second initial upper mask layer on the second initial lower mask layer;
step S3: implanting doping ions into a partial region of the second initial top mask layer to form a doping region in the second initial top mask layer;
step S4: etching to remove the second initial top mask layer outside the doped region, and enabling the doped region to form a second top mask layer;
step S5: etching the second initial bottom mask layer by taking the second top mask layer as a mask so that the second initial bottom mask layer forms a second bottom mask layer;
step S6: reducing the width of the second bottom mask layer and the second top mask layer;
step S7: and after reducing the widths of the second bottom mask layer and the second top mask layer, etching the first initial mask structure by taking the second bottom mask layer and the second top mask layer as masks, so that the first initial mask structure forms a first mask structure.
By adopting the semiconductor structure formed by the scheme, the line width of the graph of the first mask structure is reduced. And the first mask structure is used as a mask for etching the substrate, so that the size of a pattern formed in the substrate is reduced, and the requirements of the process are met. Accordingly, the performance of the semiconductor structure is improved correspondingly.
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
First, as shown in fig. 6, a substrate 1 is provided.
With continued reference to fig. 6, a first initial mask structure 2 and a second initial mask structure 3 located on the first initial mask structure 2 are formed on a substrate 1, the second initial mask structure 3 comprising a second initial lower mask layer 31 and a second initial upper mask layer 32 located on the second initial lower mask layer 31.
Preferably, in this embodiment, the materials of the second initial bottom mask layer 31 and the second initial top mask layer 32 are different, wherein the material of the second initial bottom mask layer 31 comprises silicon oxide, and the material of the second initial top mask layer 32 comprises an amorphous silicon layer.
It should be noted that, in the present embodiment, the first initial mask structure 2 includes a first initial lower mask layer 21 and a first initial upper mask layer 22 located on the first initial lower mask layer 21; the material of the first initial top mask layer 22 is different from the material of the second initial bottom mask layer 31.
It should be noted that, in the present embodiment, the materials of the first initial lower mask layer 21 and the second initial lower mask layer 31 are the same; the second initial top mask layer 32 and the first initial top mask layer 22 are of the same material.
In this embodiment, the material of the first initial top mask layer 22 is an amorphous silicon layer; the material of the first initial underlying mask layer 21 is silicon oxide.
With continued reference to fig. 6, dopant ions are implanted into portions of the second initial top mask layer 32 to form doped regions 4 in the second initial top mask layer 32.
Specifically, in this embodiment, the method for implanting dopant ions into the second initial top mask layer 32 includes: forming a patterned structure 6 on the second initial top-level masking layer 32; implanting dopant ions into the second initial top mask layer 32 using the patterned structure 6 as a mask; after implanting dopant ions into the second initial top mask layer 32, patterned structure 6 is removed.
It is noted that patterned structure 6 in this embodiment includes a bottom layer pattern on top of second initial top mask layer 32, and a top layer pattern on top of the bottom layer pattern.
Preferably, the material of the bottom layer pattern in this embodiment is a spin-on carbon layer (SOC), and the material of the top layer pattern is an anti-reflective silicon coating (SiARC). Of course, in other embodiments of the present application, only one layer of patterned structure 6 may be optionally disposed, and multiple layers of patterned structures 6 may also be optionally disposed, which is not specifically limited in this embodiment.
The method for removing the patterned structure 6 in this embodiment includes, but is not limited to, etching, which is not specifically limited in this embodiment.
It should be noted that the doped region 4 in this embodiment includes a first doped region to an nth doped region, and the first doped region to the nth doped region are separated from each other.
That is, the number of the doped regions 4 in the present embodiment may be one, two, or more. When the number of the patterned structures 6 formed on the second initial top mask layer 32 is two, one doped region 4 is formed between two patterned structures 6; when the number of the patterned structures 6 is three, one doped region 4 is formed between two adjacent patterned structures 6, and so on.
And any two adjacent doped regions 4 are separated from each other by about the width of one patterned structure 6.
Preferably, in this embodiment, the doping ions are implanted into the second initial top mask layer 32 by sequentially adopting a plurality of ion implantation processes, so as to form the doped region 4.
Referring to fig. 7, the second initial top-level mask layer 32 outside the doped region 4 is etched away and the doped region 4 is formed into a second top-level mask layer 41.
Referring to fig. 8, the second initial lower mask layer 31 is etched using the second upper mask layer 41 as a mask, so that the second initial lower mask layer 31 forms a second lower mask layer 5.
Referring to fig. 9, the widths of the second bottom mask layer 5 and the second top mask layer 41 are reduced.
Preferably, in the present embodiment, the process of reducing the width of the second bottom mask layer 5 and the second top mask layer 41 is a lateral etching process.
Specifically, the lateral etching process includes an isotropic wet etching process or an isotropic dry etching process.
Further, it should be noted that, while the widths of the second bottom mask layer 5 and the second top mask layer 41 are reduced, the thickness of the second bottom mask layer 5 in the direction perpendicular to the substrate 1 and the thickness of the first initial top mask layer 22 in the direction perpendicular to the substrate 1 are also reduced.
Further, after reducing the widths of the second bottom mask layer 5 and the second top mask layer 41, etching the first initial mask structure 2 by using the second bottom mask layer 5 and the second top mask layer 41 as masks, so that the first initial mask structure 2 forms a first mask structure, including:
as shown in fig. 10, the first initial top mask layer 22 is etched using the second bottom mask layer 5 and the second top mask layer 41 as masks, so that the first initial top mask layer 22 forms the first top mask layer 8.
Further, while the first top mask layer 8 is formed by etching, the second top mask layer 41 and a part of the second bottom mask layer 5 may be etched and removed entirely. Alternatively, the second top mask layer 41 may be etched at the same time as the first top mask layer 8 is etched to partially remove the second top mask layer 41 or completely remove the second top mask layer 41.
Then, as shown in fig. 11, the first initial lower mask layer 21 is etched away from the side of the first upper mask layer 8, so that the first initial lower mask layer 21 forms the first lower mask layer 7.
Further, while the first lower mask layer 7 is formed by etching, a part of the second lower mask layer 5 may be also removed by etching.
Further, the substrate 1 provided in the present embodiment includes: a substrate; a plurality of gate structures located on the substrate; source and drain regions located at two sides of the gate structure; a dielectric layer which is positioned on the substrate and covers the grid structure and the source drain region; the first mask structure 23 covers a portion of the dielectric layer over the source and drain regions.
The material of the substrate in this embodiment includes, but is not limited to, silicon oxide, germanium, and other materials commonly used in semiconductor substrates, which are not limited to this example.
The gate structure may be a dummy gate or a metal gate structure.
The material of the dielectric layer includes, but is not limited to, silicon dioxide, or other dielectric layer materials.
It should be noted that the specific structure of the substrate 1 is not shown in the drawings of the present embodiment, and in fact, the substrate 1 may also include other structures, such as an isolation structure, and of course, the above structure may not be completely included. This embodiment is not particularly limited thereto.
It should be noted that, in this embodiment, after the first mask structure 23 is formed, plug grooves are formed in the dielectric layer between the gate structures, the plug grooves expose part of the source/drain regions, and the plug grooves are divided by the first mask structure 23 in the extending direction of the gate structures.
In the semiconductor structure formed by the above technical solution, as shown in fig. 12, which is a scanning electron microscope image of the semiconductor structure provided by the embodiment of the present invention, it can be seen that the line width of the pattern of the first mask structure is small. In the method, the pattern of the second top mask layer formed by the doped region is transferred to the second bottom mask layer, and then the widths of the second bottom mask layer and the second top mask layer are reduced, so that the line width of the pattern of the first mask structure is reduced when the pattern is further transferred to the first mask structure. And the first mask structure is used as a mask for etching the substrate, so that the size of a pattern formed in the substrate is reduced, and the requirements of the process are met. Accordingly, the performance of the semiconductor structure is improved correspondingly.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing is a more detailed description of the invention, taken in conjunction with the specific embodiments thereof, and that no limitation of the invention is intended thereby. Various changes in form and detail, including simple deductions or substitutions, may be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a first initial mask structure and a second initial mask structure on the first initial mask structure on the substrate, the second initial mask structure comprising a second initial lower mask layer and a second initial upper mask layer on the second initial lower mask layer;
implanting doping ions into a partial region of the second initial top mask layer to form a doped region in the second initial top mask layer;
etching the second initial top mask layer except the doped region, and enabling the doped region to form a second top mask layer;
etching the second initial bottom mask layer by taking the second top mask layer as a mask so as to form a second bottom mask layer by the second initial bottom mask layer;
reducing the width of the second bottom mask layer and the second top mask layer;
and after the widths of the second bottom mask layer and the second top mask layer are reduced, etching the first initial mask structure by taking the second bottom mask layer and the second top mask layer as masks, so that the first initial mask structure forms a first mask structure.
2. The method of forming a semiconductor structure of claim 1, wherein the material of the second initial bottom mask layer comprises silicon oxide and the material of the second initial top mask layer comprises an amorphous silicon layer.
3. The method of forming a semiconductor structure of claim 1, wherein said first initial mask structure comprises a first initial lower mask layer and a first initial upper mask layer located over said first initial lower mask layer; the material of the first initial top mask layer and the material of the second initial bottom mask layer are different.
4. The method of forming a semiconductor structure of claim 3, wherein the first initial underlying mask layer and the second initial underlying mask layer are the same material; the second initial top mask layer and the first initial top mask layer are the same material.
5. The method for forming a semiconductor structure of claim 3, wherein the etching the first initial mask structure using the second bottom mask layer and the second top mask layer as masks comprises: etching the first initial top mask layer by using the second bottom mask layer and the second top mask layer as masks to form the first initial top mask layer; and etching and removing the first initial bottom mask layer at the side part of the first top mask layer to form the first initial bottom mask layer on the first initial bottom mask layer.
6. The method of claim 1, wherein the process of reducing the width of the second bottom mask layer and the second top mask layer is a lateral etch process.
7. The method of forming a semiconductor structure of claim 6, wherein the lateral etching process comprises an isotropic wet etching process or an isotropic dry etching process.
8. The method of forming a semiconductor structure of claim 1, wherein implanting the dopant ions into the second initial top mask layer comprises: forming a patterned structure on the second initial top-level mask layer; implanting the dopant ions into the second initial top-level mask layer using the patterned structure as a mask; and removing the patterned structure after the doping ions are implanted into the second initial top mask layer.
9. The method of claim 1, wherein the doped regions comprise first to nth doped regions, the first to nth doped regions being separated from each other;
and implanting the doping ions into the second initial top mask layer by adopting a plurality of ion implantation processes to form the doping regions.
10. The method of forming a semiconductor structure of claim 1 or 9, wherein providing the substrate comprises: a substrate; a plurality of gate structures located on the substrate; source and drain regions located at two sides of the gate structure; a dielectric layer which is positioned on the substrate and covers the grid structure and the source drain region; the first mask structure covers a part of the dielectric layer on the source drain region;
the method for forming the semiconductor structure further comprises the following steps: after the first mask structure is formed, plug grooves are formed in the dielectric layer between the grid structures, partial source and drain regions are exposed out of the plug grooves, and the plug grooves are divided by the first mask structure in the extending direction of the grid structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010191214.7A CN113496941A (en) | 2020-03-18 | 2020-03-18 | Method for forming semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010191214.7A CN113496941A (en) | 2020-03-18 | 2020-03-18 | Method for forming semiconductor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113496941A true CN113496941A (en) | 2021-10-12 |
Family
ID=77992937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010191214.7A Pending CN113496941A (en) | 2020-03-18 | 2020-03-18 | Method for forming semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113496941A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59113645A (en) * | 1982-12-20 | 1984-06-30 | Matsushita Electric Ind Co Ltd | Forming method of wiring pattern |
| US20070231749A1 (en) * | 2006-04-03 | 2007-10-04 | Nanya Technology Corporation | Method for forming a semiconductor device |
| US20080017992A1 (en) * | 2006-07-18 | 2008-01-24 | Masaru Kito | Semiconductor device and method of manufacturing the same |
| CN101271839A (en) * | 2007-03-19 | 2008-09-24 | 海力士半导体有限公司 | Method for manufacturing semiconductor device |
| JP2008288526A (en) * | 2007-05-21 | 2008-11-27 | Sharp Corp | Manufacturing method of semiconductor device |
| CN102446724A (en) * | 2010-09-30 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing gate electrode |
| US20160351791A1 (en) * | 2015-05-25 | 2016-12-01 | Globalfoundries Singapore Pte. Ltd. | Small pitch and high density contact array |
| US20180130668A1 (en) * | 2015-05-01 | 2018-05-10 | The Regents Of The University Of California | Enhanced patterning of integrated circuit layer by tilted ion implantation |
| CN110416067A (en) * | 2018-04-30 | 2019-11-05 | 台湾积体电路制造股份有限公司 | The manufacturing method of semiconductor device |
-
2020
- 2020-03-18 CN CN202010191214.7A patent/CN113496941A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59113645A (en) * | 1982-12-20 | 1984-06-30 | Matsushita Electric Ind Co Ltd | Forming method of wiring pattern |
| US20070231749A1 (en) * | 2006-04-03 | 2007-10-04 | Nanya Technology Corporation | Method for forming a semiconductor device |
| US20080017992A1 (en) * | 2006-07-18 | 2008-01-24 | Masaru Kito | Semiconductor device and method of manufacturing the same |
| CN101271839A (en) * | 2007-03-19 | 2008-09-24 | 海力士半导体有限公司 | Method for manufacturing semiconductor device |
| JP2008288526A (en) * | 2007-05-21 | 2008-11-27 | Sharp Corp | Manufacturing method of semiconductor device |
| CN102446724A (en) * | 2010-09-30 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing gate electrode |
| US20180130668A1 (en) * | 2015-05-01 | 2018-05-10 | The Regents Of The University Of California | Enhanced patterning of integrated circuit layer by tilted ion implantation |
| US20160351791A1 (en) * | 2015-05-25 | 2016-12-01 | Globalfoundries Singapore Pte. Ltd. | Small pitch and high density contact array |
| CN110416067A (en) * | 2018-04-30 | 2019-11-05 | 台湾积体电路制造股份有限公司 | The manufacturing method of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI356446B (en) | Methods to reduce the critical dimension of semico | |
| US10559571B2 (en) | Methods of fabricating semiconductor memory devices | |
| TWI471903B (en) | Frequency doubling using spacer mask | |
| TWI540650B (en) | Method for manufacturing finfet device | |
| US20090017631A1 (en) | Self-aligned pillar patterning using multiple spacer masks | |
| US7846849B2 (en) | Frequency tripling using spacer mask having interposed regions | |
| TW201203311A (en) | Method for forming contact hole of semiconductor device | |
| TWI508131B (en) | Method for forming fine pattern | |
| WO2011002590A1 (en) | Method of forming contact hole arrays using a hybrid spacer technique | |
| US20060211229A1 (en) | Method for fabricating semiconductor device | |
| CN116825786B (en) | Semiconductor structure and preparation method thereof | |
| US11145760B2 (en) | Structure having improved fin critical dimension control | |
| CN108074798B (en) | Method for manufacturing self-aligned exposure semiconductor structure | |
| JP2006135067A (en) | Semiconductor device and manufacturing method thereof | |
| CN111668093A (en) | Semiconductor device and method of forming the same | |
| CN113496941A (en) | Method for forming semiconductor structure | |
| US20210175080A1 (en) | Semiconductor structure and forming method thereof | |
| TWI548039B (en) | Method for fabricating semiconductor device | |
| TWI449085B (en) | Process for semiconductor device | |
| WO2022095609A1 (en) | Method for manufacturing capacitance connection line of memory, and memory | |
| JPH03178129A (en) | Semiconductor device and manufacture thereof | |
| KR100356475B1 (en) | Method of manufacturing a transistor | |
| TWI552313B (en) | Method of simultaneously manufacturing semiconductor devices in cell region and peripheral region | |
| TWI565006B (en) | Method for fabricating memory device | |
| CN117042449A (en) | Method for preparing semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |