CN116314032A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN116314032A
CN116314032A CN202310174180.4A CN202310174180A CN116314032A CN 116314032 A CN116314032 A CN 116314032A CN 202310174180 A CN202310174180 A CN 202310174180A CN 116314032 A CN116314032 A CN 116314032A
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device region
buffer layer
region
layer
nmos device
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冯远皓
薛广杰
李乐
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a substrate, wherein the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region; forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure; removing the buffer layer on the NMOS device region; forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region. The technical scheme of the invention can improve the performance of one of the NMOS device and the PMOS device, avoid reducing the performance of the other device, and simultaneously avoid increasing the manufacturing cost of the chip.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method of fabricating the same.
Background
Currently, stress memorization techniques (SMT, stress Memorization Technology) are commonly used to improve the electron mobility of NMOS devices and the hole mobility of PMOS devices. Taking the example of improving the electron mobility of the NMOS device, the method comprises the following steps: after the side wall and source drain ion implantation process is completed, depositing a silicon nitride layer with high tensile stress on the NMOS device region and the PMOS device region, transmitting the tensile stress to the source drain and the grid electrode of the NMOS device through a high-temperature annealing process, improving the electron mobility of the NMOS device, and finally removing the silicon nitride layer. However, tensile stress in the silicon nitride layer is also transferred to the source drain and gate of the PMOS device, which reduces the hole mobility of the PMOS device, thereby affecting the performance of the PMOS device.
Wherein, in order to transfer more tensile stress into the NMOS device region to further enhance the electron mobility of the NMOS device, a thicker silicon nitride layer is deposited; but at the same time may cause tensile stress in the thicker silicon nitride layer to be transferred to the PMOS device region, thereby affecting the performance of the PMOS device. Therefore, in order to improve the performance of the NMOS device and avoid reducing the performance of the PMOS device, an additional photolithography and etching process is added after depositing the thicker silicon nitride layer and before the high temperature annealing process to remove the silicon nitride layer on the PMOS device region, and only the silicon nitride layer on the NMOS device region is maintained. However, this method adds an additional photolithography and etching process, which in turn results in increased chip manufacturing costs.
Therefore, how to improve the performance of one of the NMOS device and the PMOS device and avoid reducing the performance of the other device, and also avoid increasing the manufacturing cost of the chip is a problem to be solved.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which can improve the performance of one of an NMOS device and a PMOS device and avoid the performance of the other device from being reduced and the manufacturing cost of a chip from being increased.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region;
forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;
forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region.
Optionally, when the stress layer is a tensile stress layer, before forming the stress layer on the buffer layer, the method for manufacturing the semiconductor device further includes:
forming a first source region and a first drain region in the substrate at two sides of the gate structure of the NMOS device region, wherein the first source region and the first drain region are formed by using the same patterned photoresist layer as a mask;
when the stress layer is a compressive stress layer, the method for manufacturing the semiconductor device further includes, before forming the stress layer on the buffer layer:
and forming a second source region and a second drain region in the substrate at two sides of the gate structure of the PMOS device region, wherein the second source region and the second drain region are formed by using the same patterned photoresist layer as a mask for forming the buffer layer.
Optionally, when the stress layer is a tensile stress layer;
the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises the following steps:
forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure;
removing the first buffer layer on the NMOS device region;
Forming a second buffer layer on the substrate and the gate structure of the NMOS device region and on the first buffer layer of the PMOS device region;
alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:
forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;
and removing part of the buffer layer with the thickness on the NMOS device region.
Optionally, before or after removing the first buffer layer on the NMOS device region, or before or after removing a portion of the buffer layer on the NMOS device region, the method for manufacturing a semiconductor device further includes:
and forming a first source region and a first drain region in the substrate at two sides of the grid structure of the NMOS device region, wherein the same patterned photoresist layer is used as a mask for forming the first source region and the first drain region and removing a first buffer layer on the NMOS device region or removing part of the buffer layer with the thickness on the NMOS device region.
Optionally, after removing the first buffer layer on the NMOS device region or after removing a portion of the thickness of the buffer layer on the NMOS device region, the method of manufacturing a semiconductor device further includes:
And forming a second source electrode region and a second drain electrode region in the substrate at two sides of the grid structure of the PMOS device region.
Optionally, when the stress layer is a compressive stress layer;
the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises the following steps:
forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure;
removing the first buffer layer on the PMOS device region;
forming a second buffer layer on the substrate and the gate structure of the PMOS device region and the first buffer layer of the NMOS device region;
alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:
forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;
and removing part of the buffer layer with the thickness on the PMOS device region.
Optionally, before or after removing the first buffer layer on the PMOS device region, or before or after removing a portion of the thickness of the buffer layer on the PMOS device region, the method further includes:
And forming a second source region and a second drain region in the substrate at two sides of the grid structure of the PMOS device region, wherein the same patterned photoresist layer is used as a mask for forming the second source region and the second drain region and removing the first buffer layer on the PMOS device region or removing part of the buffer layer with the thickness on the PMOS device region.
Optionally, after removing the first buffer layer on the PMOS device region or after removing a portion of the thickness of the buffer layer on the PMOS device region, the method of manufacturing a semiconductor device further includes:
and forming a first source electrode region and a first drain electrode region in the substrate at two sides of the grid structure of the NMOS device region.
Optionally, the method for manufacturing a semiconductor device further includes:
performing an annealing process;
and removing the stress layer.
The present invention also provides a semiconductor device including:
the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region;
the buffer layer is formed on the substrates of the NMOS device region and the PMOS device region and covers the grid structure;
A stress layer formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region.
Optionally, the material of the stress layer includes silicon nitride, and the material of the buffer layer includes silicon oxide.
Optionally, the semiconductor device further includes:
the first source electrode region and the first drain electrode region are formed in the substrate at two sides of the grid structure of the NMOS device region;
and the second source electrode region and the second drain electrode region are formed in the substrate at two sides of the grid structure of the PMOS device region.
Optionally, a P-well is formed in the substrate of the NMOS device region, and the first source region and the first drain region are formed on top of the P-well; an N-well is formed in the substrate of the PMOS device region, and the second source region and the second drain region are formed on top of the N-well.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the manufacturing method of the semiconductor device, the buffer layer is formed on the substrates of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; removing the buffer layer on the NMOS device region; forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region, so that the performance of one of the NMOS device and the PMOS device is improved, the performance of the other device is prevented from being reduced, and the manufacturing cost of the chip is prevented from being increased.
2. The semiconductor device of the present invention, since it comprises: the buffer layer is formed on the substrates of the NMOS device region and the PMOS device region and covers the grid structure; a stress layer formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region, so that the performance of one of the NMOS device and the PMOS device is improved, the performance of the other device is prevented from being reduced, and the manufacturing cost of the chip is prevented from being increased.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 2 a-2 i are schematic device diagrams illustrating an embodiment of a method of fabricating the semiconductor device shown in FIG. 1;
fig. 3a to 3g are schematic device diagrams of another embodiment of the method of manufacturing a semiconductor device shown in fig. 1.
Wherein, the reference numerals of the figures 1-3 g are as follows:
11-a substrate; a 111-P well; 112-N well; 113-trench isolation structures; 114-lightly doped source region; 115-lightly doped drain region; 116-a first source region; 117-a first drain region; 118-a second source region; 119-a second drain region; a 12-gate structure; 13-side walls; 14-a buffer layer; 141-a first buffer layer; 142-a second buffer layer; 151-a first patterned photoresist layer; 152-a second patterned photoresist layer; 16-stress layer.
Detailed Description
In order to make the objects, advantages and features of the present invention more apparent, the following more particular description of the semiconductor device and method of fabricating the same is provided. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, referring to fig. 1, as can be seen from fig. 1, the method for manufacturing a semiconductor device includes:
step S1, providing a substrate, wherein the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region;
step S2, forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;
s3, forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region.
The method of manufacturing the semiconductor device according to the present embodiment will be described in detail with reference to fig. 2a to 2i and fig. 3a to 3 g.
According to step S1, referring to fig. 2a, a substrate 11 is provided, wherein the substrate 11 includes an NMOS device region A1 and a PMOS device region A2, a gate structure 12 and a sidewall 13 are formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the sidewall 13 is formed on a sidewall of the gate structure 12.
The gate structure 12 includes a bottom-up gate oxide layer and a gate layer.
A trench isolation structure 113 may be formed in the substrate 11 between the NMOS device region A1 and the PMOS device region A2 to achieve mutual isolation between the NMOS device region A1 and the PMOS device region A2. The top surface of the trench isolation structure 113 is flush with the top surface of the substrate 11 or slightly higher than the top surface of the substrate 11.
A P-well 111 is formed in the substrate 11 of the NMOS device region A1, an N-well 112 is formed in the substrate 11 of the PMOS device region A2, and bottom surfaces of the P-well 111 and the N-well 112 may be lower than bottom surfaces of the trench isolation structures 113.
In addition, a lightly doped source region 114 and a lightly doped drain region 115 are formed on top of the P-well 111 at both sides of the gate structure 12 in the NMOS device region A1; a lightly doped source region 114 and a lightly doped drain region 115 are also formed on top of the N-well 112 on both sides of the gate structure 12 in the PMOS device region A2. And, in the NMOS device region A1 and the PMOS device region A2, the lightly doped source region 114 and the lightly doped drain region 115 each extend below the gate structure 12.
According to step S2, a buffer layer 14 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the buffer layer 14 covers the gate structure 12 and the sidewall 13. Wherein the buffer layer 14 serves to buffer and protect the device while also serving as a barrier.
Preferably, the material of the buffer layer 14 includes silicon oxide. The material of the buffer layer 14 may also include silicon oxides such as silicon oxynitride, fluorinated silicon glass, phosphosilicate glass, and borophosphosilicate glass.
In step S3, as shown in fig. 2i and 3g, a stress layer 16 is formed on the buffer layer 14. When the stress layer 16 is a tensile stress layer, the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1; when the stress layer 16 is a compressive stress layer, the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2.
When the stress layer 16 is a tensile stress layer, the method of manufacturing the semiconductor device further includes, prior to forming the stress layer 16 on the buffer layer 14: forming a first source region 116 and a first drain region 117 in the substrate 11 at two sides of the gate structure 12 of the NMOS device region A1, wherein the forming of the first source region 116 and the first drain region 117 and the forming of the buffer layer 14 use the same patterned photoresist layer as a mask; when the stress layer 16 is a compressive stress layer, the method of manufacturing a semiconductor device further includes, prior to forming the stress layer 16 on the buffer layer 14: a second source region 118 and a second drain region 119 are formed in the substrate 11 at two sides of the gate structure 12 of the PMOS device region A2, and the second source region 118 and the second drain region 119 are formed using the same patterned photoresist layer as the buffer layer 14 as a mask. Therefore, the mask and the photoetching step are not required to be additionally added, and the cost of the stress memorization process is further reduced.
In one embodiment, when the stress layer 16 is a tensile stress layer, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 in the step S2 may include: first, as shown in fig. 2b, a first buffer layer 141 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the first buffer layer 141 covers the gate structure 12 and the sidewall 13; then, as shown in fig. 2d, a first patterned photoresist layer 151 is formed, the first patterned photoresist layer 151 covers the first buffer layer 141 of the PMOS device region A2 and exposes the first buffer layer 141 of the NMOS device region A1, and an etching process is performed using the first patterned photoresist layer 151 as a mask to remove the first buffer layer 141 on the NMOS device region A1; then, as shown in fig. 2e, the first patterned photoresist layer 151 is removed; then, as shown in fig. 2h, a second buffer layer 142 is formed on the substrate 11, the gate structure 12 and the side wall 13 of the NMOS device region A1 and on the first buffer layer 141 of the PMOS device region A2, where the second buffer layer 142 on the NMOS device region A1 is used as the buffer layer 14 on the NMOS device region A1, and the first buffer layer 141 and the second buffer layer 142 on the PMOS device region A2 are used together as the buffer layer 14 on the PMOS device region A2, so that the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1.
Also, before (as shown in fig. 2 c) or after removing the first buffer layer 141 on the NMOS device region A1, the method of manufacturing a semiconductor device may further include: an ion implantation process is performed to form a first source region 116 and a first drain region 117 in the substrate 11 on a side of the sidewall 13 of the NMOS device region A1 away from the gate structure 12. As shown in fig. 2c and fig. 2d, the first source region 116 and the first drain region 117 are formed using the same patterned photoresist layer (i.e., the first patterned photoresist layer 151) as the mask used for removing the first buffer layer 141 on the NMOS device region A1.
Alternatively, when the stress layer 16 is a tensile stress layer, in the step S2, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 may include: firstly, as shown in fig. 3a, a buffer layer 14 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the buffer layer 14 covers the gate structure 12 and the sidewall 13; then, as shown in fig. 3c, a first patterned photoresist layer 151 is formed, where the first patterned photoresist layer 151 covers the buffer layer 14 of the PMOS device area A2 and exposes the buffer layer 14 of the NMOS device area A1, and an etching process is performed with the first patterned photoresist layer 151 as a mask to remove a portion of the buffer layer 14 with a thickness on the NMOS device area A1, so that the thickness of the buffer layer 14 on the PMOS device area A2 is greater than the thickness of the buffer layer 14 on the NMOS device area A1; then, as shown in fig. 3d, the first patterned photoresist layer 151 is removed.
And, before (as shown in fig. 3 b) or after removing a part of the buffer layer on the NMOS device region, the method for manufacturing the semiconductor device further includes: an ion implantation process is performed to form a first source region 116 and a first drain region 117 in the substrate 11 on a side of the sidewall 13 of the NMOS device region A1 away from the gate structure 12. As shown in fig. 3b and 3c, the buffer layer 14, which is formed by removing a portion of the thickness of the NMOS device region A1, and the first source region 116 and the first drain region 117 are formed by using the same patterned photoresist layer (i.e., the first patterned photoresist layer 151) as a mask.
As can be seen from the above steps, when the stress layer 16 is a tensile stress layer, the steps of forming the first source region 116 and the first drain region 117 and removing the first buffer layer 141 on the NMOS device region A1 or removing the buffer layer 14 with a partial thickness on the NMOS device region A1 all use the first patterned photoresist layer 151 as a mask, i.e. use the same photomask, so that no additional photomask and photolithography steps are required, thereby reducing the cost of the stress memorization process.
In addition, when the material of the buffer layer 14 is silicon oxide, hydrofluoric acid may be used to etch away the first buffer layer 141 and a portion of the thickness of the buffer layer 14 on the NMOS device region A1.
After removing the first buffer layer 141 on the NMOS device region A1 and before forming the second buffer layer 142, or after removing a portion of the thickness of the buffer layer 14 on the NMOS device region A1, the method of manufacturing a semiconductor device may further include: first, as shown in fig. 2f and 3e, a second patterned photoresist layer 152 is formed, wherein the second patterned photoresist layer 152 covers the NMOS device region A1 and exposes the PMOS device region A2; then, as shown in fig. 2f and fig. 3e, an ion implantation process is performed using the second patterned photoresist layer 152 as a mask, so as to form a second source region 118 and a second drain region 119 in the substrate 11 on a side of the sidewall 13 of the PMOS device region A2 away from the gate structure 12; the second patterned photoresist layer 152 is then removed, as shown in fig. 2g and 3 f.
In another embodiment (not shown), when the stress layer 16 is a compressive stress layer, in the step S2, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 includes: first, a first buffer layer 141 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the first buffer layer 141 covers the gate structure 12 and the sidewall 13; then, a first patterned photoresist layer 151 is formed, the first patterned photoresist layer 151 covers the first buffer layer 141 of the NMOS device region A1 and exposes the first buffer layer 141 of the PMOS device region A2, and an etching process is performed using the first patterned photoresist layer 151 as a mask to remove the first buffer layer 141 on the PMOS device region A2; then, removing the first patterned photoresist layer 151; then, a second buffer layer 142 is formed on the substrate 11, the gate structure 12 and the side wall 13 of the PMOS device region A2 and on the first buffer layer 141 of the NMOS device region A1, where the second buffer layer 142 on the PMOS device region A2 is used as the buffer layer 14 on the PMOS device region A2, and the first buffer layer 141 and the second buffer layer 142 on the NMOS device region A1 are used together as the buffer layer 14 on the NMOS device region A1, so that the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2.
And, before or after removing the first buffer layer 141 on the PMOS device region A2, the method of manufacturing a semiconductor device further includes: an ion implantation process is performed to form a second source region 118 and a second drain region 119 in the substrate 11 on a side of the sidewall 13 of the PMOS device region A2 away from the gate structure 12. The second source region 118 and the second drain region 119 are formed using the same patterned photoresist layer (i.e., the first patterned photoresist layer 151) as the mask for removing the first buffer layer 141 on the PMOS device region A2.
Alternatively, when the stress layer 16 is a compressive stress layer, in the step S2, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 includes: firstly, forming a buffer layer 14 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, wherein the buffer layer 14 covers the gate structure 12 and the side wall 13; then, a first patterned photoresist layer 151 is formed, the first patterned photoresist layer 151 covers the buffer layer 14 of the NMOS device region A1 and exposes the buffer layer 14 of the PMOS device region A2, and an etching process is performed with the first patterned photoresist layer 151 as a mask to remove a portion of the buffer layer 14 with a thickness on the PMOS device region A2, so that the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2; then, the first patterned photoresist layer 151 is removed.
And, before or after removing the buffer layer 14 of a partial thickness on the PMOS device region A2, the method of manufacturing a semiconductor device further includes: an ion implantation process is performed to form a second source region 118 and a second drain region 119 in the substrate 11 on a side of the sidewall 13 of the PMOS device region A2 away from the gate structure 12. Wherein the second source region 118 and the second drain region 119 are formed using the same patterned photoresist layer (i.e., the first patterned photoresist layer 151) as the mask for removing the buffer layer 14 having a partial thickness on the PMOS device region A2.
As can be seen from the above steps, when the stress layer 16 is a compressive stress layer, the steps of forming the second source region 118 and the second drain region 119 and removing the first buffer layer 141 on the PMOS device region A2 or removing a portion of the thickness of the buffer layer 14 on the PMOS device region A2 all use the first patterned photoresist layer 151 as a mask, i.e. use the same photomask, so that no additional photomask and photolithography steps are required, thereby reducing the cost of the stress memorization process.
In addition, when the material of the buffer layer 14 is silicon oxide, hydrofluoric acid may be used to etch away the first buffer layer 141 and a portion of the thickness of the buffer layer 14 on the PMOS device region A2.
After removing the first buffer layer 141 on the PMOS device region A2 and before forming the second buffer layer 142, or after removing a part of the thickness of the buffer layer 14 on the PMOS device region A2, the method of manufacturing a semiconductor device further includes: first, a second patterned photoresist layer 152 is formed, wherein the second patterned photoresist layer 152 covers the PMOS device region A2 and exposes the NMOS device region A1; then, an ion implantation process is performed with the second patterned photoresist layer 152 as a mask, so as to form a first source region 116 and a first drain region 117 in the substrate 11 on a side of the sidewall 13 of the NMOS device region A1, which is far away from the gate structure 12; the second patterned photoresist layer 152 is then removed.
It should be noted that, in this embodiment, the device schematic diagrams corresponding to the step S2 to the step S3 are not illustrated when the stress layer 16 is a compressive stress layer, and compared with the device schematic diagrams corresponding to the step S2 to the step S3 when the stress layer 16 is a tensile stress layer (i.e. fig. 2b to 2i and fig. 3a to 3 g), the device schematic diagrams corresponding to the stress layer 16 is a compressive stress layer and the main difference between the device schematic diagrams corresponding to the stress layer 16 and the device schematic diagrams is that the exposed areas of the first patterned photoresist layer 151 and the second patterned photoresist layer 152 are different, so that the buffer layer 14 on the NMOS device region A1 and the PMOS device region A2 can meet different requirements under different tensile stress or compressive stress.
The first source region 116 and the first drain region 117 may extend below the sidewall 13, the first source region 116 and the first drain region 117 are formed on top of the P-well 111, and bottom surfaces of the first source region 116 and the first drain region 117 are lower than bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115.
The second source region 118 and the second drain region 119 are formed on top of the N-well 112, the second source region 118 and the second drain region 119 may extend below the sidewall 13, and bottom surfaces of the second source region 118 and the second drain region 119 are lower than bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115.
In the NMOS device region A1, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the first source region 116 and the first drain region 117 are all N-type; in the PMOS device region A2, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the second source region 118 and the second drain region 119 are P-type.
Preferably, the thickness of the first buffer layer 141 is
Figure BDA0004103295910000121
Preferably, the thickness of the second buffer layer 142 is
Figure BDA0004103295910000122
Preferably, the material of the stress layer 16 includes silicon nitride, and the parameters in forming the stress layer 16 are adjusted to make the stress layer 16 have high tensile stress or high compressive stress.
The method of manufacturing a semiconductor device may further include: first, an annealing process is performed to introduce tensile stress in the stress layer 16 into the gate structure 12, the first source region 116, the first drain region 117, and the substrate 11 of the NMOS device region A1, or compressive stress in the stress layer 16 into the gate structure 12, the second source region 118, the second drain region 119, and the substrate 11 of the PMOS device region A2; the stress layer 16 is then removed.
In the method for manufacturing a semiconductor device according to the present invention, when the stress layer 16 is a tensile stress layer, since the buffer layer 14 is formed between the NMOS device region A1 and the PMOS device region A2 and the stress layer 16, and the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1, after the high-temperature annealing process is performed, more tensile stress in the stress layer 16 on the NMOS device region A1 can be smoothly transferred to the gate structure 12, the first source region 116, the first drain region 117 and the substrate 11 of the NMOS device region A1 after passing through the thinner buffer layer 14, and the tensile stress in the stress layer 16 on the PMOS device region A2 is more difficult to be transferred to the gate structure 12, the second source region 118, the second drain region 119 and the substrate 11 of the NMOS device region A2 through the thicker buffer layer 14, so that the tensile stress in the buffer layer 16 on the PMOS device region A1 is not required to be increased, and the tensile stress in the buffer layer 16 is not required to be further increased, and the tensile stress in the buffer layer 16 A1 can be prevented from being transferred to the buffer layer 1. Therefore, the electron mobility of the NMOS device is further improved, and the hole mobility of the PMOS device is prevented from being reduced, so that the performance of the NMOS device is improved, and the performance of the PMOS device is prevented from being reduced.
When the stress layer 16 is a compressive stress layer, since the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2, after the high-temperature annealing process is performed, more compressive stress in the stress layer 16 on the PMOS device region A2 can be smoothly transferred into the gate structure 12, the second source region 118, the second drain region 119 and the substrate 11 of the PMOS device region A2 through the thinner buffer layer 14, and the compressive stress in the stress layer 16 on the NMOS device region A1 is more difficult to be transferred into the gate structure 12, the first source region 116, the first drain region 117 and the substrate 11 through the thicker buffer layer 14, so that the thickness of the stress layer 16 is not increased, and the compressive stress in the PMOS device region A2 is not increased, and the stress layer 16 is also prevented from being influenced by the thickness of the NMOS device region A1, so that the stress layer 14 on the NMOS device region A1 is prevented from being influenced by the thickness of the buffer layer 16, and the stress layer 14 on the PMOS device region A1 is prevented from being influenced. Therefore, the electron mobility of the NMOS device can be prevented from being reduced while the hole mobility of the PMOS device is further improved, and the performance of the NMOS device can be prevented from being reduced while the performance of the PMOS device is improved.
Moreover, when the stress layer 16 is a tensile stress layer, since the buffer layer 14 on the PMOS device region A2 has a sufficient blocking effect on tensile stress, no additional photolithography and etching steps are required to be introduced to remove the stress layer 16 on the PMOS device region A2 after forming the stress layer 16 and before performing the annealing process, thereby avoiding increasing the chip manufacturing cost; when the stress layer 16 is a compressive stress layer, the buffer layer 14 on the NMOS device region A1 has a sufficient blocking effect on compressive stress, so that no additional photolithography and etching steps need to be introduced to remove the stress layer 16 on the NMOS device region A1 after forming the stress layer 16 and before performing the annealing process, thereby avoiding an increase in chip manufacturing cost.
In addition, since the material of the stress layer 16 (for example, silicon nitride) and the material of the buffer layer 14 (for example, silicon oxide) are not matched with the lattice constants of the materials of the gate structure 12 and the substrate 11 (for example, polysilicon and monocrystalline silicon, respectively), the lattice spacing difference is large, if the thickness of the stress layer 16 is increased so that more tensile stress is transferred to the NMOS device region A1 or more compressive stress is transferred to the PMOS device region A2, damage to the gate structure 12 and the substrate 11 is more easily caused, and further, leakage current of the device is more easily caused, and even the device cannot work. Therefore, the present invention does not allow more tensile stress to be transferred into the NMOS device region A1 or more compressive stress to be transferred into the PMOS device region A2 by increasing the thickness of the stress layer 16, so that excessive leakage current resulting in the device can be avoided.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region; forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure; forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region. The manufacturing method of the semiconductor device provided by the invention can improve the performance of one of the NMOS device and the PMOS device, avoid reducing the performance of the other device, and simultaneously avoid increasing the manufacturing cost of the chip.
An embodiment of the present invention provides a semiconductor device including: the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region; the buffer layer is formed on the substrates of the NMOS device region and the PMOS device region and covers the grid structure; a stress layer formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region.
The semiconductor device provided in this embodiment is described in detail below with reference to fig. 2i and 3 g.
The substrate 11 includes an NMOS device region A1 and a PMOS device region A2, a gate structure 12 and a sidewall 13 are formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the sidewall 13 is formed on a sidewall of the gate structure 12.
The gate structure 12 includes a bottom-up gate oxide layer and a gate layer.
A trench isolation structure 113 may be formed in the substrate 11 between the NMOS device region A1 and the PMOS device region A2 to achieve mutual isolation between the NMOS device region A1 and the PMOS device region A2. The top surface of the trench isolation structure 113 is flush with the top surface of the substrate 11 or slightly higher than the top surface of the substrate 11.
A P-well 111 is formed in the substrate 11 of the NMOS device region A1, an N-well 112 is formed in the substrate 11 of the PMOS device region A2, and bottom surfaces of the P-well 111 and the N-well 112 may be lower than bottom surfaces of the trench isolation structures 113.
In addition, a lightly doped source region 114 and a lightly doped drain region 115 are formed on top of the P-well 111 at both sides of the gate structure 12 in the NMOS device region A1; a lightly doped source region 114 and a lightly doped drain region 115 are also formed on top of the N-well 112 on both sides of the gate structure 12 in the PMOS device region A2. And, in the NMOS device region A1 and the PMOS device region A2, the lightly doped source region 114 and the lightly doped drain region 115 each extend below the gate structure 12.
The semiconductor device further includes:
a first source region 116 and a first drain region 117 formed in the substrate 11 on a side of the sidewall 13 of the NMOS device region A1 away from the gate structure 12, where the first source region 116 and the first drain region 117 may extend below the sidewall 13;
a second source region 118 and a second drain region 119 are formed in the substrate 11 on a side of the sidewall 13 of the PMOS device region A2 remote from the gate structure 12, and the second source region 118 and the second drain region 119 may extend below the sidewall 13.
Wherein the first source region 116 and the first drain region 117 are formed on top of the P-well 111, and the bottom surfaces of the first source region 116 and the first drain region 117 are lower than the bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115; the second source region 118 and the second drain region 119 are formed on top of the N-well 112, and the bottom surfaces of the second source region 118 and the second drain region 119 are lower than the bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115.
In the NMOS device region A1, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the first source region 116 and the first drain region 117 are all N-type; in the PMOS device region A2, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the second source region 118 and the second drain region 119 are P-type.
The buffer layer 14 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the buffer layer 14 covers the gate structure 12 and the sidewall 13. Wherein the buffer layer 14 serves to buffer and protect the device while also serving as a barrier.
Preferably, the material of the buffer layer 14 includes silicon oxide. The material of the buffer layer 14 may also include silicon oxides such as silicon oxynitride, fluorinated silicon glass, phosphosilicate glass, and borophosphosilicate glass.
The stress layer 16 is formed on the buffer layer 14.
When the stress layer 16 is a tensile stress layer, the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1; when the stress layer 16 is a compressive stress layer, the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2.
When the stress layer 16 is a tensile stress layer, in the embodiment shown in fig. 2i, the buffer layer 14 on the PMOS device region A2 includes a first buffer layer 141 and a second buffer layer 142, and the buffer layer 14 on the NMOS device region A1 includes only the second buffer layer 142, so that the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1; in the embodiment shown in fig. 3g, a portion of the thickness of buffer layer 14 over NMOS device region A1 is removed such that the thickness of buffer layer 14 over PMOS device region A2 is greater than the thickness of buffer layer 14 over NMOS device region A1.
When the stress layer 16 is a compressive stress layer, the buffer layer 14 on the NMOS device region A1 includes a first buffer layer 141 and a second buffer layer 142, and the buffer layer 14 on the PMOS device region A2 includes only the second buffer layer 142, such that the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2; alternatively, a portion of the thickness of buffer layer 14 over PMOS device region A2 is removed such that the thickness of buffer layer 14 over NMOS device region A1 is greater than the thickness of buffer layer 14 over PMOS device region A2.
Preferably, the thickness of the first buffer layer 141 is
Figure BDA0004103295910000171
Preferably, the thickness of the second buffer layer 142 is
Figure BDA0004103295910000172
Preferably, the material of the stress layer 16 includes silicon nitride, and the parameters in forming the stress layer 16 are adjusted to make the stress layer 16 have high tensile stress or high compressive stress.
Note that the stress layer 16 is a stress layer after the annealing process is performed, so that tensile stress in the stress layer 16 can be introduced into the gate structure 12, the first source region 116, the first drain region 117, and the substrate 11 of the NMOS device region A1, or compressive stress in the stress layer 16 can be introduced into the gate structure 12, the second source region 118, the second drain region 119, and the substrate 11 of the PMOS device region A2; and, after performing the annealing process, the stress layer 16 may be removed. In the semiconductor device of the present invention, when the stress layer 16 is a tensile stress layer, since the buffer layer 14 is formed between the NMOS device region A1 and the PMOS device region A2 and the stress layer 16, and the thickness of the buffer layer 14 on the PMOS device region A2 is greater than that of the buffer layer 14 on the NMOS device region A1, after the high-temperature annealing process is performed, more tensile stress in the stress layer 16 on the NMOS device region A1 can be smoothly transferred to the gate structure 12, the first source region 116, the first drain region 117 and the substrate 11 of the NMOS device region A1 after passing through the thinner buffer layer 14, and the tensile stress in the stress layer 16 on the PMOS device region A2 is more difficult to be transferred to the gate structure 12, the second source region 118, the second drain region 119 and the substrate 11 of the PMOS device region A2 through the thicker buffer layer 14, so that the tensile stress in the buffer layer 16 can be prevented from being transferred to the buffer layer 1, and the thickness of the buffer layer 16 in the PMOS device region A2 is not increased, and the tensile stress layer 16 in the PMOS device region A1 is prevented from being affected. Therefore, the electron mobility of the NMOS device is further improved, and the hole mobility of the PMOS device is prevented from being reduced, so that the performance of the NMOS device is improved, and the performance of the PMOS device is prevented from being reduced.
When the stress layer 16 is a compressive stress layer, since the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2, after the high-temperature annealing process is performed, more compressive stress in the stress layer 16 on the PMOS device region A2 can be smoothly transferred into the gate structure 12, the second source region 118, the second drain region 119 and the substrate 11 of the PMOS device region A2 through the thinner buffer layer 14, and the compressive stress in the stress layer 16 on the NMOS device region A1 is more difficult to be transferred into the gate structure 12, the first source region 116, the first drain region 117 and the substrate 11 through the thicker buffer layer 14, so that the thickness of the stress layer 16 is not increased, and the compressive stress in the PMOS device region A2 is not increased, and the stress layer 16 is also prevented from being influenced by the thickness of the NMOS device region A1, so that the stress layer 14 on the NMOS device region A1 is prevented from being influenced by the thickness of the buffer layer 16, and the stress layer 14 on the PMOS device region A1 is prevented from being influenced. Therefore, the electron mobility of the NMOS device can be prevented from being reduced while the hole mobility of the PMOS device is further improved, and the performance of the NMOS device can be prevented from being reduced while the performance of the PMOS device is improved.
Moreover, when the stress layer 16 is a tensile stress layer, since the buffer layer 14 on the PMOS device region A2 has a sufficient blocking effect on tensile stress, the stress layers 16 on the NMOS device region A1 and the PMOS device region A2 are both retained, which means that no additional photolithography and etching steps need to be introduced to remove the stress layer 16 on the PMOS device region A2 before the annealing process is performed, thereby avoiding an increase in chip manufacturing cost; when the stress layer 16 is a compressive stress layer, since the buffer layer 14 on the NMOS device region A1 has a sufficient blocking effect on compressive stress, the stress layer 16 on both the NMOS device region A1 and the PMOS device region A2 is preserved, which means that no additional photolithography and etching steps need to be introduced to remove the stress layer 16 on the NMOS device region A1 before the annealing process is performed, thereby avoiding an increase in chip manufacturing cost.
In addition, since the material of the stress layer 16 (for example, silicon nitride) and the material of the buffer layer 14 (for example, silicon oxide) are not matched with the lattice constants of the materials of the gate structure 12 and the substrate 11 (for example, polysilicon and monocrystalline silicon, respectively), the lattice spacing difference is large, if the thickness of the stress layer 16 is increased so that more tensile stress is transferred to the NMOS device region A1 or more compressive stress is transferred to the PMOS device region A2, damage to the gate structure 12 and the substrate 11 is more easily caused, and further, leakage current of the device is more easily caused, and even the device cannot work. Therefore, the present invention does not allow more tensile stress to be transferred into the NMOS device region A1 or more compressive stress to be transferred into the PMOS device region A2 by increasing the thickness of the stress layer 16, so that excessive leakage current resulting in the device can be avoided.
In summary, the present invention provides a semiconductor device, including: the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region; the buffer layer is formed on the substrates of the NMOS device region and the PMOS device region and covers the grid structure; a stress layer formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region. The semiconductor device provided by the invention can improve the performance of one of the NMOS device and the PMOS device, avoid reducing the performance of the other device, and simultaneously avoid increasing the manufacturing cost of the chip.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (13)

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region;
forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;
forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein when the stress layer is a tensile stress layer, the method for manufacturing a semiconductor device further comprises, before forming the stress layer on the buffer layer:
forming a first source region and a first drain region in the substrate at two sides of the gate structure of the NMOS device region, wherein the first source region and the first drain region are formed by using the same patterned photoresist layer as a mask;
When the stress layer is a compressive stress layer, the method for manufacturing the semiconductor device further includes, before forming the stress layer on the buffer layer:
and forming a second source region and a second drain region in the substrate at two sides of the gate structure of the PMOS device region, wherein the second source region and the second drain region are formed by using the same patterned photoresist layer as a mask for forming the buffer layer.
3. The method for manufacturing a semiconductor device according to claim 1, wherein when the stress layer is a tensile stress layer;
the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises the following steps:
forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure;
removing the first buffer layer on the NMOS device region;
forming a second buffer layer on the substrate and the gate structure of the NMOS device region and on the first buffer layer of the PMOS device region;
alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:
forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;
And removing part of the buffer layer with the thickness on the NMOS device region.
4. The method of manufacturing a semiconductor device of claim 3, wherein the method of manufacturing a semiconductor device further comprises, before or after removing the first buffer layer on the NMOS device region, or before or after removing a portion of the thickness of the buffer layer on the NMOS device region:
and forming a first source region and a first drain region in the substrate at two sides of the grid structure of the NMOS device region, wherein the same patterned photoresist layer is used as a mask for forming the first source region and the first drain region and removing a first buffer layer on the NMOS device region or removing part of the buffer layer with the thickness on the NMOS device region.
5. The method of manufacturing a semiconductor device according to claim 3, wherein after removing the first buffer layer over the NMOS device region or after removing a portion of the thickness of the buffer layer over the NMOS device region, the method of manufacturing a semiconductor device further comprises:
and forming a second source electrode region and a second drain electrode region in the substrate at two sides of the grid structure of the PMOS device region.
6. The method for manufacturing a semiconductor device according to claim 1, wherein when the stress layer is a compressive stress layer;
the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises the following steps:
forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure;
removing the first buffer layer on the PMOS device region;
forming a second buffer layer on the substrate and the gate structure of the PMOS device region and the first buffer layer of the NMOS device region;
alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:
forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, wherein the buffer layer covers the grid structure;
and removing part of the buffer layer with the thickness on the PMOS device region.
7. The method of manufacturing a semiconductor device according to claim 6, wherein before or after removing the first buffer layer on the PMOS device region, or before or after removing a portion of the thickness of the buffer layer on the PMOS device region, the method of manufacturing a semiconductor device further comprises:
And forming a second source region and a second drain region in the substrate at two sides of the grid structure of the PMOS device region, wherein the same patterned photoresist layer is used as a mask for forming the second source region and the second drain region and removing the first buffer layer on the PMOS device region or removing part of the buffer layer with the thickness on the PMOS device region.
8. The method of manufacturing a semiconductor device according to claim 6, wherein after removing the first buffer layer over the PMOS device region or after removing a portion of the thickness of the buffer layer over the PMOS device region, the method of manufacturing a semiconductor device further comprises:
and forming a first source electrode region and a first drain electrode region in the substrate at two sides of the grid structure of the NMOS device region.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the method for manufacturing a semiconductor device further comprises:
performing an annealing process;
and removing the stress layer.
10. A semiconductor device, comprising:
the substrate comprises an NMOS device region and a PMOS device region, and grid structures are formed on the substrates of the NMOS device region and the PMOS device region;
The buffer layer is formed on the substrates of the NMOS device region and the PMOS device region and covers the grid structure;
a stress layer formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is larger than that of the buffer layer on the NMOS device region; and when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is larger than that of the buffer layer on the PMOS device region.
11. The semiconductor device of claim 10, wherein a material of the stress layer comprises silicon nitride and a material of the buffer layer comprises silicon oxide.
12. The semiconductor device according to claim 10, wherein the semiconductor device further comprises:
the first source electrode region and the first drain electrode region are formed in the substrate at two sides of the grid structure of the NMOS device region;
and the second source electrode region and the second drain electrode region are formed in the substrate at two sides of the grid structure of the PMOS device region.
13. The semiconductor device of claim 12, wherein a P-well is formed in a substrate of the NMOS device region, the first source region and the first drain region being formed on top of the P-well; an N-well is formed in the substrate of the PMOS device region, and the second source region and the second drain region are formed on top of the N-well.
CN202310174180.4A 2023-02-27 2023-02-27 Semiconductor device and method for manufacturing the same Pending CN116314032A (en)

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