CN116314017A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN116314017A CN116314017A CN202310558023.3A CN202310558023A CN116314017A CN 116314017 A CN116314017 A CN 116314017A CN 202310558023 A CN202310558023 A CN 202310558023A CN 116314017 A CN116314017 A CN 116314017A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 80
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 41
- 239000001301 oxygen Substances 0.000 claims abstract description 41
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 41
- 150000002500 ions Chemical class 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims description 351
- 239000011241 protective layer Substances 0.000 claims description 30
- 229910001449 indium ion Inorganic materials 0.000 claims description 22
- 239000002019 doping agent Substances 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 16
- -1 hydrogen ions Chemical class 0.000 claims description 13
- 239000002245 particle Substances 0.000 claims description 9
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 5
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 description 28
- 238000010586 diagram Methods 0.000 description 15
- 239000010409 thin film Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 125000004430 oxygen atom Chemical group O* 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- Geometry (AREA)
- Thin Film Transistor (AREA)
Abstract
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a method for manufacturing the same, the semiconductor structure including: a substrate; the first IGZO layer is positioned on the substrate and comprises a channel region and source-drain doped regions positioned on two opposite sides of the channel region; the second IGZO layer is at least positioned on the channel region, doped ions are arranged in the second IGZO layer, and the number of oxygen vacancies in the second IGZO layer is smaller than that in the first IGZO layer; and the first grid electrode is positioned on the surface of the second IGZO layer away from the substrate. At least carrier mobility in the semiconductor structure may be improved.
Description
Technical Field
Embodiments of the present disclosure relate to the field of semiconductors, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
Thin film transistors (TFTs, thin Film Transistor) are widely used in the display field as core devices for active matrix drive flat panel display technology. Currently, in flat panel display technology, silicon-based thin film transistors are a relatively mature industrialized technology, and mainly include amorphous silicon and polysilicon thin film transistors. As flat panel display technology has evolved toward large area, high resolution, flexible, and rollable, and many new flat panel display technologies have emerged, there is a greater demand for performance of thin film transistors.
IGZO is an amorphous oxide containing indium, gallium, and zinc, and has higher electron mobility than amorphous silicon. The application of the IGZO to the channel material of the new generation of thin film transistors can greatly improve the charge and discharge rate of the thin film transistors to the pixel electrode, improve the corresponding speed of the pixels and realize faster refresh rate. The semiconductor structure has higher energy efficiency level and higher efficiency.
However, there are some problems with such semiconductor structures.
Disclosure of Invention
Embodiments of the present disclosure provide a semiconductor structure and a method of fabricating the same, which are at least beneficial for improving carrier mobility in the semiconductor structure.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a semiconductor structure, including: a substrate; the first IGZO layer is positioned on the substrate and comprises a channel region and source-drain doping regions positioned on two opposite sides of the channel region; a second IGZO layer, the second IGZO layer being located at least on the channel region and having doping ions therein, the number of oxygen vacancies in the second IGZO layer being smaller than the number of oxygen vacancies in the first IGZO layer; and a first gate electrode on a surface of the second IGZO layer remote from the substrate.
In some embodiments, the dopant particles of the dopant ions in the second IGZO layer are nitrogen-containing particles.
In some embodiments, the indium ion concentration in the first IGZO layer is greater than the indium ion concentration in the second IGZO layer.
In some embodiments, the second IGZO layer is further located on opposite sides of the channel region, and the source-drain doped region is further located within the second IGZO layer.
In some embodiments, further comprising: and the second grid electrode is positioned in the substrate, is positioned on one side of the first IGZO layer far away from the second IGZO layer, and is opposite to the channel region.
In some embodiments, further comprising: and a third IGZO layer, the third IGZO layer being at least between the channel region and the second gate electrode, and having the dopant ions therein, the number of oxygen vacancies in the third IGZO layer being smaller than the number of oxygen vacancies in the first IGZO layer.
In some embodiments, the third IGZO layer is also located on opposite sides of the channel region, and the source drain doped region is also located within the third IGZO layer.
In some embodiments, further comprising: the doped region is doped with hydrogen ions, is at least positioned in the first IGZO layer, and is positioned between the source drain doped region and the channel region.
In some embodiments, further comprising: and the protective layer is positioned on one side surface of the first IGZO layer close to the substrate, and at least contacts with the doped region.
In some embodiments, the second IGZO layer is located only on the channel region.
In some embodiments, further comprising: and the side wall structure is positioned on one side surface of the first IGZO layer away from the substrate, and covers the side surface of the first grid electrode and the side surface of the second IGZO layer.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming a first IGZO layer on the substrate, the first IGZO layer including a channel region; forming a second IGZO layer, wherein the second IGZO layer is at least positioned on the channel region, doped ions are arranged in the second IGZO layer, and the number of oxygen vacancies in the second IGZO layer is smaller than that in the first IGZO layer; forming a first gate electrode on a portion of the surface of the second IGZO layer remote from the substrate; and forming source-drain doped regions, wherein the source-drain doped regions are at least positioned on two opposite sides of the channel region.
In some embodiments, the method of forming the second IGZO layer is an in situ doping method.
In some embodiments, the second IGZO layer is formed at a gas flow rate of 15sccm-30sccm of the gas providing the dopant ions.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
the embodiment of the disclosure provides a semiconductor structure, which comprises: a substrate; the first IGZO layer is positioned on the substrate and comprises a channel region and source-drain doped regions positioned on two opposite sides of the channel region; the second IGZO layer is at least positioned on the channel region, doped ions are arranged in the second IGZO layer, and the number of oxygen vacancies in the second IGZO layer is smaller than that in the first IGZO layer; the first gate electrode is located on a surface of the second IGZO layer remote from the substrate. In the related art, since there is only one IGZO layer in the semiconductor structure and the IGZO layer is adjacent to the gate electrode, electrons in the IGZO layer may have a certain loss, thereby causing a decrease in electron mobility in the IGZO layer. The related art solves this problem by fabricating two IGZO layers having different oxygen contents. The higher oxygen content IGZO layer is adjacent to the gate electrode and is located between the lower oxygen content IGZO layer and the gate electrode. At the moment, the IGZO layer with higher oxygen content can play a certain barrier role between the IGZO layer with lower oxygen content and the grid electrode, so that the electron loss in the IGZO layer with lower oxygen content is reduced, and the carrier mobility is improved. However, the blocking effect of such IGZO layers with higher oxygen content is limited, and the carrier mobility of the semiconductor structure still needs to be improved. In the semiconductor structure provided by the embodiment of the disclosure, the second IGZO layer is disposed between the first gate and the first IGZO layer. The second IGZO layer is doped with doping ions, and the doping ions occupy part of oxygen vacancies in the second IGZO layer, so that the number of the oxygen vacancies in the second IGZO layer is smaller than that of the oxygen vacancies in the first IGZO layer, interface state density of the second IGZO layer is reduced, and the second IGZO layer has higher stability. The second IGZO layer can play a better barrier effect between the first IGZO layer and the first grid electrode, effectively reduce the situation of electron loss in the first IGZO layer, improve the carrier concentration in the first IGZO layer, improve the carrier mobility of the semiconductor structure, and optimize the performance of the semiconductor structure.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a first semiconductor structure according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a second semiconductor structure according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a third semiconductor structure according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a fourth semiconductor structure according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a fifth semiconductor structure according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a sixth semiconductor structure according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a seventh semiconductor structure according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an eighth semiconductor structure according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram corresponding to a step of providing a substrate in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;
fig. 10 is a schematic structural diagram corresponding to a step of forming a second gate, a protective layer, and a second gate oxide layer in a method for manufacturing a semiconductor structure according to another embodiment of the disclosure;
fig. 11 is a schematic diagram of another structure corresponding to a step of forming a second gate, a protective layer, and a second gate oxide layer in a method for manufacturing a semiconductor structure according to another embodiment of the disclosure;
fig. 12 is a schematic structural diagram corresponding to steps of forming a third IGZO layer, a first IGZO layer, and a second IGZO layer in a method for manufacturing a semiconductor structure according to another embodiment of the disclosure;
fig. 13 is a schematic structural diagram corresponding to a step of forming a first gate in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;
fig. 14 is a schematic structural diagram corresponding to a step of forming a sidewall structure and a doped region in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;
fig. 15 is a schematic structural diagram corresponding to a step of forming a source-drain doped region in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.
Detailed Description
As known from the background art, the current semiconductor structure has the problem of low carrier mobility.
Embodiments of the present disclosure provide a semiconductor structure including a substrate; the first IGZO layer is positioned on the substrate and comprises a channel region and source-drain doped regions positioned on two opposite sides of the channel region; the second IGZO layer is at least positioned on the channel region, doped ions are arranged in the second IGZO layer, and the number of oxygen vacancies in the second IGZO layer is smaller than that in the first IGZO layer; the first gate electrode is located on a surface of the second IGZO layer remote from the substrate. The second IGZO layer can better isolate the first IGZO layer from the first grid electrode, so that electron loss in the first IGZO layer can be effectively reduced, and carrier mobility in the semiconductor structure can be improved.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Referring to fig. 1, a semiconductor structure includes: a substrate 100; the first IGZO layer 110, the first IGZO layer 110 being located on the substrate 100, the first IGZO layer 110 including a channel region 111 and source-drain doped regions 112 located at opposite sides of the channel region 111; a second IGZO layer 120, the second IGZO layer 120 being at least on the channel region 111, the second IGZO layer 120 having dopant ions therein, the number of oxygen vacancies in the second IGZO layer 120 being less than the number of oxygen vacancies in the first IGZO layer 110; the first gate electrode 130, the first gate electrode 130 is located on a surface of the second IGZO layer 120 remote from the substrate 100.
In some embodiments, the material of the substrate 100 may include single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may also be a glass substrate or other material such as a III-V compound such as gallium arsenide. In the disclosed embodiment, the material of the base 100 may be in single crystal silicon (Si) or a glass substrate.
The first IGZO layer 110 and the second IGZO layer 120 each contain indium, gallium and zinc, and IGZO is a novel semiconductor material. The use of IGZO material in the first IGZO layer 110 in the semiconductor structure as a channel of the semiconductor structure may improve the performance of the semiconductor structure. Compared with a channel made of amorphous silicon, the carrier mobility of the channel layer made of the IGZO material is 20-30 times that of the channel layer made of the amorphous silicon material, and the charge and discharge rate of the semiconductor structure can be improved by the IGZO layer, so that the energy efficiency of the semiconductor structure is improved.
In some embodiments, the indium ion concentration in the first IGZO layer 110 may be greater than the indium ion concentration in the second IGZO layer 120. Wherein the concentration of indium ions refers to the percentage of the number of indium ions in the film layer to the total number of atoms in the film layer. The concentration of indium ions in the second IGZO layer 120 is the concentration of indium ions in the general IGZO material. The concentration of indium ions in the first IGZO layer 110 is greater than the concentration of indium ions in the second IGZO layer 120, i.e., the concentration of indium ions in the first IGZO layer 110 is greater than the concentration of indium ions in the conventional IGZO material. The higher indium ion concentration may enable the first IGZO layer 110 to have higher conductive properties relative to a general IGZO material. In the semiconductor structure provided in the embodiments of the present disclosure, the first IGZO layer 110 has a channel region, and setting the first IGZO layer 110 to have a higher indium ion concentration may make the conductivity of the first IGZO layer 110 better, so that the conductivity of the channel region of the semiconductor structure is better, and the conductivity of the semiconductor structure can be improved.
In some embodiments, the concentration of indium ions in the first IGZO layer 110 may be 5% -15%. For example, the concentration of indium ions may be 5%, 10%, 15%, or the like. If the concentration of indium ions in the first IGZO layer 110 is too low, it may be difficult to better improve the conductivity of the first IGZO layer 110; if the concentration of indium ions in the first IGZO layer 110 is too high, the manufacturing cost of the semiconductor structure is increased, resulting in some waste. Therefore, the concentration of the indium ions in the first IGZO layer 110 needs to be in a proper range, and when the concentration of the indium ions in the first IGZO layer 110 is 5-15%, the effect of better improving the conductivity of the first IGZO layer 110 can be achieved, waste can be reduced, and cost can be reduced.
The source/drain doped region 112 is doped, wherein if N-type doping is required, N-type ions, such as nitrogen ions, phosphorus ions, etc., may be implanted. If P-type doping is required, P-type ions, such as boron ions, aluminum ions, etc., may be implanted.
In some embodiments, the doping particles of the doping ions in the second IGZO layer 120 may be nitrogen-containing particles. The nitrogen-containing particles may occupy a portion of oxygen vacancies in the second IGZO layer 120, so that the oxygen vacancies in the second IGZO layer 120 are reduced, the interface state density of the second IGZO layer 120 is reduced, and the stability of the second IGZO layer 120 can be improved. The second IGZO layer 120 with higher stability is located between the first IGZO layer 110 and the first gate 130, which can play a better role in blocking, effectively reduce the electron loss in the first IGZO layer 110, and improve the carrier concentration in the first IGZO layer 110, thereby improving the carrier mobility in the first IGZO layer 110.
In some embodiments, the material of the first gate 130 may include one or more of polysilicon or tungsten.
With continued reference to fig. 1, in some embodiments, the second IGZO layer 120 may be located only on the channel region 111. The second IGZO layer 120 may function to isolate the first IGZO layer 110 from the first gate electrode 130 when it is only on the channel region. In addition, at this time, the source-drain doped regions 112 are only located at two sides of the channel region 111 in the first IGZO layer 110, where the channel region 111 in the first IGZO layer 110 is a region with a higher carrier concentration, a higher carrier mobility and a better conductivity, and if the source-drain doped regions 112 are only in contact with the channel region 111 in the first IGZO layer 110, the mobility of the semiconductor structure can be further improved, and the interference to the channel region 111 in the first IGZO layer 110 can be reduced.
Referring to fig. 2, in some embodiments, if the second IGZO layer 120 is only located on the channel region 111, the semiconductor structure may further include: and a sidewall structure 140, the sidewall structure 140 being on a side surface of the first IGZO layer 110 remote from the substrate 100, and the sidewall structure 140 covering a side surface of the first gate electrode 130 and a side surface of the second IGZO layer 120. When the second IGZO layer 120 is only on the channel region 111, the second IGZO layer 120 may be flush with sidewalls of the first gate electrode 130. The sidewall structure 140 may protect the first gate 130 and the second IGZO layer 120, and the material of the sidewall structure 140 may include silicon oxide or silicon nitride. The sidewall structure 140 may include one or more sidewalls. If the sidewall structure 140 includes a multi-layer sidewall, the sidewall structure 140 may include a first sidewall and a second sidewall, the first sidewall covers a side surface of the first gate 130 and a side surface of the second IGZO layer 120, and the second sidewall covers a side surface of the first gate, where a material of the first sidewall may include silicon oxide, and a material of the second sidewall may include silicon nitride.
Referring to fig. 3, in some embodiments, the second IGZO layer 120 may also be located at opposite sides of the channel region 111, and the source-drain doped region 112 may also be located within the second IGZO layer 120. The second IGZO layer 120 covers the entire area of the surface of the first IGZO layer 110 remote from the substrate 100. The sidewall 140 is located on the surface of the second IGZO layer 120 away from the substrate 100, and the sidewall 140 covers only the surface of the first gate 130. The second IGZO layer 120 is also located at opposite sides of the channel region 111 to reduce the process steps of patterning the second IGZO layer 120, thereby enabling the process flow to be simplified.
Referring to fig. 4, in some embodiments, the semiconductor structure may further include a first gate oxide layer 131. The first gate oxide layer 131 is located between the first gate electrode 130 and the second IGZO layer 120. The material of the first gate oxide layer 131 may include silicon oxide, aluminum oxide, or the like. The arrangement of the first gate oxide layer 131 can improve the electron conduction performance of the semiconductor structure, so that electrons can be conducted in the semiconductor structure more smoothly, the first gate oxide layer 131 can also control current, prevent overheat or short circuit of a device caused by overlarge current, form a charge channel, be used for controlling the flow of electrons in the device, improve the stability of the device, improve the efficiency of the device, and protect the device from environmental factors to a certain extent. In addition, the first gate oxide layer 131 has a certain surface activity, and can be used as a surface active layer in the semiconductor structure to receive or place other substances. The sidewall structure 140 is located on a surface of the second IGZO layer 120 remote from the substrate 100, and the sidewall structure 140 covers a side of the first gate oxide layer 131 and a side of the first gate electrode 130.
Referring to fig. 5, in some embodiments, the semiconductor structure may further include: the second gate 150, the second gate 150 is located in the substrate 100, on a side of the first IGZO layer 110 away from the second IGZO layer 120, and opposite to the channel region 111. The second gate 150 shares the channel region 111 and the source-drain doped region 112 in the first IGZO layer 110 and the second IGZO layer 120 with the first gate 130, and the use of two gates in the semiconductor structure can improve the power, reduce the resistance, reduce the on-resistance, improve the thermal stability, and improve the performance of the semiconductor structure from various aspects. The material of the second gate 150 may include one or more of polysilicon or tungsten.
Referring to fig. 5 to 6, in some embodiments, the semiconductor structure may further include a second gate oxide layer 151, the second gate oxide layer 151 being located at least between the first IGZO layer 110 and the second gate 150. The material of the second gate oxide layer 151 may include silicon oxide, aluminum oxide, or the like.
In some embodiments, the semiconductor structure may further include a protection layer 170, where the protection layer 170 is located on a surface of the first IGZO layer 110 near the substrate 100, the protection layer 170 covers at least a side surface of the second gate 150, and the protection layer 170 can protect the second gate 150. The material of the protective layer 170 may include silicon nitride.
Referring to fig. 5, in some embodiments, the second gate oxide layer 151 may cover a surface of the first IGZO layer 110 remote from the second IGZO layer 120, and the protective layer 170 is on a surface of the second gate oxide layer 151 close to the substrate 100. Since the second gate 150 cannot make contact with the substrate 100, an insulating process is required, and in some embodiments, the semiconductor structure may further include an insulating layer 160, where the insulating layer 160 is located on a surface of the substrate 100, and the second gate 150 and the protective layer 170 are located on a surface of the insulating layer 160 away from the substrate 100. The thickness of the protective layer 170 may be greater than or equal to the thickness of the second gate electrode 150, and the second gate oxide layer 151 is located on a surface of the protective layer 170 remote from the substrate 100. The material of the insulating layer 160 may include silicon oxide.
Referring to fig. 6, in some embodiments, the second gate oxide 151 may further surround the second gate 150, the protective layer 170 is located on the surface of the substrate 100, and the protective layer 170 covers the sides of the second gate oxide 151. The first IGZO layer 110 is located on the surface of the second gate oxide layer 151 and the protective layer 170 remote from the substrate 100. Since the second gate oxide layer 151 between the second gate electrode 150 and the substrate 100 may already serve to insulate the second gate electrode 150 from the substrate 100, the insulating layer 160 does not need to be added.
In some embodiments, the semiconductor structure may further include: the doped region 113, the doped region 113 is doped with hydrogen ions, the doped region 113 is at least located in the first IGZO layer 110, and the doped region 113 is located between the source-drain doped region 112 and the channel region 111. If the second IGZO layer 120 is also located at opposite sides of the channel region 111, the doped region 113 may also be located within the second IGZO layer 120. The H ions in the doped region 113 occupy the original oxygen atoms in the first IGZO layer 110, so that oxygen atoms overflow from the first IGZO layer 110 to form oxygen vacancies, and the number of oxygen vacancies in the first IGZO layer 110 increases. The oxygen vacancies may act as transport orbitals for carriers when the semiconductor structure is in operation, and an increase in the number of oxygen vacancies may result in an increase in carrier mobility in the first IGZO layer 110. That is, the doped region 113 can further improve carrier mobility in the semiconductor structure.
With continued reference to fig. 6, in some embodiments, the protection layer 170 is located on the surface of the substrate 100, and the protection layer 170 covers the side surface of the second gate oxide layer 151, where at least the surface of the protection layer 170 away from the substrate 100 may be in contact with the doped region 113, and where the surface of the protection layer 170 away from the substrate 100 may also be in contact with the source-drain doped region 112 and part of the channel region 111. The material of the protective layer 170 may be silicon nitride. Since the material of the protective layer 170 does not contain oxygen, when the hydrogen ions doped in the doped region 113 occupy the original oxygen atoms in the first IGZO layer 110, the oxygen atoms in the first IGZO layer 110 can diffuse into the protective layer 170 more easily, and more oxygen vacancies can be generated in the first IGZO layer 110, so that the effect of improving the carrier mobility of the semiconductor structure in the doped region 113 can be enhanced.
Referring to fig. 7-8, in some embodiments, the semiconductor structure may further include: and a third IGZO layer 180, the third IGZO layer 180 being located at least between the channel region 111 and the second gate electrode 150, and the third IGZO layer 180 having doping ions therein, the number of oxygen vacancies in the third IGZO layer 180 being smaller than the number of oxygen vacancies in the first IGZO layer 110. Because the distance between the first IGZO layer 110 and the second gate 150 is relatively short, electrons in the first IGZO layer 110 may have a certain loss, and the third IGZO layer 180 is located between the first IGZO layer 110 and the second gate 150, so that the effect of blocking the first IGZO layer 110 and the second gate 150 can be achieved, the electron loss in the first IGZO layer 110 is reduced, the carrier concentration in the first IGZO layer 110 is improved, and the carrier mobility in the first IGZO layer 110 is improved. In some embodiments, the doping particles of the doping ions in the third IGZO layer 180 may be nitrogen-containing particles, so that the barrier effect of the third IGZO layer 180 is better.
Referring to fig. 7, in some embodiments, the third IGZO layer 180 may be located only between the first IGZO layer 110 and the second gate electrode 150, and the protective layer 170 may also cover sides of the third IGZO layer 180. Since the protective layer 170 has high mechanical strength, when the protective layer 170 covers the side of the third IGZO layer 180, it is possible to provide a strong support for the semiconductor structure, so that the stability of the semiconductor structure can be improved.
Referring to fig. 8, in some embodiments, the third IGZO layer 180 may also be located at opposite sides of the channel region 111, and the source drain doped region 112 may also be located within the third IGZO layer 180. The third IGZO layer 180 covers the entire area of the surface of the first IGZO layer 110 near the substrate 100, which can reduce the process steps of patterning the protective layer 170 and simplify the process flow. At this time, the doped region 113 may also be located in the third IGZO layer 180, and the doped region 113 is still in contact with the protective layer 170.
The embodiment of the disclosure provides a semiconductor structure, which comprises: a substrate; the first IGZO layer is positioned on the substrate and comprises a channel region and source-drain doped regions positioned on two opposite sides of the channel region; the second IGZO layer is at least positioned on the channel region, doped ions are arranged in the second IGZO layer, and the number of oxygen vacancies in the second IGZO layer is smaller than that in the first IGZO layer; the first gate electrode is located on a surface of the second IGZO layer remote from the substrate. The second IGZO layer can better isolate the first IGZO layer from the first grid electrode, so that electron loss in the first IGZO layer can be effectively reduced, carrier concentration in the first IGZO layer is improved, and carrier mobility in the semiconductor structure can be improved.
Accordingly, another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which may be used to form the semiconductor structure. The method for manufacturing a semiconductor structure according to another embodiment of the present disclosure will be described in detail with reference to the accompanying drawings, and the same or corresponding parts as those of the previous embodiment may be referred to for the corresponding description of the previous embodiment, which will not be described in detail.
Referring to fig. 9, a substrate 100 is provided.
In some embodiments, the material of the substrate 100 may include single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may also be a glass substrate or other material such as a III-V compound such as gallium arsenide. In the disclosed embodiment, the material of the base 100 may be in single crystal silicon (Si) or a glass substrate.
Referring to fig. 10 or 11, a second gate electrode 150, a protective layer 170, and a second gate oxide layer 151 are formed. The material of the second gate electrode 150 may include one or more of polysilicon or tungsten, the material of the protective layer 170 may include silicon nitride, and the material of the second gate oxide layer 151 may include silicon oxide.
Referring to fig. 10, since an insulation process is required between the second gate electrode 150 and the substrate 100, an insulation layer 160 may be further formed before forming the second gate electrode 150, the protection layer 170, and the second gate oxide layer 151, and a material of the insulation layer 160 may include silicon nitride. An insulating layer 160 is located on the surface of the substrate 100. After the insulating layer 160 is formed, the second gate 150 may be formed, and the second gate 150 is located on a surface of the insulating layer 160 remote from the substrate 100. The protection layer 170 is formed, the protection layer 170 and the second gate 150 together cover the entire surface of the insulating layer 160 away from the substrate 100, and the protection layer 170 covers the side surface of the second gate 150, and the thickness of the protection layer 170 may be greater than or equal to the thickness of the second gate 150, that is, the top surface of the protection layer 170 may cover the top surface of the second gate 150 or be flush with the top surface of the second gate 150. The second gate oxide layer 151 is formed, and the second gate oxide layer 151 may be located on a surface of the protective layer 170 remote from the substrate 100.
Referring to fig. 11, the process steps of forming the second gate electrode 150, the protective layer 170, and the second gate oxide layer 151 may further include: the protective layer 170 is formed, the protective layer 170 is located on the surface of the substrate 100, and the protective layer 170 covers only a partial area of the surface of the substrate 100. The second gate oxide layer 151 and the second gate electrode 150 are formed such that the second gate oxide layer 151 surrounds the second gate electrode 150, the second gate oxide layer 151 and the protective layer 170 together cover the entire surface of the substrate 100, and the protective layer 170 covers the sides of the second gate oxide layer 151. In the structure formed by this process step, the second gate oxide layer 151 located between the second gate electrode 150 and the substrate 100 may already serve to insulate the second gate electrode 150 from the substrate 100, so that the insulating layer 160 does not need to be formed.
Referring to fig. 12, a third IGZO layer 180 is formed, the third IGZO layer 180 is located on at least a portion of the surface of the second gate oxide layer 151 facing the second gate electrode 150 away from the substrate 100, and the third IGZO layer 180 has doping ions therein, and the number of oxygen vacancies in the third IGZO layer 180 is smaller than that in the first IGZO layer. In some embodiments, the third IGZO layer 180 may further cover the second gate oxide layer 151 and the entire surface of the protective layer 170 away from the substrate 100.
With continued reference to fig. 12, a first IGZO layer 110 is formed, the first IGZO layer 110 being located on the substrate 100, the first IGZO layer 110 including a channel region 111. The first IGZO layer 110 may be on a surface of the third IGZO layer 180 remote from the substrate 100, and the channel region 111 is opposite to the second gate electrode 150.
With continued reference to fig. 12, a second IGZO layer 120 is formed, the second IGZO layer 120 being located at least on the channel region 111, and the second IGZO layer 120 having dopant ions therein, the number of oxygen vacancies in the second IGZO layer 120 being smaller than the number of oxygen vacancies in the first IGZO layer 110. The second IGZO layer 120 may be formed only on the channel region 111, or may also be formed on opposite sides of the channel region 111.
In some embodiments, the method of forming the third IGZO layer 180 doped with the doping ions and the second IGZO layer 120 may be an in-situ doping method. The third IGZO layer 180 and the second IGZO layer 120 are doped with dopant ions during the process of forming the third IGZO layer 180 and the second IGZO layer 120. The in-situ doping process can improve the stability and reliability of the process, and the in-situ doping method is adopted to form the second IGZO layer 120 and the third IGZO layer 180, so that the yield of the semiconductor structure can be improved.
In some embodiments, the gas flow rate of the introduced gas providing the dopant ions may be 15sccm-30sccm when forming the second IGZO layer 120. For example, when the second IGZO layer 120 is formed, the gas flow rate of the gas supplied with the dopant ions may be 15 seem, 17 seem, 20 seem, 23 seem, 25 seem, 27 seem, 30 seem, or the like. If the gas flow for providing the doping ions is too large, the concentration of the doping ions doped into the second IGZO layer 120 is too large, which may cause too small the number of oxygen vacancies in the second IGZO layer 120, affecting the performance of the second IGZO layer 120; if the gas flow rate of the dopant ions is too small, the concentration of the dopant ions doped into the second IGZO layer 120 is too small, the blocking effect of the second IGZO layer 120 on the first gate 130 and the first IGZO layer 110 may be poor, and the first IGZO layer 110 still has more electron loss, so that the carrier mobility of the semiconductor structure still needs to be improved. Therefore, when the second IGZO layer 120 is formed, the gas flow rate of the gas for providing the doping ions needs to be selected to be in a proper range, and when the gas flow rate of the gas for providing the doping ions is 15sccm-30sccm, the second IGZO layer 120 has better performance and can effectively block the first gate 130 and the first IGZO layer 110.
Similarly, when the third IGZO layer 180 having the dopant ions is formed, the gas flow rate of the gas supplied with the dopant ions may be 15sccm to 30sccm.
Referring to fig. 13, a first gate electrode 130 is formed, the first gate electrode 130 being located on a portion of the surface of the second IGZO layer 120 remote from the substrate 100. Before forming the first gate electrode 130, a first gate oxide layer 131 may be formed, where the first gate oxide layer 131 is located on a surface of the second IGZO layer 120 away from the substrate 100, and the first gate oxide layer 131 is located between the first gate electrode 130 and the second IGZO layer 120.
Referring to fig. 14, a sidewall structure 140 is formed, the sidewall structure 140 may be located on a surface of the second IGZO layer 120 remote from the substrate 100, and the sidewall structure 140 may cover sides of the first gate oxide layer 131 and sides of the first gate electrode 130.
With continued reference to fig. 14, a doped region 113 is formed, the doped region 113 being doped with hydrogen ions. The doped region 113 may be located in both side regions of the channel region 111 at this time, and the doped region 113 may be located in the first IGZO layer 110, the second IGZO layer 120, and the third IGZO layer 180. The process of forming the doped region 113 may be a plasma treatment process.
Referring to fig. 15, source-drain doped regions 112 are formed, the source-drain doped regions 112 being located at least on opposite sides of the channel region 111. The source/drain doped region 112 is doped, wherein if N-type doping is required, N-type ions, such as nitrogen ions, phosphorus ions, etc., may be implanted. If P-type doping is required, P-type ions, such as boron ions, aluminum ions, etc., may be implanted. After forming the source-drain doped region 112, the doped region 113 may be located between the channel region 111 and the source-drain doped region 112, and the source-drain doped region 112 may be located within the first IGZO layer 110, the second IGZO layer 120, and the third IGZO layer 180.
In a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure, a substrate is provided; forming a first IGZO layer on the substrate, the first IGZO layer including a channel region; forming a second IGZO layer, wherein the second IGZO layer is at least positioned on the channel region, doped ions are arranged in the second IGZO layer, and the number of oxygen vacancies in the second IGZO layer is smaller than that in the first IGZO layer; forming a first grid electrode, wherein the first grid electrode is positioned on a part of the surface of the second IGZO layer, which is far away from the substrate; source and drain doped regions are formed at least on opposite sides of the channel region. The second IGZO layer can better isolate the first IGZO layer from the first grid electrode, so that electron loss in the first IGZO layer can be effectively reduced, and carrier mobility in the semiconductor structure can be improved.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be assessed accordingly to that of the appended claims.
Claims (14)
1. A semiconductor structure, comprising:
a substrate;
the first IGZO layer is positioned on the substrate and comprises a channel region and source-drain doping regions positioned on two opposite sides of the channel region;
a second IGZO layer, the second IGZO layer being located at least on the channel region and having doping ions therein, the number of oxygen vacancies in the second IGZO layer being smaller than the number of oxygen vacancies in the first IGZO layer;
and a first gate electrode on a surface of the second IGZO layer remote from the substrate.
2. The semiconductor structure of claim 1, wherein the dopant particles of the dopant ions in the second IGZO layer are nitrogen-containing particles.
3. The semiconductor structure of claim 1, wherein a concentration of indium ions in the first IGZO layer is greater than a concentration of indium ions in the second IGZO layer.
4. The semiconductor structure of claim 1, wherein the second IGZO layer is further located on opposite sides of the channel region, and the source drain doped region is further located within the second IGZO layer.
5. The semiconductor structure of claim 1, further comprising:
and the second grid electrode is positioned in the substrate, is positioned on one side of the first IGZO layer far away from the second IGZO layer, and is opposite to the channel region.
6. The semiconductor structure of claim 5, further comprising:
and a third IGZO layer, the third IGZO layer being at least between the channel region and the second gate electrode, and having the dopant ions therein, the number of oxygen vacancies in the third IGZO layer being smaller than the number of oxygen vacancies in the first IGZO layer.
7. The semiconductor structure of claim 6, wherein the third IGZO layer is further located on opposite sides of the channel region, and the source drain doped region is further located within the third IGZO layer.
8. The semiconductor structure of any of claims 1-7, further comprising:
the doped region is doped with hydrogen ions, is at least positioned in the first IGZO layer, and is positioned between the source drain doped region and the channel region.
9. The semiconductor structure of claim 8, further comprising: and the protective layer is positioned on one side surface of the first IGZO layer close to the substrate, and at least contacts with the doped region.
10. The semiconductor structure of claim 1, wherein the second IGZO layer is located only on the channel region.
11. The semiconductor structure of claim 10, further comprising: and the side wall structure is positioned on one side surface of the first IGZO layer away from the substrate, and covers the side surface of the first grid electrode and the side surface of the second IGZO layer.
12. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a first IGZO layer on the substrate, the first IGZO layer including a channel region;
forming a second IGZO layer, wherein the second IGZO layer is at least positioned on the channel region, doped ions are arranged in the second IGZO layer, and the number of oxygen vacancies in the second IGZO layer is smaller than that in the first IGZO layer;
forming a first gate electrode on a portion of the surface of the second IGZO layer remote from the substrate;
and forming source-drain doped regions, wherein the source-drain doped regions are at least positioned on two opposite sides of the channel region.
13. The method of manufacturing according to claim 12, wherein the method of forming the second IGZO layer is an in-situ doping method.
14. The manufacturing method according to claim 13, wherein a gas flow rate of the gas supplying the dopant ions is 15sccm to 30sccm when the second IGZO layer is formed.
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