CN116312370A

CN116312370A - Display panel and display device

Info

Publication number: CN116312370A
Application number: CN202310198058.0A
Authority: CN
Inventors: 匡建; 周星耀; 张蒙蒙; 高娅娜
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2023-03-01
Filing date: 2023-03-01
Publication date: 2023-06-23

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a pixel circuit, wherein the pixel circuit comprises a driving transistor, a data writing transistor and a first module, a first end of the first module and the data writing transistor are connected with a first node, and a second end of the first module and a first pole of the driving transistor are connected with a second node; the working process of the pixel circuit comprises a data frame, wherein the data frame comprises a writing stage, a pre-charging stage and a light-emitting stage; during the write phase: the data writing transistor and the first module are started, the data writing transistor writes the data voltage into the first node, and the first module caches the data voltage and writes the data voltage into the second node; during the precharge phase: the data writing transistor is turned off, the first module is turned on, and the first module writes the cached data voltage into the second node; in the light-emitting stage: the drive transistor generates a drive current under control of its gate voltage. The invention can solve the problem of low gray scale and low frequency display flicker.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

An Organic Light-Emitting Diode (OLED) has the advantages of low power consumption, low cost, self-luminescence, wide viewing angle, fast response speed and the like, and becomes one of research hotspots in the current display field. The electronic product can display in different application scenes by adopting different refresh rates, for example, a driving mode with higher refresh rate is adopted to drive and display dynamic pictures (such as sports events or game scenes) so as to ensure the fluency of the display pictures; the slow lens image or the static picture is driven and displayed by adopting a driving mode with low refresh rate so as to reduce the power consumption. At present, flicker phenomenon exists during low-gray-scale and low-frequency display, which affects visual experience.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, which are used for solving the problem of flicker during low-gray-scale low-frequency display in the prior art.

In a first aspect, an embodiment of the present invention provides a display panel, including a pixel circuit, where the pixel circuit includes a driving transistor, a data writing transistor, and a first module, a first end of the first module and the data writing transistor are connected to a first node, and a second end of the first module and a first pole of the driving transistor are connected to a second node;

the working process of the pixel circuit comprises a data frame, wherein the data frame comprises a writing stage, a pre-charging stage and a light-emitting stage; wherein,,

during the write phase: the data writing transistor and the first module are started, the data writing transistor writes the data voltage into the first node, and the first module caches the data voltage and writes the data voltage into the second node;

during the precharge phase: the data writing transistor is turned off, the first module is turned on, and the first module writes the cached data voltage into the second node;

in the light-emitting stage: the drive transistor generates a drive current under control of its gate voltage.

In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display apparatus, including a display panel provided by any embodiment of the present invention.

The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: a first module is provided in the pixel circuit, the data writing transistor is connected to the second node through the first module, and a first pole of the driving transistor is connected to the second node. The first module buffers the data voltage during a write phase and then provides the buffered data voltage to the second node during a precharge phase to precharge the second node. The first module pre-charges the second node by using the data voltage before the light-emitting stage, so that the potential rising speed of the second node is faster in the light-emitting stage, thereby improving the speed of the driving transistor for generating the driving current, further improving the light-emitting hysteresis effect of the data frame during low-gray-scale display and improving the light-emitting brightness of the data frame. The display flicker problem can be effectively improved when the display is applied to low-gray-scale low-frequency display.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.

Fig. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a timing diagram of the pixel circuit provided in the embodiment of FIG. 1;

FIG. 3 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 5 is a timing diagram of another display panel according to an embodiment of the present invention;

FIG. 6 is a timing diagram of another display panel according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 8 is a timing diagram of another display panel according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 10 is a timing diagram of another display panel according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 12 is a timing chart of another display panel according to an embodiment of the present invention;

fig. 13 is a schematic diagram of a display device according to an embodiment of the invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In the prior art, a low-frequency display mode is realized by superposing data frames and maintaining frames, and a mode with a display refresh rate smaller than 60Hz is generally considered to be a low-frequency display mode. When displaying low gray scale at low frequency, as the data voltage increases, the hysteresis effect of the driving transistor caused by the reset writing data voltage of the pixel circuit is aggravated, so that the larger the brightness difference between the data frame and the sustain frame is, the aggravated the display flicker problem is caused.

In order to solve the problems in the prior art, an embodiment of the present invention provides a display panel, which includes a plurality of pixel circuits and a plurality of light emitting devices, wherein the pixel circuits are coupled with the light emitting devices. The light emitting device is an organic light emitting device or an inorganic light emitting device. The precharge phase is added after the writing phase of the pixel circuit work, and the node in the pixel circuit is charged by utilizing the data voltage in the precharge phase, so that the node is precharged before the light-emitting phase, the light-emitting hysteresis effect of the data frame during low-gray-scale display can be effectively improved, the light-emitting brightness of the data frame is improved, and the display flickering problem is improved.

Fig. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention, and fig. 2 is a timing chart of the pixel circuit according to the embodiment of fig. 1.

As shown in fig. 1, the pixel circuit includes a driving transistor Tm, a data writing transistor M1, and a first module 10, a first terminal of the first module 10 and the data writing transistor M1 are connected to a first node N1, and a second terminal of the first module 10 and a first pole of the driving transistor Tm are connected to a second node N2. The first module 10 is used for writing a data voltage in cooperation with the data writing transistor M1, and is also used for buffering the data voltage and precharging the second node N2 with the buffered data voltage after writing the data voltage.

The pixel circuit further includes an electrode reset transistor M2, a gate reset transistor M3, a threshold compensation transistor M4, a first light emitting control transistor M5, and a second light emitting control transistor M6, wherein the driving transistor Tm is connected in series between the first light emitting control transistor M5 and the second light emitting control transistor M6, a gate of the driving transistor Tm is connected to the third node N3, a first pole of the driving transistor Tm is connected to the second node N2, and a second pole of the driving transistor Tm is connected to the fourth node N4. The gate reset transistor M3 is connected to the third node N3, the first light emitting control transistor M5 is connected to the second node N2, the threshold compensation transistor M4 is connected in series between the third node N3 and the fourth node N4, the first electrode of the second light emitting control transistor M6 is connected to the fourth node N4, the second electrode of the second light emitting control transistor M6 is connected to the fifth node N5, the electrode reset transistor M2 is connected to the fifth node N5, one electrode of the light emitting device PD is connected to the fifth node N5, and the other electrode receives the first power signal Pvee. One plate of the pixel storage capacitor Cst receives the second power signal Pvdd, and the other plate is connected to the first node N1. Optionally, the second power signal Pvdd is a positive power signal, and the first power signal Pvee is a negative power signal. The first power supply signal Pvee and the second power supply signal Pvdd are both constant voltage signals.

The gate reset transistor M3 and the threshold compensation transistor M4 are illustrated in fig. 1 as n-type transistors, and the active layer of the n-type transistor includes a metal oxide. The other transistors in the pixel circuit except the gate reset transistor M3 and the threshold compensation transistor M4 are p-type transistors, and the active layer of the p-type transistor contains silicon. The arrangement can reduce the leakage current of the gate reset transistor M3 and the threshold compensation transistor M4 to the third node N3, and improve the potential stability of the third node N3, namely, the gate potential stability of the driving transistor Tm. The gate of the gate reset transistor M3 receives the scan signal Sn1, the gate of the electrode reset transistor M2 receives the scan signal Sp2, the gate of the data writing transistor M1 receives the scan signal Sp1, the gate of the threshold compensation transistor M4 receives the scan signal Sn2, and the gates of the first and second light emission control transistors M5 and M6 receive the light emission control signal Emit. In addition, the control electrode of the first module 10 receives the scan signal Sp3, and the Data writing transistor M1 receives the Data voltage Data.

As shown in fig. 2, the duty cycle of the pixel circuit includes a reset phase t1, a write phase t2, a precharge phase t3, and a light emitting phase t4. Wherein,,

in the reset phase t1: the scan signal Sn1 controls the gate reset transistor M3 to turn on, and the gate reset transistor M3 writes the reset signal Vref to the third node N3 to reset the gate of the driving transistor Tm.

In the write phase t2: the scan signal Sp1 controls the Data writing transistor M1 to turn on, and the Data writing transistor M1 writes the Data voltage Data to the first node N1; the first module 10 buffers the Data voltage Data written to the first node N1, and simultaneously, the first module 10 writes the Data voltage Data to the second node N2 under the control of the scan signal Sp 2; at this stage, the driving transistor Tm is turned on under the potential control of the third node N3, the scan signal Sn2 controls the threshold compensation transistor M4 to be turned on, and the data voltage is written into the third node N3 and compensates the threshold voltage of the driving transistor Tm. In addition, the electrode reset transistor M2 is turned on under the control of the scan signal Sp1 at this stage to reset the electrode of the light emitting device PD with the reset signal Vref.

In precharge phase t3: the data writing transistor M1 is turned off, the first module 10 is turned on under the control of the scan signal Sp2, and the first module 10 writes the buffered data voltage into the second node N2. The second node N2 is precharged with the Data voltage Data at this stage.

In the light-emitting phase t4: the first and second light emission control transistors M5 and M6 are turned on under the control of the light emission control signal Emit, the driving transistor Tm generates a driving current under the control of the gate voltage thereof, and the light emitting device PD emits light under the control of the driving current.

In the display panel provided by the embodiment of the invention, the first module 10 is arranged in the pixel circuit, the data writing transistor M1 is connected to the second node N2 through the first module 10, and the first pole of the driving transistor Tm is connected to the second node N2. The operation of the pixel circuit comprises a data frame, wherein the data frame at least comprises a writing phase t2, a pre-charging phase t3 and a light-emitting phase t4. The first module 10 caches the Data voltage Data in the writing phase t2, and then provides the cached Data voltage Data to the second node N2 in the precharge phase t3 to precharge the second node N2. Before the light-emitting stage t4, the first module 10 pre-charges the second node N2 with the data voltage, so that the potential of the second node N2 rises faster in the light-emitting stage t4, thereby increasing the speed of the driving transistor Tm to generate the driving current, further improving the light-emitting hysteresis effect of the data frame during low gray scale display, and increasing the light-emitting brightness of the data frame. The display flicker problem can be effectively improved when the display is applied to low-gray-scale low-frequency display.

The gate reset transistor M3 and the threshold compensation transistor M4 are illustrated in fig. 1 as n-type transistors, and the remaining transistors are p-type transistors. In other embodiments, all of the transistors in the pixel circuit are p-type transistors and are not illustrated in the figures.

In addition, the gate reset transistor M3 and the electrode reset transistor M2 shown in fig. 1 each receive the reset signal Vref, that is, both receive the same reset signal. In other embodiments, the gate reset transistor M3 receives a first reset signal, the electrode reset transistor M2 receives a second reset signal, and the voltage values of the first reset signal and the second reset signal are different, which is not illustrated in the drawings. The following related embodiments are illustrated with only the gate reset transistor M3 and the electrode reset transistor M2 receiving the reset signal Vref.

The data frame in the embodiment of the present invention includes a reset phase t1, as illustrated in the timing diagram of fig. 2, the reset phase t1 being performed before the write phase t 2; in the reset phase t1: the gate reset transistor M3 is turned on to supply the reset signal Vref to the gate of the driving transistor Tm. In the embodiment of the invention, the reset phase t1 is firstly executed, the write phase t2 is then executed, and the precharge phase t3 is executed after the write phase t2 in the data frame. The first module 10 is additionally arranged between the data writing transistor M1 and the second node N2, and the second node N2 is precharged by the first module 10 in the precharge phase t3 using the buffered data voltage, so as to increase the speed of generating the driving current by the driving transistor Tm, and further improve the light-emitting hysteresis effect of the data frame during low gray scale display. This embodiment does not change the order of the reset phase t1 and the write phase t2 in the data frame.

As shown in fig. 1, the first module 10 includes a first transistor M7 and a first capacitor Cr. One polar plate of the first capacitor Cr is connected to the first node N1, and the other polar plate is connected to a fixed potential, for example, the other polar plate of the first capacitor Cr is grounded; a first pole of the first transistor M7 is connected to the first node N1, and a second pole of the first transistor M7 is connected to the second node N2. In the writing stage t2, the first capacitor Cr buffers the Data voltage Data written into the first node N1, and the first transistor M7 is turned on under the control of the scan signal Sp2 to provide the Data voltage Data to the second node N2. In the precharge phase t3, the first transistor M7 is turned on again under the control of the scan signal Sp2, and the Data voltage Data buffered by the first capacitor Cr is written into the second node N2 again to precharge. The first capacitor Cr realizes a function of buffering the Data voltage Data, and the working period of the writing stage t2 and the precharge stage t3 is matched by using the switching state of the first transistor M7 to realize a process of writing the Data voltage Data into the pixel circuit and a process of precharging the second node N2. The first module 10 has a simple structure and is easy to realize, and the influence on the whole occupied space of the pixel circuit in the display panel is small.

The first transistor M7 is illustrated in fig. 1 as a p-type transistor, which is not limited by the present invention. In other embodiments, the first transistor M7 is an n-type transistor, which is not illustrated in the drawings.

In some embodiments, as shown in fig. 1, a threshold compensation transistor M4 is connected in series between the gate of the drive transistor Tm and the second pole of the drive transistor Tm; the gate reset transistor M3 and the threshold compensation transistor M4 are n-type transistors, and the active layers of the gate reset transistor M3 and the threshold compensation transistor M4 include metal oxides. By the arrangement, the leakage current of the grid reset transistor M3 and the threshold compensation transistor M4 to the third node N3 in the off state can be reduced, so that the potential stability of the third node N3 is improved, the potential of the third node N3 in the light-emitting stage is prevented from being continuously pulled down due to the leakage current, and the driving current stability provided by the driving transistor Tm can be improved.

In some embodiments, fig. 3 is a schematic diagram of another display panel according to an embodiment of the present invention, as shown in fig. 3, the display panel includes a first scan line 21 and a second scan line 22, a gate of the data writing transistor M1 is electrically connected to the first scan line 21, and a control electrode of the first module 10 is electrically connected to the second scan line 22. In the display panel, one scanning line drives one pixel circuit row, and one pixel circuit row includes a plurality of pixel circuits, so that gates of data writing transistors M1 of the plurality of pixel circuits in the one pixel circuit row are connected to the same first scanning line 21, and first modules 10 of the plurality of pixel circuits in the one pixel circuit row are connected to the same second scanning line 22, and only connection situations of the one pixel circuit with the first scanning line 21 and the second scanning line 22 are illustrated in fig. 3.

The timing of the operation of the pixel circuit in the embodiment of fig. 3 can be understood in conjunction with the timing diagram provided in fig. 2. As shown in fig. 2, the first scan line 21 provides the scan signal Sp1 and the second scan line 22 provides the scan signal Sp2 in the data frame including the writing phase t 2. The scan signal Sp1 comprises a pulse signal and the scan signal Sp2 comprises two consecutive pulse signals in the data frame, the two consecutive pulse signals indicating a certain time interval between the two pulse signals. That is, in the data frame, the first scan line 21 supplies a one-time pulse signal, and the second scan line 22 supplies two continuous pulse signals. The first scan line 21 provides a pulse signal to control the data write transistor M1 to be turned on in the write phase t2, and the second scan line 22 provides a pulse signal to control the first module 10 to be turned on in the write phase t2 and the precharge phase t3.

In the display panel provided by the embodiment of the invention, when the pixel circuit works in a data frame, the first module 10 works once in the writing stage t2 and the precharge stage t3 respectively. The second scan line 22 controls the first module 10 to operate with the data writing transistor M1 to complete the process of writing the data voltage when the first pulse signal is provided, and controls the first module 10 to write the buffered data voltage to the second node N2 when the second scan line 22 provides the second pulse signal to precharge the second node N2. The continuous two pulse signals are used to control the operation of the first module 10 in the writing phase t2 and the precharge phase t3, that is, the continuous enable signal is not used to control the operation of the first module 10 in the writing phase t2 and the precharge phase t3. If the second scan line 22 is used to provide a pulse signal to control the first module 10 to operate in the writing phase t2 and the pre-charging phase t3, the second node N2 is continuously charged after the data writing transistor M1 is turned off, so that the potential of the pixel storage capacitor Cst is lost, the potential of the third node N3 is reduced, the written data voltage is inaccurate, and finally the light emitting brightness of the light emitting device is inaccurate. The embodiment of the invention provides continuous two pulse signals on the second scanning line 22 of the data frame, and can ensure that the second node N2 is precharged after the potential of the pixel storage capacitor Cst is stable, so as to ensure that accurate data voltage is written in to ensure that the light emitting brightness of the light emitting device is accurate.

In some embodiments, as shown in fig. 3, the display panel further includes a third scan line 23, and the gate of the threshold compensation transistor M4 is electrically connected to the third scan line 23; the threshold compensation transistors M4 of a plurality of pixel circuits in one pixel circuit row are connected to the same third scanning line 23. As shown in fig. 2, the third scan line 23 supplies a scan signal Sn2. The scan signal Sn2 includes one pulse signal in the data frame, that is, the third scan line 23 supplies one pulse signal in the data frame. Wherein, in the writing phase t2: the third scan line 23 provides a pulse signal to control the threshold compensation transistor M4 to be turned on for compensating the threshold voltage of the driving transistor Tm, and at this stage, the threshold compensation transistor M4 is turned on to complete the writing of the data voltage to the third node N3 in cooperation with the writing of the data voltage. As can be seen from fig. 2, the start time of the second pulse signal provided by the second scan line 22 is later than the end time of the pulse signal provided by the third scan line 23, so that the second node N2 is precharged after the data writing period t2 is completely ended, that is, after the potential of the pixel storage capacitor Cst is stabilized, so as to ensure that the accurate data voltage is written to make the light emitting brightness of the light emitting device accurate.

In some embodiments, the display panel includes a first mode of operation; in a first mode of operation, a duty cycle of the pixel circuit includes a data frame and at least one sustain frame. The data frame includes a writing period t2, and the sustain frame does not include the writing period t2, and the sustain frame is performed after the data frame, and the light emitting device is controlled at the sustain frame to maintain the brightness of the data frame. The first working mode is a low-frequency working mode.

Fig. 4 is a schematic diagram of another pixel circuit according to an embodiment of the present invention, and fig. 5 is a timing chart of another display panel according to an embodiment of the present invention. The reference numerals of the transistors in the pixel circuit provided in fig. 4 can be understood with reference to fig. 1, and the difference between fig. 4 and fig. 1 is that the Data writing transistor M1 receives the Data voltage Data or the adjustment voltage Vp. Fig. 5 illustrates a data frame Z1 and one sustain frame Z2. As shown in fig. 5, the data frame Z1 includes a reset phase t1, a write phase t2, a precharge phase t3, and a light-emitting phase t4, and the sustain frame Z2 includes a adjust phase t5 and a light-emitting phase t4.

Wherein, in the adjustment phase t5: the scan signal Sp1 controls the data writing transistor M1 to turn on to write the adjustment voltage to the first node N1, the first capacitor Cr in the first module 10 buffers the adjustment voltage Vp, and the first transistor M7 in the first module 10 turns on to write the adjustment voltage Vp to the second node N2 under the control of the scan signal Sp2, wherein the adjustment voltage Vp is a constant voltage. In the light emitting period t4, the third node N3 maintains the potential in the data frame Z1, and the driving transistor Tm generates a driving current under the control of the potential of the third node N3, so that the light emitting device PD maintains the luminance of the data frame Z1. In this embodiment, in the adjustment stage t5 set in the sustain frame Z2, the first module 10 works in cooperation with the data writing transistor M1 in the adjustment stage t5 to write the adjustment voltage Vp into the second node N2, and the bias state of the driving transistor Tm can be adjusted by using the adjustment voltage Vp, so that the threshold voltage drift caused by the hysteresis effect of the driving transistor Tm when the driving transistor Tm works in a fixed bias state for a long time is improved, and further, the influence of the hysteresis effect of the driving transistor Tm on the display effect is improved. In addition, in this embodiment, the data writing transistor M1 and the first module 10 are multiplexed in the adjustment stage, and the adjustment voltage Vp is transmitted by the data line in the display panel in the sustain frame Z2, so that it is not necessary to add the adjustment transistor and the signal line for transmitting the adjustment voltage Vp to the panel, and wiring in the display panel can be simplified, and wiring space can be saved. The precharge phase t3 set in the data frame Z1 is matched with the adjustment phase t5 in the maintenance frame Z2, so that better bias adjustment effect can be realized, and the problem of picture flicker is effectively improved.

In some embodiments, as shown in fig. 5, the sustain frame Z2 further includes an auxiliary adjustment stage t6. In the auxiliary regulation phase t6: the scan signal Sp1 controls the data writing transistor M1 to be turned off, and the first transistor M7 in the first module 10 is turned on under the control of the scan signal Sp2 to write the regulated voltage Vp buffered in the regulation stage t5 to the second node N2. In this embodiment, the first module 10 writes the adjustment voltage Vp into the second node N2 in the auxiliary adjustment stage t6, and in this stage, the adjustment voltage Vp can also adjust the bias state of the driving transistor Tm, which increases the bias adjustment time in the maintenance frame Z2, so as to further improve the threshold voltage drift caused by the hysteresis effect of the driving transistor Tm when the driving transistor Tm operates in the fixed bias state for a long time, and further improve the influence of the hysteresis effect of the driving transistor Tm on the display effect.

In some embodiments, the display panel includes a first scan line 21 and a second scan line 22; the gate of the data writing transistor M1 is electrically connected to the first scan line 21, and the control electrode of the first module 10 is electrically connected to the second scan line 22; the first scan line 21 provides a scan signal Sp1, and the second scan line 22 provides a scan signal Sp2. As seen in connection with the timing of fig. 5, in data frame Z1: the first scan line provides a pulse signal once to control the data write transistor M1 to be turned on in the write phase t2, and the second scan line provides a pulse signal twice to control the first module 10 to be turned on in the write phase t2 and the precharge phase t3, respectively. In the sustain frame Z2, the first scan line provides a first pulse signal to control the data write transistor M1 to be turned on in the adjustment phase t5, and the second scan line provides a second pulse signal to control the first module 10 to be turned on in the adjustment phase t5 and the auxiliary adjustment phase t6, respectively. In this embodiment, in the data frame Z1 and the sustain frame Z2, the second scan line 22 provides two continuous pulse signals, where the writing phase t2 corresponds to the adjusting phase t5, and the precharge phase t3 corresponds to the auxiliary adjusting phase t6, so that the second scan line provides the same signal in the data frame Z1 and the sustain frame Z2, and the signal in the second scan line 22 does not need to be changed, so that the signal providing mode of the second scan line 22 can be simplified, that is, the control mode of the display panel is simplified, and the operation amount of the driving chip is reduced.

In other embodiments, fig. 6 is a timing chart of another display panel according to an embodiment of the invention. As shown in fig. 6, in data frame Z1: the first scan line provides a pulse signal once to control the data write transistor M1 to be turned on in the write phase t2, and the second scan line provides a pulse signal twice to control the first module 10 to be turned on in the write phase t2 and the precharge phase t3, respectively. In the sustain frame Z2, the first scan line 21 and the second scan line 22 each supply a pulse signal once; the first scan line 21 provides a pulse signal to control the data write transistor M1 to be turned on in the adjustment phase t5, and the second scan line 22 provides a pulse signal to control the first module 10 to be turned on in the adjustment phase t 5. In the adjustment phase t5, the adjustment voltage Vp is written to the second node N2 to adjust the bias state of the driving transistor Tm. In this embodiment, the number of times of providing the pulse signal by the second scan line 22 in the data frame Z1 and the sustain frame Z2 is different, and the signal providing manner of the second scan line 22 is adjusted in the sustain frame Z2, so that the second scan line 22 only writes the adjusting phase t5 to the second node N2 in cooperation with the data writing transistor M1 in the adjusting phase t 5.

In other embodiments, fig. 7 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, and fig. 8 is a timing chart of another display panel provided by an embodiment of the present invention. As shown in fig. 7, the pixel circuit further includes a regulating transistor M8, the regulating transistor M8 is connected to the second node N2, the regulating transistor M8 receives the regulating signal Vp, and the gate of the regulating transistor M8 receives the scan signal Sp3.

As seen in connection with fig. 8, in the first mode of operation, the duty cycle of the pixel circuit includes a data frame Z1 and at least one sustain frame Z2; the sustain frame Z2 includes a regulation phase t5 and a lighting phase t4; wherein,,

in the conditioning phase t5: the scan signal Sp1 controls the data writing transistor M1 to be turned off, the scan signal Sp2 controls the first module 10 to be turned off, the scan signal Sp3 controls the adjusting transistor M8 to be turned on, and the adjusting transistor M8 writes the adjusting voltage Vp into the second node N2. The bias state of the driving transistor Tm is adjusted with the adjustment voltage Vp in the adjustment phase t 5. In this embodiment, the adjustment transistor M8 is disposed in the pixel circuit, the bias state of the driving transistor Tm is adjusted in the sustain frame Z2 by the adjustment transistor M8, the first module 10 is kept in the off state all the time in the sustain frame Z2, the sustain frame Z2 does not include the reset phase and the write phase, the pulse time of the scan signal Sp3 is not affected by the pulse width of the scan signal in the data frame Z2, and the pulse time of the scan signal Sp3 can be set relatively long to enhance the adjustment capability of the bias state of the driving transistor Tm.

In other embodiments, the adjusting transistor M8 is connected to the second pole of the driving transistor Tm, i.e. connected to the fourth node N4, and the adjusting transistor M8 writes the adjusting voltage Vp to the second pole of the driving transistor Tm in the adjusting phase t5 to adjust the bias state of the driving transistor Tm.

In other embodiments, fig. 9 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, and fig. 10 is a timing chart of another display panel provided by an embodiment of the present invention. As shown in fig. 9, the pixel circuit includes a data writing transistor M1, an electrode reset transistor M2, a gate reset transistor M3, a first light emitting control transistor M5, a second light emitting control transistor M6, a first module 10, a pixel storage capacitor Cst, and a voltage stabilizing transistor M9, wherein one plate of the pixel storage capacitor Cst is connected to a gate of the driving transistor Tm, and the other plate is connected to a fixed potential (the second power signal Pvdd is schematically received in fig. 9); the voltage stabilizing transistor M9 is connected between the gates of the gate reset transistor M3 and the driving transistor Tm; the active layer of the gate reset transistor M3 includes silicon, and the active layer of the voltage stabilizing transistor M9 includes metal oxide. In this embodiment, the transistors other than the voltage stabilizing transistor M9 are p-type transistors.

As shown in fig. 10, the operation of the pixel circuit includes a data frame Z1, and the data frame Z1 includes a reset phase t1, a write phase t2, a precharge phase t3, and a light-emitting phase t4. Wherein,,

in the reset phase t1: the gate reset transistor M3 is turned on under the control of the scan signal Sp4, and the voltage stabilizing transistor M9 is turned on under the control of the scan signal Sn, and the reset signal Vref is supplied to the third node N3 to reset the gate of the driving transistor Tm. In the write phase t2: the scan signal Sp1 controls the Data writing transistor M1 to be turned on, the scan signal Sp2 controls the first module 10 to be turned on, the scan signal Sn controls the voltage stabilizing transistor M9 to be turned on, the Data voltage Data is written into the third node N3, and the threshold voltage of the driving transistor Tm is compensated by the voltage stabilizing transistor M9; while the first module 10 buffers the Data voltage Data at this stage. In precharge phase t3: the first module 10 turns on the buffered Data voltage Data to be supplied to the second node N2 to precharge the second node N2. In the light-emitting phase t4: the first and second light emission control transistors M5 and M6 are turned on under the control of the light emission control signal Emit, the driving transistor Tm generates a driving current under the control of the gate voltage thereof, and the light emitting device PD emits light under the control of the driving current. As can be seen from the timing chart of fig. 10, the scan signal Sn provides a continuous high level signal (the high level signal is the enable signal) in the reset phase t1 and the write phase t2, so that the voltage stabilizing transistor M9 maintains the on state in both phases.

The first module 10 is disposed between the data writing transistor M1 and the second node N2, and the first module 10 is configured to write a data voltage in cooperation with the data writing transistor M1, and is further configured to buffer the data voltage and precharge the second node N2 with the buffered data voltage after writing the data voltage. The first module 10 pre-charges the second node N2 with the data voltage before the light emitting period t4, and the potential of the second node N2 rises faster during the light emitting period t4, so that the driving current generating speed of the driving transistor Tm can be increased, the light emitting hysteresis effect of the data frame during low gray scale display can be improved, and the light emitting brightness of the data frame can be improved. The display flicker problem can be effectively improved when the display is applied to low-gray-scale low-frequency display. In addition, the voltage stabilizing transistor M9 is connected between the gate reset transistor M3 and the third node N3, the voltage stabilizing transistor M9 is matched with the gate reset transistor M3 to reset the gate of the driving transistor Tm, the voltage stabilizing transistor M9 is matched with the data writing transistor M1 to complete the process of writing data voltage and compensating threshold value, the active layer of the voltage stabilizing transistor M9 is provided with metal oxide, so that leakage current to the third node N3 can be reduced, the potential stability of the third node N3 is improved, the potential of the third node N3 is prevented from being continuously pulled down in a light-emitting stage due to the leakage current, and the driving current stability provided by the driving transistor Tm can be improved.

As shown in fig. 10, the operation of the pixel circuit further includes a sustain frame Z2, and the sustain frame Z2 includes a regulation phase t5 and a light emission phase t4. In the conditioning phase t5: the scan signal Sp1 controls the data writing transistor M1 to turn on to write the adjusting voltage to the first node N1, the first capacitor Cr in the first module 10 buffers the adjusting voltage Vp, and the first transistor M7 in the first module 10 turns on to write the adjusting voltage Vp to the second node N2 under the control of the scan signal Sp2. In the light emitting period t4, the third node N3 maintains the potential in the data frame Z1, and the driving transistor Tm generates a driving current under the control of the potential of the third node N3, so that the light emitting device PD maintains the luminance of the data frame Z1. In the adjustment stage t5 of the setting of the sustain frame Z2, the first module 10 works in the adjustment stage t5 in cooperation with the data writing transistor M1 to write the adjustment voltage Vp into the second node N2, and the bias state of the driving transistor Tm can be adjusted by using the adjustment voltage Vp, so that the threshold voltage drift caused by the hysteresis effect of the driving transistor Tm when the driving transistor Tm works in a fixed bias state for a long time is improved, and further, the influence of the hysteresis effect of the driving transistor Tm on the display effect is improved.

The sustain frame Z2 shown in fig. 10 further includes an auxiliary adjustment stage t6, in which the first module 10 writes the adjustment voltage Vp into the second node N2, and in this stage the adjustment voltage Vp can also adjust the bias state of the driving transistor Tm, which increases the bias adjustment time in the sustain frame Z2, so as to further improve the threshold voltage drift caused by the hysteresis effect of the driving transistor Tm in the fixed bias state when the driving transistor Tm operates for a long period of time. In this embodiment, the scan signal Sp2 is the same signal in the data frame Z1 and the sustain frame Z2, and the control method of the display panel can be simplified.

In other embodiments, the scan signal Sp2 received by the control terminal of the first module 10 includes two pulses in the data frame Z1 and one pulse in the sustain frame Z2, which are not illustrated in the drawings.

In other embodiments, fig. 11 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, and fig. 12 is a timing chart of another display panel provided by an embodiment of the present invention. The pixel circuit comprises a driving transistor Tm, a data writing transistor M1, an electrode reset transistor M2, a grid reset transistor M3, a first light emitting control transistor M5, a second light emitting control transistor M6, a first module 10, a pixel storage capacitor Cst, a voltage stabilizing transistor M9 and a threshold value compensation transistor M4, wherein the active layer of the threshold value compensation transistor M4 comprises silicon; the first pole of the threshold compensation transistor M4 is connected to the second pole of the driving transistor Tm, and the second pole of the threshold compensation transistor M4 is connected to the voltage stabilizing transistor M9 and the gate reset transistor M3. Namely, the threshold compensation transistor M4 is connected to the third node N3 through the voltage stabilizing transistor M9. The gate of the threshold compensation transistor M4 receives the scan signal Sp5.

As shown in fig. 12, in the writing stage t2 of the Data frame Z1, the scan signal Sp5 controls the threshold compensation transistor M4 to be turned on, and the threshold compensation transistor M4 works in cooperation with the voltage stabilizing transistor M9, the Data writing transistor M1, and the first module 10 to write the Data voltage Data to the third node N3 and compensate the threshold voltage of the driving transistor Tm. In this embodiment, the threshold compensation transistor M4 and the gate reset transistor M3 are both connected to the third node N3 through the voltage stabilizing transistor M9, and the effect of reducing the leakage current to the third node N3 can be achieved by providing only that the active layer of the voltage stabilizing transistor M9 includes a metal oxide.

In addition, in the embodiment including the sustain frame Z2 as shown in fig. 12, the scan signal Sp5 does not include a pulse signal in the sustain frame Z2, that is, the threshold compensation transistor M4 is in an off state in the sustain frame Z2. In the adjustment stage t5 of the maintenance frame Z2, the data writing transistor M1 and the first module 10 are used to cooperate to write the adjustment voltage Vp to the second node N2, and in the auxiliary adjustment stage t6, the first module 10 writes the adjustment voltage Vp to the second node N2 again, so that the bias adjustment time in the maintenance frame Z2 is increased, and further, the threshold voltage drift caused by the hysteresis effect of the driving transistor Tm in the fixed bias state during long-term operation is improved.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 13 is a schematic diagram of a display device provided by the embodiment of the present invention, and as shown in fig. 13, the display device includes a display panel 100 provided by any embodiment of the present invention. The display device provided by the embodiment of the invention can be electronic equipment such as a mobile phone, a tablet personal computer, a television, a vehicle-mounted display device and the like.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A display panel, wherein the display panel comprises a pixel circuit, the pixel circuit comprises a driving transistor, a data writing transistor and a first module, a first end of the first module and the data writing transistor are connected with a first node, and a second end of the first module and a first pole of the driving transistor are connected with a second node;

during the write phase: the data writing transistor and the first module are started, the data writing transistor writes data voltage into the first node, and the first module caches the data voltage and writes the data voltage into the second node;

during the precharge phase: the data writing transistor is closed, the first module is opened, and the first module writes the cached data voltage into the second node;

in the light emitting phase: the drive transistor generates a drive current under control of its gate voltage.

2. The display panel of claim 1, wherein the display panel comprises,

the first module includes a first transistor and a first capacitor; one polar plate of the first capacitor is connected with the first node, and the other polar plate is connected with a fixed potential; a first pole of the first transistor is connected to the first node and a second pole of the first transistor is connected to the second node.

3. The display panel of claim 1, wherein the display panel comprises,

the display panel comprises a first scanning line and a second scanning line; the grid electrode of the data writing transistor is electrically connected with the first scanning line, and the control electrode of the first module is electrically connected with the second scanning line; wherein,,

in the data frame, the first scanning line provides a pulse signal for controlling the data writing transistor to be turned on in the writing stage, and the second scanning line provides a pulse signal for controlling the first module to be turned on in the writing stage and the precharge stage respectively.

4. The display panel according to claim 3, wherein,

the pixel circuit further includes a threshold compensation transistor connected between the gate of the drive transistor and a second pole;

the display panel further comprises a third scanning line, and the grid electrode of the threshold compensation transistor is electrically connected with the third scanning line;

during the write phase: the third scanning signal provides a primary pulse signal to control the threshold compensation transistor to be turned on so as to compensate the threshold voltage of the driving transistor; wherein,,

the start time of the second pulse signal provided by the second scanning line is later than the end time of the pulse signal provided by the third scanning line.

5. The display panel of claim 1, wherein the display panel comprises,

the display panel comprises a first working mode;

in the first operation mode, the working period of the pixel circuit comprises the data frame and at least one maintenance frame; the sustain frame includes an adjustment phase and the lighting phase; wherein,,

in the conditioning phase: the data writing transistor and the first module are started, the data writing transistor writes the regulating voltage into the first node, and the first module caches the regulating voltage and writes the regulating voltage into the second node.

6. The display panel of claim 5, wherein the display panel comprises,

in the sustain frame, the first scan line and the second scan line each provide a pulse signal; the first scanning line provides a pulse signal to control the data writing transistor to be started in the adjusting stage, and the second scanning line provides a pulse signal to control the first module to be started in the adjusting stage.

7. The display panel of claim 5, wherein the display panel comprises,

the maintenance frame further comprises an auxiliary adjustment phase;

in the auxiliary adjustment phase: the data writing transistor is turned off, the first module is turned on, and the first module writes the cached regulating voltage into the second node.

8. The display panel of claim 7, wherein the display panel comprises,

in the maintenance frame, the first scanning line provides a pulse signal for controlling the data writing transistor to be turned on in the adjustment stage, and the second scanning line provides a pulse signal for controlling the first module to be turned on in the adjustment stage and the auxiliary adjustment stage respectively.

9. The display panel of claim 1, wherein the display panel comprises,

the pixel circuit further includes a regulating transistor connected to the second node or to a second pole of the driving transistor;

the display panel comprises a first working mode;

in the conditioning phase: the data writing transistor and the first module are turned off, the adjusting transistor is turned on, and the adjusting transistor writes an adjusting voltage to the second node or to the second pole of the driving transistor.

10. The display panel of claim 1, wherein the display panel comprises,

the pixel circuit includes a gate reset transistor coupled to a gate of the drive transistor;

the data frame further includes a reset phase, the reset phase being performed prior to the write phase;

in the reset phase: the gate reset transistor is turned on to provide a reset signal to the gate of the drive transistor.

11. The display panel of claim 10, wherein the display panel comprises,

the pixel circuit comprises a pixel storage capacitor and a voltage stabilizing transistor;

one polar plate of the pixel storage capacitor is connected with the grid electrode of the driving transistor, and the other polar plate is connected with a fixed potential; the voltage stabilizing transistor is connected between the grid reset transistor and the grid of the driving transistor;

the active layer of the grid reset transistor comprises silicon, and the active layer of the voltage stabilizing transistor comprises metal oxide.

12. The display panel of claim 10, wherein the display panel comprises,

the pixel circuit further includes a threshold compensation transistor, an active layer of the threshold compensation transistor including silicon; the first pole of the threshold compensation transistor is connected with the second pole of the driving transistor, and the second pole of the threshold compensation transistor is connected with the voltage stabilizing transistor and the grid reset transistor.

13. The display panel of claim 10, wherein the display panel comprises,

the pixel circuit further includes a threshold compensation transistor connected in series between the gate of the drive transistor and a second pole of the drive transistor; wherein,,

the active layers of the gate reset transistor and the threshold compensation transistor each include a metal oxide.

14. A display device comprising the display panel according to any one of claims 1 to 13.