KR20090016050A - Electro-luminescence pixel, panel with the pixels, and device and method of driving the panel - Google Patents

Abstract

An electro-luminescence pixel, an electro-luminescence panel including the same, and a device and a method for driving the panel are provided to present the image of the uniform luminance by correcting the threshold voltage of the thin film transistor, the threshold voltage of the light emitting diode and the variation of voltage on the supply voltage line. An electro-luminescence pixel comprises the first thin film transistor(MN21), the capacitor(CSt21), the second thin film transistor(MN22) and the third thin film transistor(MN23). The first thin film transistor controls the current amount flowing in the light emitting diode connected to the first supply voltage line. The capacitor stores the control voltage supplied to the gate electrode of the first thin film transistor. The second thin film transistor stores the pixel driving signal on the data line in at the capacitor. The third thin film transistor charges the capacitor with the threshold voltage of the light emitting diode, the threshold voltage of the first thin film transistor and the difference voltage and the resultant voltage of the supply voltage on the first supply voltage line.

Description

Electroluminescent pixel, electroluminescent panel including the same, driving device and method for driving the electroluminescent panel {Electro-Luminescence Pixel, Panel with the Pixels, and Device and Method of driving the Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electroluminescent panel that displays an image by adjusting the amount of emitted light, and more particularly, to an electroluminescent pixel including a light emitting diode.

Conventional flat panel display devices display an image on a flat panel such as a liquid crystal panel, an electroluminescence panel, a plasma display panel, or the like. Such a flat panel display device can be made slimmer and lighter, and a large screen can be easily implemented. Accordingly, flat panel displays are being used as display devices for computer systems, television receivers, and telecommunications devices in place of conventional cathode ray tube displays.

Among flat panel displays, the electroluminescent display is spotlighted in that it has a wide viewing angle and does not require a separate light source. This is because the electroluminescent display includes a plurality of electroluminescent pixels arranged in an active matrix form on a flat plate. The electroluminescent panel used in the electroluminescent display device displays an image by causing each of the electroluminescent pixels to generate an amount of light corresponding to a voltage or a current of the pixel data signal.

The electroluminescent pixel responsive to the pixel data signal is, as shown in FIG. 1, a connected ELD and a first NMOS thin film connected in series between the first and second supply voltage lines VL1 and VL2. A transistor MN11 is provided. The high potential voltage VDD is supplied to the first supply voltage line VL1, while the low potential voltage VL2 is supplied to the second supply voltage line VL2. The first NMOS thin film transistor MN11 adjusts the amount of current supplied from the first supply voltage line VL1 to the electroluminescent diode ELD in response to the voltage on the control node CN. The light emitting diode ELD emits light corresponding to the amount of current from the first supply voltage line VL1 to display the flash point of the image.

The electroluminescent pixel of FIG. 1 includes a second NMOS thin film transistor MN12 connected between a gate line GL, a data line DL, and a control node CN, and a control node CN and an electroluminescent diode ( A storage capacitor Cst11 is connected between the positive terminals of the ELD. The second NMOS thin film transistor MN12 switches the pixel data signal Vps to be supplied from the data line DL to the control node CN in response to the scan signal SS on the gate line GL. In the pixel voltage write period Tpw in which the second NMOS thin film transistor MN12 is turned on by the scan signal SS having a high potential voltage (ie, high logic) as shown in FIG. The capacitor Cst11 charges the voltage of the pixel driving signal Vps supplied from the data line DL via the control node CN. In this case, the voltage on the control node CN becomes the sum voltage Vps + Vth_eld of the voltage Vps of the pixel driving signal stored in the storage capacitor Cst11 and the threshold voltage Vth_eld of the ELD. This is because the storage capacitor Cst11 forms a series circuit with the electroluminescent diode ELD. By the voltage Vps + Vth_eld on the control node CN, the first NMOS thin film transistor MN11 is continuously maintained during the image display period (that is, the turn-off period of the second NMOS thin film transistor MN12) Tem. Driven. As described above, the electroluminescent pixel of FIG. 1 can compensate for the threshold voltage of the ELD and prevent unevenness of luminance due to variation and variation of the threshold voltage of the ELD.

The electroluminescent pixel may be configured as shown in FIG. 3. In the electroluminescent pixel of FIG. 3, an electroluminescent pixel in response to a pixel data signal is connected between a cathode terminal of an electroluminescent diode ELD connected to a first voltage line VL1 and a second voltage line VL2. One PMOS thin film transistor MP11 is provided. The high potential voltage VDD is supplied to the first supply voltage line VL1, while the low potential voltage VL2 is supplied to the second supply voltage line VL2. The first PMOS thin film transistor MP11 adjusts the amount of current supplied to the electroluminescent diode ELD in response to the voltage on the control node CN. The light emitting diode ELD emits light corresponding to the amount of current controlled by the first PMOS thin film transistor MP11 to display a flash point of the image.

3 includes a second PMOS thin film transistor MP12 connected between the gate line GL, the data line DL, and the control node CN, and the control node CN and the electroluminescent diode ( The storage capacitor Cst12 connected between the cathode terminals of ELD is provided. The second PMOS thin film transistor MP12 switches the pixel data signal Vps to be supplied from the data line DL to the control node CN in response to the scan signal / SS on the gate line GL. In the pixel voltage write period Tpw in which the second PMOS thin film transistor MP12 is turned on by the scan signal / SS of the low potential voltage (ie, low logic) as shown in FIG. 4, The storage capacitor Cst12 charges the voltage of the pixel data signal Vps supplied from the data line DL via the control node CN. In this case, the voltage on the control node CN becomes a sum voltage Vps + Vth_eld of the pixel driving voltage Vps stored in the storage capacitor Cst12 and the threshold voltage Vth_eld of the ELD. This is because the storage capacitor Cst12 forms a series circuit with the electroluminescent diode ELD. The voltage Vps stored in the storage capacitor Cst12 is maintained until the second PMOS thin film transistor MP12 is turned on again. By the voltage Vps + Vth_eld on the control node CN, the first PMOS thin film transistor MP11 is in a period during which an image is displayed (ie, the turn-off period of the second PMOS thin film transistor MP12) Tem. It is continuously driven. As described above, the electroluminescent pixel of FIG. 3 can compensate for the threshold voltage of the ELD to prevent the luminance unevenness due to the variation or variation of the threshold voltage of the ELD.

  However, in the conventional electroluminescent pixel, the threshold voltage Vth_mx11 of the first thin film transistor MN11 or MP11 for controlling the amount of current flowing through the electroluminescent diode may also vary. In addition, the threshold voltage of the driving thin film transistor may vary depending on the EL pixels. In other words, there may be a variation in the threshold voltage of the driving thin film transistor of the electroluminescent pixel. In addition, there may be deviations and fluctuations in the high potential voltage or the low potential voltage due to the unevenness of the impedance of the supply voltage line VL1 or VL2 to which the anode or cathode of the electroluminescent diode is connected. Such fluctuations in the threshold voltages of the driving thin film transistors and fluctuations and deviations in the voltages on the supply voltage lines not only prevent the electroluminescent pixels from responding precisely to the pixel driving voltage but also prevent the pixels from being correctly displayed according to the pixel driving voltage. As a result, the luminance of the electroluminescent panel and the electroluminescent display device is not uniform and the image quality of the image is deteriorated.

It is therefore an object of the present invention to provide an electroluminescent pixel suitable for accurately displaying a flash point in response to a pixel drive signal.

Another object of the present invention is to provide an electroluminescent panel suitable for displaying an image of uniform brightness and quality.

It is still another object of the present invention to provide an electroluminescent display and a driving method thereof suitable for displaying an image of uniform luminance and quality.

According to an aspect of the present invention, there is provided an electroluminescent pixel, including: a first thin film transistor configured to control an amount of current flowing through an electroluminescent diode connected to a first supply voltage line; A capacitor storing a control voltage supplied to a gate electrode of the first thin film transistor; A second thin film transistor configured to store a pixel driving signal on a data line in the capacitor in response to a scan signal; A third thin film transistor configured to charge the capacitor with a difference voltage and a sum voltage of the threshold voltage of the EL, the threshold voltage of the first thin film transistor, and the supply voltage on the first supply voltage line, in response to the scan signal; It is provided.

According to another aspect of the present invention, an electroluminescent panel includes: a plurality of pairs of gate lines and emission control lines; A plurality of data lines; A first thin film transistor and a first thin film for controlling an amount of current flowing through an electroluminescent diode connected to a first supply voltage line in each of the regions divided by the plurality of pairs of gate lines and emission control lines and the plurality of data lines A capacitor for storing a control voltage supplied to a gate electrode of a transistor; a second thin film transistor for storing a pixel driving signal on the data line in the capacitor in response to a scan signal on the gate line; and a scan signal on the gate line. An electric field including a third thin film transistor configured to charge the capacitor in response to a difference and a sum voltage of the threshold voltage of the EL, the threshold voltage of the first thin film transistor, and the supply voltage on the first supply voltage line. A light emitting pixel is provided.

In another exemplary embodiment, an EL display device includes a plurality of pairs of gate lines, a plurality of data lines, the plurality of pairs of gate lines, emission control lines, and regions divided by the plurality of data lines. A first thin film transistor for controlling the amount of current flowing through the electroluminescent diode connected to the first supply voltage line, a capacitor for storing a control voltage supplied to the gate electrode of the first thin film transistor, and a scan signal on the gate line A second thin film transistor for storing a pixel driving signal on the data line in the capacitor, a threshold voltage of the electroluminescent diode, a threshold voltage of the first thin film transistor, and the capacitor in response to the scan signal on the gate line Wherein the difference and sum voltage of the supply voltage on the first supply voltage line An electroluminescent panel having electroluminescent pixels comprising a third thin film transistor charged in a capacitor; A gate driver for driving gate lines on the electroluminescent panel; A radiation line driver for driving the radiation control lines on the electroluminescent panel in any one of a form complementary to and partially overlapping with the gate lines; And a data driver supplying a pixel driving voltage to data lines on the electroluminescent panel.

In another embodiment, a method of driving an EL display device includes: a plurality of gate lines, a plurality of data lines, the plurality of pairs of gate lines and emission control lines, and an area divided by the plurality of data lines. Each of the electroluminescent panel includes electroluminescent pixels including a thin film transistor for controlling an amount of current flowing through an electroluminescent diode connected to a supply voltage line, and a capacitor for storing a control voltage supplied to a gate electrode of the first thin film transistor. An electroluminescent display for displaying an image on a display. The driving method includes supplying pixel driving voltages on the data lines on the electroluminescent panel; The gate line on the electroluminescent panel is sequentially-enabled so that each of the electroluminescent pixels is combined with either the sum of the threshold voltages of the thin film transistor and the electroluminescent diode and the sum of the voltage on the supply voltage line and the difference voltage. Causing a pixel driving voltage to charge each of the capacitors of the electroluminescent pixel; And sequentially disabling the gate line on the electroluminescent panel so that each of the electroluminescent pixels emits light according to a voltage stored in a capacitor.

According to the above configuration, the electroluminescent pixel according to the present invention is corrected by the threshold voltage of the EL, the threshold voltage of the EL driving thin film transistor, and the voltage on the supply voltage line when the pixel driving signal is charged. In some cases, the pixel driving signal is charged in the charging capacitor so that the amount of current flowing through the electroluminescent diode during light emission is varied only in accordance with the voltage of the pixel driving signal. Accordingly, the electroluminescent pixel according to the present invention allows the amount of emitted light to accurately respond to the voltage of the pixel driving signal. In addition, the electroluminescent panel in which the electroluminescent pixels are arranged in a matrix form also provides an image of uniform luminance by correcting the deviation of the threshold voltage of the thin film transistor, the threshold voltage of the electroluminescent diode, and the voltage on the supply voltage line. Can be. Furthermore, an electroluminescent display device including a panel in which an electroluminescent pixel is arranged according to the present invention also has high quality corresponding to video data by correcting deviations of a threshold voltage of a thin film transistor, a threshold voltage of an electroluminescent diode, and a voltage on a supply voltage line. Can provide an image.

Other objects, other features, and other advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments associated with the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a circuit diagram illustrating in detail an electroluminescent pixel according to an exemplary embodiment of the present invention. Referring to FIG. 5, an electroluminescent pixel according to an exemplary embodiment of the present invention may include a first NMOS transistor MN21 and an electric field connected in series between a first node N11 and a first voltage supply line VL1. A light emitting diode ELD and a second NMOS transistor MN22 connected between the second voltage supply line VL2 and the first node N11 are provided. The low potential voltage VSS is supplied to the first voltage supply line VL1, while the high potential voltage VDD is supplied to the second voltage supply line VL2. The first NMOS transistor MN21 adjusts the amount of current to be supplied to the electroluminescent diode ELD from the first node N1 in response to the voltage on the second node N12. As the voltage on the second node N12 increases, the first NMOS transistor MN21 increases the amount of current flowing through the ELD. The electroluminescent diode ELD emits light corresponding to the amount of current supplied from the first NMOS transistor MN21 so that the flash point is displayed. The second NMOS thin film transistor MN22 selectively connects the first node N11 to the second voltage supply line VL2 according to a logic value of the emission control signal ECS on the emission control line ECL. When the emission control signal ECS maintains the high potential level (ie, high logic) (ie, the emission period Tem), the second NMOS transistor MN22 connects the first connection node N11 to the second voltage supply line. A high potential voltage VDD is supplied to the first node N11 by connecting to a VL2. A current is supplied to the ELD by the high potential voltage VDD supplied to the first node N11, so that the ELD emits light. As a result, the second NMOS thin film transistor MN22 controls the light emission period of the ELD.

The electroluminescent pixel of FIG. 5 is connected between the storage capacitor Cst21, the third node N13, and the third supply voltage line VL3 connected between the second node N12 and the third node N13. A fourth NMOS thin film transistor MN24 connected between a third NMOS thin film transistor MN23, a data line DL, and a third node N13, and a first NMOS thin film transistor MN24 connected between the first and second nodes N11 and N12. A fifth NMOS thin film transistor MN25 is further provided. The third supply voltage line VL3 is supplied to the reference voltage Vref. The third NMOS thin film transistor MN23 selectively connects the storage capacitor Cst21 to the third supply voltage line VL3 according to a logic value of the emission control signal ECS on the emission control line ECL. In detail, the light emission period Tem in which the logic value of the emission control signal ECS maintains a high potential level (ie, high logic), the third NMOS transistor MN23 is turned on, and thus the third node N13. ) Is connected to the third supply voltage line VL3. In this case, the reference voltage Vref on the third supply voltage line VL3 is supplied to the storage capacitor Cst21 via the third NMOS thin film transistor MN23 and the third node N13. Accordingly, the voltage on the second node N12 (that is, the voltage of the gate electrode of the first NMOS transistor MN21) is boosted by the difference voltage between the reference voltage Vref and the storage voltage of the storage capacitor Cst22.

The fourth NMOS thin film transistor MN24 selectively connects the third node N13 to the data line DL according to a logic value of the scan signal SS on the gate line GL. In the pixel voltage write period Tpw at which the scan signal SS maintains a high potential level (ie, high logic), the fourth NMOS thin film transistor MN24 is turned on to connect the third node N13 to the data line. DL). In this case, the pixel driving voltage Vps on the data line DL is stored in the storage capacitor Cst21 via the fourth NMOS thin film transistor MN24 and the third node N13. On the contrary, in the period in which the scan signal SS maintains the low potential level (ie, low logic), the fourth NMOS thin film transistor MN24 is turned off to turn the third node N13 from the data line DL. Isolate electrically.

The fifth NMOS thin film transistor MN25 also selectively connects the second node N12 to the first node N11 according to a logic value of the scan signal SS on the gate line GL. In the pixel voltage write period Tpw at which the scan signal SS maintains a high potential level (ie, high logic), the fifth NMOS thin film transistor MN25 is turned on to turn the second node N12 to the first node. (N11). In this case, the first NMOS thin film transistor MN21 having the gate electrode and the drain electrode commonly connected to the second node N12 operates as a diode. In addition, the first NMOS thin film transistor MN21 acting as a diode forms a series circuit connected between the second node N12 and the first supply voltage line VL1 together with the ELD. Accordingly, the second node N12 has the sum of the threshold voltage Vth-mn21 of the first NMOS thin film transistor MN21, the threshold voltage Vth-eld of the ELD, and the low potential voltage VSS. The voltage Vth_mn21 + Vth_eld + VSS is shown. In addition, a difference voltage Vth_mn21 + Vth_eld + VSS-Vps between the voltage on the second node N12 and the charging voltage Vps of the storage capacitor Cst21 is displayed in the third node N13. As a result, the storage capacitor Cst charges the voltage Vps of the pixel driving signal based on the voltage Vth_mn21 + Vth_eld + VSS on the second node N12 corrected by the fifth NMOS thin film transistor MN25. Done. On the contrary, in the period in which the scan signal SS maintains the low potential level (ie, low logic), the fifth NMOS thin film transistor MN25 is turned off so that the second node N12 is turned off from the first node N11. Isolate electrically. In this case, the first NMOS thin film transistor MN21 performs an operation of controlling the amount of current supplied from the first node N11 to the ELD.

It is assumed that the scan signal SS and the radiation control signal ECS having opposite phases are supplied to the gate line GL and the emission control line ECL connected to the electroluminescent pixels of FIG. 5 as shown in FIG. 6. In this case, the sampling of the pixel driving signal Vps repeats the light emission operation as the electroluminescent pixel of FIG. 5 is changed into a potential level at which the scan signal SS and the emission control signal ECS are opposite to each other. The sampling operation of the pixel drive signal Vps is such that the scan signal SS maintains a high potential level (ie, high logic) while the emission control signal ECS maintains a low potential level (ie, low logic). It is performed in the pixel voltage write period Tpw. On the other hand, the light emission operation is performed in the light emission period Tpw in which the scan signal SS maintains a low potential level (ie, low logic) and the emission control signal ECS maintains a high potential level (ie, high logic). Is performed.

FIG. 7A illustrates the connection state of the electroluminescent pixel of FIG. 5 in the pixel voltage writing period. The second NMOS thin film transistor MN22 in response to the emission control signal ECS having the low potential level is turned off to separate the first supply voltage line VL1 from the first node N11. The third NMOS thin film transistor MN23 is turned off by the radiation control signal ECS having a low potential level to separate the third supply voltage line VL3 from the third node N13. On the other hand, the fourth and fifth NMOS thin film transistors MN24 and MN25 in response to the high potential level scan signal SS are turned on. Accordingly, the data line DL is electrically connected to the charging capacitor Cst21 via the third node N13, and the first NMOS thin film transistor MN21 performs an operation of a diode. The diode operation of the first NMOS thin film transistor MN21 is because the drain electrode and the gate electrode of the first NMOS thin film transistor MN21 are electrically connected by the fifth NMOS thin film transistor MN25. As a result, the storage capacitor Cst21, the first NMOS thin film transistor MN21 acting as a diode, and the electroluminescent diode ELD are connected in series between the data line DL and the second supply voltage line VL2. do. As a result, the ELD is turned off and does not emit light, while the charging capacitor Cst21 charges the pixel driving signal Vps from the data line DL.

  In this case, the low potential voltage VSS at the gate electrode of the first NMOS transistor MN21 (that is, the second node N12), the threshold voltage Vth_eld of the ELD, and the first NMOS thin film transistor MN21. Since the sum voltage (Vth_mn21 + Vth_eld + VSS) of the threshold voltage (Vth_mn21) of V is transferred, the voltage of "Vth_mn21 + Vth_eld + VSS-Vps" is stored in the charging capacitor Cst21. In other words, the charging voltage Vcst21 of the charging capacitor Cst21 becomes as follows.

Vcst21 = Vth_mn21 + Vth_eld + VSS-Vps

FIG. 7B illustrates the connection state of the electroluminescent pixel of FIG. 5 in the light emission period Tem. The fourth and fifth NMOS thin film transistors MN24 and MN25 in response to the scan signal SS of the low potential level are turned off. Accordingly, the data line DL is separated from the charging capacitor Cst21, and the drain electrode and gate electrode of the first NMOS thin film transistor MN21 are also separated from each other.

On the other hand, the second NMOS thin film transistor MN22 responding to the emission control signal ECS having the high potential level is turned on to pass the first supply voltage line VL1 through the first node N11 to the first NMOS thin film transistor. It is electrically connected to the drain electrode of (MN21). The third NMOS thin film transistor MN23 is also turned on by the radiation control signal ECS of the high potential level so that the reference voltage Vref on the third supply voltage line VL3 passes through the third node N13. To be supplied to the charging capacitor Cst21. Accordingly, the first NMOS thin film transistor MN21 performs a current amount control operation, and the ELD also emits light corresponding to the amount of current from the first NMOS thin film transistor MN21.

At this time, the voltage Vg of the gate electrode (that is, the second node N12) of the first NMOS thin film transistor MN21 is boosted by the voltage change amount (− (Vps−Vref)) at the third node N13. Therefore, it becomes as (2).

Vg = Vref-Vps + Vth_mn21 + Vth_eld + VSS

The voltage Vs on the source electrode of the first NMOS thin film transistor MN21 is also determined by the current flowing through the ELD and the threshold voltage Vth_eld of the ELV. Veld (F (Vps)) is increased from the sum voltage as shown in Equation 3.

Vs = Vth_eld + VSS + Veld (F (Vps))

In other words, a voltage Vgs calculated as shown in Equation 4 is applied between the gate electrode and the source electrode of the first NMOS thin film transistor MN21.

Vgs = {Vref-Vps + Vth_mn21 + Vth-eld + VSS}-{Vth_eld + VSS + Veld (F (Vps))}

    = Vref + Vth_mn21-Vps-Veld (F (Vps))

The amount of current flowing through the ELD using the gate-source voltage Vgs of the first NMOS thin film transistor MN21 is calculated as shown in Equation 5 below.

Ield = W / 2L Cox μ · [{Vref + Vth_mn21-Vps-Veld (F (Vps))}-Vth_mn21] ²

= W / 2LCoxμ (Vref-Vps-Veld (F (Vps))} ²

In Equation 5, "W" and "L" are the width and length of the channel of the first NMOS thin film transistor MN21, and "Cox" and "μ" correspond to a constant along with the reference voltage Vref.

As shown in Equation 5, the amount of current flowing through the ELD is only changed according to the voltage of the pixel driving signal Vps. In addition, the amount of light emitted from the ELD also changes only in accordance with the voltage of the pixel driving signal Vps.

As described above, the electroluminescent pixel according to the present invention includes the first NMOS thin film transistor MN21 which is a threshold voltage of the ELD and a thin film transistor for driving the ELD when the pixel driving signal is charged. The pixel driving signal is charged in the charging capacitor Cst21 so as to be corrected by the threshold voltage and the voltage on the supply voltage line, so that the amount of current flowing through the electroluminescent diode ELD during light emission is determined by the pixel driving signal Vps. Only vary with voltage. Accordingly, the electroluminescent pixel according to the present invention allows the amount of emitted light to accurately respond to the voltage of the pixel driving signal. In addition, the electroluminescent panel in which the electroluminescent pixels are arranged in a matrix form also provides an image of uniform luminance by correcting the deviation of the threshold voltage of the thin film transistor, the threshold voltage of the electroluminescent diode, and the voltage on the supply voltage line. Can be. Furthermore, an electroluminescent display device including a panel in which an electroluminescent pixel is arranged according to the present invention also has high quality corresponding to video data by correcting deviations of a threshold voltage of a thin film transistor, a threshold voltage of an electroluminescent diode, and a voltage on a supply voltage line. Can provide an image.

In the electroluminescent pixel, as shown by a dotted line in FIG. 6, the emission control signal ECL in which the end of the enable period overlaps with the start of the enable period (that is, the high logic period) of the scan signal SS. It may be driven by. In this case, a section in which the enable section of the scan signal SS and the enable section of the emission control signal ECS overlap each other is used as the initialization period Tini. This initialization period Tini progresses from the end of the light emission period Tem to the start of the pixel voltage write period Tpw. In this case, all of the second to fifth NMOS transistors MN22 to MN25 in the electroluminescent pixel are turned on. In contrast, the first NMOS transistor MN21 operates as a diode. This is because the drain electrode and the gate electrode of the first NMOS transistor MN21 are electrically connected to each other by the turned-on fourth NMOS transistor MN24. The high potential voltage VDD on the second supply voltage line VL2 is supplied to the second node N11 via the second NMOS transistor MN22. In the first node N11, the sum voltage VSS + Vth_eld + Vth_mn21 of the low potential voltage VSS, the threshold voltage Vth_eld of the ELD, and the threshold voltage Vth_mn21 of the first NMOS transistor MN21. Higher voltage). Accordingly, the voltage charged on the first node N11 includes the low potential voltage VSS, the threshold voltage Vth_eld of the ELD, and the first NMOS transistor MN21 in the pixel voltage write period Tpw. The sum voltage (VSS + Vth_eld + Vth_mn21) of the threshold voltage (Vth_mn21) of Nm is correctly charged to the second node N12. As a result, in the electroluminescent pixel, variations and deviations of the threshold voltage Vth_eld of the electroluminescent diode ELD, the threshold voltage Vth_mn21 of the driving first NMOS thin film transistor MN21 and the low potential voltage VSS are further increased. Ensure correct calibration

8 is a circuit diagram illustrating in detail an electroluminescent pixel according to another exemplary embodiment of the present invention. Referring to FIG. 8, an electroluminescent pixel according to another exemplary embodiment of the present invention includes an ELD and a first PMOS transistor connected in series between a first node N11 and a first voltage supply line VL1. And a second PMOS transistor MP22 connected between the second voltage supply line VL2 and the first node N11. The high potential voltage VDD is supplied to the first voltage supply line VL1, while the low potential voltage VSS is supplied to the second voltage supply line VL2. The first PMOS transistor MP21 responds to the voltage on the second node N12 (more specifically, the voltage difference between the voltage on its source electrode and the voltage on the second node N12). Adjust the amount of current flowing in the ELD). As the voltage on the second node N12 is increased, the first PMOS transistor MP21 reduces the amount of current flowing through the ELD. The ELD emits light in an amount corresponding to the amount of current controlled by the first PMOS transistor MP21 so that the flash point is displayed. The second PMOS thin film transistor MP22 selectively connects the first node N11 to the second voltage supply line VL2 according to a logic value of the emission control signal / ECS on the emission control line ECL. When the emission control signal / ECS is enabled at the low potential level (ie, low logic) (ie, the radiation period Tem), the second PMOS transistor MP22 causes the first connection node N11 to turn on the second voltage. It is connected to the supply line VL2 so that the W low potential voltage VSS is supplied to the first node N11. As the first node N11 is connected to the low potential voltage VSS, a current path of the ELD is formed, and the ELD emits light. As a result, the second PMOS thin film transistor MP22 controls the light emission period of the ELD.

The electroluminescent pixel of FIG. 8 is connected between a storage capacitor Cst22, a third node N13 and a third supply voltage line VL3 connected between the second node N12 and the third node N13. The fourth PMOS thin film transistor MP24 connected between the third PMOS thin film transistor MP23, the data line DL, and the third node N13, and the first and second nodes N11 and N12. A fifth PMOS thin film transistor MP25 is further provided. The third supply voltage line VL3 is supplied to the reference voltage Vref. The third PMOS thin film transistor MP23 selectively connects the storage capacitor Cst22 to the third supply voltage line VL3 according to a logic value of the emission control signal / ECS on the emission control line ECL. In detail, in the light emission period Tem in which the emission control signal / ECS is enabled at the low potential level (that is, low logic), the third PMOS transistor MP23 is turned on so that the third node N13 is turned on. ) Is connected to the third supply voltage line VL3. In this case, the reference voltage Vref on the third supply voltage line VL3 is supplied to the storage capacitor Cst22 via the third PMOS thin film transistor MP23 and the third node N13. Accordingly, the voltage on the second node N12 (that is, the voltage of the gate electrode of the first PMOS transistor MP21) is boosted by the difference voltage between the reference voltage Vref and the storage voltage of the storage capacitor Cst22.

The fourth PMOS thin film transistor MP24 selectively connects the third node N13 to the data line DL according to a logic value of the scan signal / SS on the gate line GL. In the pixel voltage write period Tpw at which the scan signal / SS maintains the low potential level (ie, low logic), the fourth PMOS thin film transistor MP24 is turned on to turn on the third node N13. To (DL). In this case, the pixel driving voltage Vps on the data line DL is stored in the storage capacitor Cst22 via the fourth NMOS thin film transistor MN24 and the third node N13. On the contrary, in the period in which the scan signal / SS is disabled to the high potential level (ie, high logic) (that is, in the light emission period), the fourth PMOS thin film transistor MP24 is turned off so that the third node N13 is turned off. ) Is electrically isolated from the data line DL.

The fifth PMOS thin film transistor MP25 also selectively connects the second node N12 to the first node N11 according to a logic value of the scan signal / SS on the gate line GL. In the pixel voltage write period Tpw at which the scan signal / SS maintains the low potential level (ie, low logic), the fifth PMOS thin film transistor MP25 is turned on to turn the second node N12 first. The node N11 is connected. In this case, the first PMOS thin film transistor MP21 having the gate electrode and the drain electrode commonly connected to the second node N12 operates as a diode. In addition, the first PMOS thin film transistor MP21, which operates as a diode, forms a series circuit connected between the second node N12 and the first supply voltage line VL1 together with the ELD. Accordingly, the second node N12 has a high potential voltage reduced by the sum of the threshold voltage Vth-mp21 of the first PMOS thin film transistor MP21 and the threshold voltage Vth-eld of the ELD. VDD-Vth_mp21-Vth_eld) appears. In addition, a difference voltage VDD-Vth_mp21-Vth_eld-Vps between the voltage on the second node N12 and the charging voltage Vps of the storage capacitor Cst22 is displayed at the third node N13. As a result, the storage capacitor Cst22 charges the voltage Vps of the pixel driving signal based on the voltage VDD-Vth_mp21-Vth_eld on the second node N12 corrected by the fifth PMOS thin film transistor MP25. Done. On the contrary, in the period in which the scan signal / SS is disabled to the high potential level (ie, high logic) (that is, in the light emission period Tem), the fifth PMOS thin film transistor MP25 is turned off so that the fifth PMOS thin film transistor MP25 is turned off. The two nodes N12 are electrically disconnected from the first node N11. In this case, the first PMOS thin film transistor MP21 controls the amount of current flowing from the ELD toward the first node N11.

Assume that the scan signal / SS and the radiation control signal / ECS having opposite phases are supplied to the gate line GL and the emission control line ECL connected to the electroluminescent pixels of FIG. 8 as shown in FIG. 9. . In this case, the electroluminescent pixel of FIG. 8 alternately-repeats the sampling operation and the light emission operation of the pixel driving signal Vps as the scan signal / SS and the emission control signal / ECS are changed to opposite potential levels. do. The sampling operation of the pixel drive signal Vps allows the scan signal / SS to be enabled at a low potential level (ie low logic) while the emission control signal / ECS is at a high potential level (ie high logic). Is performed in the pixel voltage write period Tpw, which is disabled. Light emission operation is such that the scan signal (/ SS) is disabled at a high potential level (ie, high logic) while the emission control signal (/ ECS) is enabled at a low potential level (ie, low logic). It is carried out in the spinning period Tem.

FIG. 10A illustrates the connection state of the electroluminescent pixel of FIG. 8 in the pixel voltage write period Tpw. The second PMOS thin film transistor MP22 responsive to the radiation control signal / ECS of the high potential level is turned off to separate the second supply voltage line VL2 from the first node N11. The third PMOS thin film transistor MP23 is also turned off by the high potential level radiation control signal / ECS to separate the third supply voltage line VL3 from the third node N13. On the other hand, the fourth and fifth PMOS thin film transistors MP24 and MP25 responding to the scan signal / SS of the low potential level are turned on. Accordingly, the data line DL is electrically connected to the charging capacitor Cst22 via the third node N13, and the first PMOS thin film transistor MP21 performs an operation of a diode. The diode operation of the first PMOS thin film transistor MP21 is because the drain electrode and the gate electrode of the first PMOS thin film transistor MP21 are electrically connected to each other by the fifth PMOS thin film transistor MP25. As a result, the storage capacitor Cst22, the first PMOS thin film transistor MP21 acting as a diode, and the electroluminescent diode ELD are connected in series between the data line DL and the first supply voltage line VL1. do. As a result, the ELD is turned off and does not emit light, while the charging capacitor Cst22 charges the pixel driving signal Vps from the data line DL.

  At this time, the threshold voltage Vth_eld of the EL LED and the threshold voltage Vth_mp21 of the first PMOS thin film transistor MP21 are applied to the gate electrode of the first PMOS transistor MP21 (that is, the second node N12). Since the high potential voltage VDD-Vth_mp21-Vth_eld reduced by the sum of the voltages is transferred, the voltage of "VDD-Vth_mp21-Vth_eld-Vps" is stored in the charging capacitor Cst22. In other words, the charging voltage Vcst22 of the charging capacitor Cst22 is expressed by Equation (6).

Vcst22 = VDD-Vth_mp21-Vth_eld-Vps

FIG. 10B illustrates the connection state of the electroluminescent pixel of FIG. 8 in the light emission period Tem. The fourth and fifth PMOS thin film transistors MP24 and MP25 in response to the high potential level scan signal / SS are turned off. Accordingly, the data line DL is separated from the charging capacitor Cst22, and the drain electrode and the gate electrode of the first PMOS thin film transistor MP21 are also separated from each other.

On the other hand, the second PMOS thin film transistor MP22 in response to the emission control signal / ECS at the low potential level is turned on so that the second supply voltage line VL2 is passed through the first node N11 to the first PMOS thin film. It is electrically connected to the drain electrode of the transistor MP21. The third PMOS thin film transistor MP23 is also turned on by the radiation control signal / ECS of the low potential level so that the reference voltage Vref on the third supply voltage line VL3 receives the third node N13. To be supplied to the charging capacitor Cst22. Accordingly, the first PMOS thin film transistor MP21 performs an amount of current control operation, and the ELD also emits light corresponding to the amount of current controlled by the first PMOS thin film transistor MP21.

At this time, the voltage Vg of the gate electrode (that is, the second node N12) of the first PMOS thin film transistor MP21 is boosted by the voltage change amount ((-Vps −Vref)) at the third node N13. Therefore, it becomes as (Equation 7).

Vg = VDD-Vref-Vps-Vth_mp21-Vth_eld

The voltage Vs on the source electrode of the first PMOS thin film transistor MP21 is also caused by the current flowing through the ELD to the threshold voltage Vth_eld of the EL from the high potential voltage VDD. The voltage level decreased by Veld (F (Vps)). The voltage Vs on the source electrode of the first PMOS thin film transistor MP21 is calculated as shown in Equation (8).

Vs = VDD-Vth_eld-Veld (F (Vps)

In other words, a voltage Vgs calculated as shown in Equation 9 is applied between the gate electrode and the source electrode of the first PMOS thin film transistor MP21.

Vgs = {VDD-Vth_eld-Veld (F (Vps))}-{VDD-Vref-Vps-Vth_mp21-Vth-eld}

    = Vref + Vth_mp21 + Vps-Veld (F (Vps))

The amount of current flowing through the ELD using the gate-source voltage Vgs of the first PMOS thin film transistor MP21 is calculated as shown in Equation 5 below.

Ield = W / 2L Cox μ · [{Vref + Vth_mp21 + Vps-Veld (F (Vps))}-Vth_mn21] ²

= W / 2LCoxμ (Vref + Vps-Veld (F (Vps))} ²

In Equation 10, "W" and "L" are the width and length of the channel of the first NMOS thin film transistor MN21, and "Cox" and "μ" are ~~~ and ~~~ as reference voltages Vref. ) And a constant.

As shown in Equation 10, the amount of current flowing through the ELD is only changed according to the voltage of the pixel driving signal Vps. In addition, the amount of light emitted from the ELD also changes only in accordance with the voltage of the pixel driving signal Vps.

As described above, the electroluminescent pixel according to the present invention includes the threshold voltage of the ELD and the first PMOS thin film transistor MP21 which is a thin film transistor for driving the ELD when the pixel driving signal is charged. The pixel driving signal is charged in the charging capacitor Cst22 so as to be corrected by the threshold voltage and the voltage on the supply voltage line, so that the amount of current flowing through the electroluminescent diode ELD during light emission is applied to the voltage of the pixel driving signal Vps. So only make it variable. Accordingly, the electroluminescent pixel according to the present invention allows the amount of emitted light to accurately respond to the voltage of the pixel driving signal. In addition, the electroluminescent panel in which the electroluminescent pixels are arranged in a matrix form also provides an image of uniform luminance by correcting the deviation of the threshold voltage of the thin film transistor, the threshold voltage of the electroluminescent diode, and the voltage on the supply voltage line. Can be. Furthermore, an electroluminescent display device including a panel in which an electroluminescent pixel is arranged according to the present invention also has high quality corresponding to video data by correcting deviations of a threshold voltage of a thin film transistor, a threshold voltage of an electroluminescent diode, and a voltage on a supply voltage line. Can provide an image.

In the electroluminescent pixel, as shown by a dotted line in FIG. 9, the emission control signal (/) in which the end of the enable period overlaps with the start of the enable period (that is, the low logic period) of the scan signal / SS May be driven by ECS). In this case, a section in which the enable section of the scan signal / SS and the enable section of the radiation control signal / ECS overlap each other is used as the initialization period Tini. This initialization period Tini progresses from the end of the light emission period Tem to the start of the pixel voltage write period Tpw. In this case, all of the second to fifth PMOS transistors MP22 to MP25 in the electroluminescent pixel are turned on. In contrast, the first PMOS transistor MP21 operates as a diode. This is because the drain electrode and the gate electrode of the first PMOS transistor MP21 are electrically connected to each other by the turned-on fifth PMOS transistor MP25. The low potential voltage VSS on the second supply voltage line VL2 is supplied to the second node N11 via the second PMOS transistor MP22. The first node N11 is charged with a voltage significantly lower than the sum voltage Vth_eld + Vth_mp21 of the threshold voltage Vth_eld of the ELD and the threshold voltage Vth_mn21 of the first PMOS transistor MP21. do. Thus, the low potential voltage VSS charged on the first node N11 has the threshold voltage Vth_eld and the first PMOS of the ELD from the high potential voltage VDD in the pixel voltage write period Tpw. The voltage VDD-Vth_eld-Vth_mp21 reduced by the sum voltage of the threshold voltage Vth_mp21 of the transistor MP21 is accurately charged in the second node N12. As a result, in the electroluminescent pixel, variations and deviations of the threshold voltage Vth_eld of the electroluminescent diode ELD, the threshold voltage Vth_mp21 and the high potential voltage VDD of the first driving PMOS thin film transistor MP21 are further increased. Ensure correct calibration

11 is a block diagram schematically illustrating an EL display device according to an exemplary embodiment. Referring to FIG. 11, an electroluminescent display according to an exemplary embodiment of the present invention includes a gate driver 12 driving n gate lines (or scan lines) GL1 to GLn on the electroluminescent panel 10; A data driver 14 for driving m data lines (or source lines) DL1 to DLm on the electroluminescent panel 10; And a radiation line driver 16 for driving n radiation control lines on the electroluminescent panel 10. In addition, the electroluminescent display includes a voltage generator 18 for generating a high potential voltage VDD, a low potential voltage VSS, and a reference voltage Vref required for the electroluminescent panel 10; And a timing controller 20 for controlling the operation timing of the gate driver 12, the data driver 14, and the radiation line driver 16. The EL panel 10 is divided into m * n unit regions by n pairs of gate lines GL1 to GLn, emission control lines ECL1 to ECLn, and m data lines DL1 to DLm. In each of the unit regions, an electroluminescent pixel having a configuration as shown in FIG. 5 or 8 is formed.

The gate driver 12 has a plurality of gate lines GL1 to GLn on the electroluminescent panel 10 sequentially each frame (for example, a period of a horizontal synchronization signal) every frame (period of one vertical synchronization signal). Generates n scan signals SS1 to SSn or / SS1 to / SSn to be enabled. The n scan signals SS1 to SSn or / SS1 to / SSn each have a pulse of high potential level (or low potential level) which is sequentially shifted by a predetermined period of time (that is, a period of one horizontal synchronization signal). In order to generate these n scan signals SS1 to SSn or / SS1 to / SSn, the gate driver 12 responds to the gate control signal GCS. The gate control signal GCS includes at least one gate clock signal swinging at a period of a gate start pulse and a horizontal synchronization signal generated at the time of the frame.

Whenever one of the plurality of gate lines GL1 to GLn is enabled (that is, every period of the horizontal synchronization signal), the data driver 14 includes m data lines DL1 to 1 on the electroluminescent panel 10. A pixel drive signal for one line to be supplied to DLm) is generated. For this purpose, the data driver 14 inputs the pixel data stream VDr for one line in response to the data control signal DCS. The pixel data VDr for one line is converted into pixel drive signals Vps in an analog form by the data driver 14. The m pixel driving signals Vps thus converted are output to m data lines DL1 to DLm on the EL panel 10 through m output channels of the data driver 14.

The radiation line driver 16 has a period in which n emission control lines ECL1 to ECLn on the electroluminescent panel 10 are sequentially fixed every frame (period of one vertical synchronizing signal), for example, a period of the horizontal synchronizing signal. N emission control signals (ECS1 to ECSn or / ECS1 to / ECSn) are generated. By these n emission control signals ECS1 to ECSn or / ECS1 to / ECSn, the n emission control lines ECL1 to ECLn on the electroluminescent panel 10 have corresponding gate lines GL1 to GLn. Disabled while enabled. Accordingly, these n emission control signals (ECS1 to ECSn or / ECS1 to / ECSn) are of low potential level (or high potential level) which are sequentially shifted by a certain period of time (ie, one horizontal synchronization signal). Each has a pulse. In order to generate the n emission control signals ECS1 to ECSn or / ECS1 to / ECSn, the radiation line driver 16 responds to the gate control signal GCS like the gate driver 12. Each of the electroluminescent pixels on the electroluminescent panel 10 is represented by n pairs of gate signals SS1 to SSn or / SS1 to / SSn and emission control signals ECL1 to ECLn or / ECL1 to / ECLn. Alternatively, as illustrated in FIG. 8, the sampling operation of the pixel voltage in the pixel voltage write period Tpw and the light emission operation in the light emission period Tem are alternately repeated.

On the contrary, the radiation line driver 16 has a period (e.g., horizontal) in which n emission control lines ECL1 to ECLn on the electroluminescent panel 10 are sequentially fixed every frame (period of one vertical synchronization signal). N emission control signals (ECS1 to ECSn or / ECS1 to / ECSn) which are disabled after each period, but are disabled after a period of time from the start of the enable period of the corresponding gate lines GL1 to GLn. Occurs. By these n emission control signals ECS1 to ECSn or / ECS1 to / ECSn, the n emission control lines ECL1 to ECLn on the electroluminescent panel 10 have corresponding gate lines GL1 to GLn. It is disabled for the rest of the enabled period except for a certain period from the beginning. Accordingly, these n emission control signals (ECS1 to ECSn or / ECS1 to / ECSn) are low potential levels (or high potentials) which are sequentially shifted by a certain period of time (i.e., less than a period of one horizontal synchronizing signal). Level) pulses, respectively. Each of the electroluminescent pixels on the electroluminescent panel 10 is represented by n pairs of gate signals SS1 to SSn or / SS1 to / SSn and emission control signals ECL1 to ECLn or / ECL1 to / ECLn. Alternatively, as shown by a dotted line in FIG. 8, in the initialization period Tini, the voltage on the gate electrode of the first thin film transistor MN21 or MP21 is initialized higher than the sum of the threshold voltages or close to the low potential voltage VSS. The operation, the sampling operation of the pixel voltage in the pixel voltage write period Tpw, and the light emission operation in the light emission period Tem are cyclically repeated.

The voltage generator 18 generates the low potential voltage VSS, the reference voltage Vref, and the high potential voltage VDD required for each of the electroluminescent pixels on the electroluminescent panel 10. In addition, the voltage generator 18 supplies the low potential voltage VSS, the reference voltage Vref, and the high potential voltage VDD to each of the electroluminescent pixels on the electroluminescent panel 10. The reference voltage Vref has a voltage level approaching the high potential voltage VDD when the electroluminescent pixels on the electroluminescent panel 10 are configured as shown in FIG. 5. In this case, the reference voltage Vref preferably has a voltage level corresponding to 90% to 98% of the potential difference between the high potential voltage VDD and the low potential voltage VSS. In contrast, when the electroluminescent pixels on the electroluminescent panel 10 are configured as shown in FIG. 8, the reference voltage Vref has a voltage level approaching the low potential voltage VSS. In this case, the reference voltage Vref preferably has a voltage level corresponding to 0.02% to 0.10% of the potential difference between the high potential voltage VDD and the low potential voltage VSS.

The timing controller 20 is the gate control signals GCS and data control signals described above, which use synchronization signals SYNC from an external system (e.g., the computer system is an image demodulation module of a graphics module or television receiver). (DCS) occurs. In addition, the timing controller 16 may input the pixel data VDf in units of frames from an external system. The pixel data in the frame unit is rearranged to the pixel data VDr by one line. The rearranged pixel data VDr for each line is supplied to the data driver 14.

Thus, the EL display device according to the present invention can provide a high-quality image corresponding to the image of the uniform brightness and the video data by correcting the deviation of the threshold voltage of the thin film transistor, the threshold voltage of the EL and the voltage on the supply voltage line. Can be.

As described above, the embodiments of the present invention have been described with reference to FIGS. 5, 8, and 11, but a person having ordinary knowledge in the technical field to which the present invention belongs should not depart from the spirit and scope of the present invention. It will be apparent that various modifications, changes, and equivalent other embodiments are possible. Accordingly, the technical scope and features of the present invention should not be limited to the description of the embodiments, but should be set by the matters set forth in the appended claims.

1 is a circuit diagram illustrating an electroluminescent pixel of the related art.

FIG. 2 is a timing chart illustrating operation timings of the electroluminescent pixel of FIG. 1.

3 is a circuit diagram illustrating an electroluminescent pixel of the related art.

4 is a timing chart illustrating an operation timing of the electroluminescent pixel of FIG. 3.

5 is a circuit diagram illustrating an electroluminescent pixel according to an exemplary embodiment of the present invention.

6 is a timing chart for explaining the operation timing of the electroluminescent pixels shown in FIG. 5.

7A and 7B are equivalent circuit diagrams illustrating a connection state for each operation process of FIG. 5.

8 is a circuit diagram illustrating an electroluminescent pixel according to another exemplary embodiment of the present invention.

FIG. 9 is a timing chart illustrating an operation process of the electroluminescent pixel of FIG. 8.

10A and 10B are equivalent circuit diagrams illustrating a connection state for each operation process of FIG. 8.

11 is a block diagram illustrating an electroluminescent display according to an exemplary embodiment of the present invention.

≪A brief description of the main parts of the drawings≫

10 electroluminescent panel 12 gate driver

14: Data Driver 16: Radiation Line Driver

18: voltage generator 20: timing controller

Cst11 ~ Cst22: Storage Capacitor ELD: Light Emitting Diode

MN11, MN12, MN21 ~ MN15: NMOS Thin Film Transistor

MP11, MP12, MP21 ~ MP25: PMOS Thin Film Transistor

Claims (17)

A first thin film transistor for controlling an amount of current flowing through the electroluminescent diode connected to the first supply voltage line; A capacitor storing a control voltage supplied to a gate electrode of the first thin film transistor; A second thin film transistor configured to store a pixel driving signal on a data line in the capacitor in response to a scan signal; A third thin film transistor configured to charge the capacitor with a difference voltage and a sum voltage of the threshold voltage of the EL, the threshold voltage of the first thin film transistor, and the supply voltage on the first supply voltage line, in response to the scan signal; And an electroluminescent pixel. The electroluminescent pixel according to claim 1, further comprising a second supply voltage line for supplying a second supply voltage to the first thin film transistor. The method of claim 2, And a fourth thin film transistor which is driven complementarily with the second thin film transistor in response to a radiation control signal to selectively supply a reference voltage on a third supply voltage line to the capacitor. Pixel. The method of claim 3, wherein And a fifth thin film transistor for selectively electro-connecting a drain electrode of the first thin film transistor to its gate electrode in response to the emission control signal. The method of claim 4, wherein A low potential voltage is supplied to the first supply voltage line, And a high potential voltage is supplied to the second supply voltage line. In claim 5, And the first to fifth thin film transistors are NMOS thin film transistors. The method of claim 4, wherein A high potential voltage is supplied to the first supply voltage line, And a low potential voltage is supplied to the second supply voltage line. In claim 7, And the first to fifth thin film transistors are PMOS thin film transistors. A plurality of pairs of gate lines and radiation control lines; A plurality of data lines; A first thin film transistor and a first thin film for controlling an amount of current flowing through an electroluminescent diode connected to a first supply voltage line in each of the regions divided by the plurality of pairs of gate lines and emission control lines and the plurality of data lines A capacitor for storing a control voltage supplied to a gate electrode of a transistor; a second thin film transistor for storing a pixel driving signal on the data line in the capacitor in response to a scan signal on the gate line; and a scan signal on the gate line. An electric field including a third thin film transistor configured to charge the capacitor in response to a difference and a sum voltage of the threshold voltage of the EL, the threshold voltage of the first thin film transistor, and the supply voltage on the first supply voltage line. Electrochemical device comprising light emitting pixel Luminous panel. 10. The device of claim 9, wherein the electroluminescent pixel is And a second supply voltage line for supplying a second supply voltage to the first thin film transistor. The method of claim 10, wherein the electroluminescent pixel And a fourth thin film transistor which is driven complementarily with the second thin film transistor in response to the emission control signal to selectively supply a reference voltage on a third supply voltage line to the capacitor. Luminous panel. 12. The device of claim 11, wherein the electroluminescent pixel is And a fifth thin film transistor for selectively electro-connecting a drain electrode of the first thin film transistor to a gate electrode thereof in response to the emission control signal. The amount of current flowing through the electroluminescent diode connected to the first supply voltage line in each of the regions divided by the plurality of pairs of gate lines, the plurality of data lines, the plurality of gate lines and the radiation control line, and the plurality of data lines. A first thin film transistor for controlling a voltage, a capacitor for storing a control voltage supplied to a gate electrode of the first thin film transistor, and a second pixel for storing a pixel driving signal on the data line in response to a scan signal on the gate line. In response to the scan signal on the gate line, a difference and a sum voltage of the threshold voltage of the electroluminescent diode, the threshold voltage of the first thin film transistor, and the supply voltage on the first supply voltage line are supplied to the capacitor. Electric field generation comprising a third thin film transistor to charge the capacitor An electroluminescent panel having optical pixels; A gate driver for driving gate lines on the electroluminescent panel; A radiation line driver for driving radiation control lines on the electroluminescent panel in any one of a form complementary to and partially overlapping with the gate lines; And And a data driver supplying a pixel driving voltage to data lines on the electroluminescent panel. The pixel of claim 13, wherein the electroluminescent pixel is And a second supply voltage line for supplying a second supply voltage to the first thin film transistor. 15. The device of claim 14, wherein the electroluminescent pixel is And a fourth thin film transistor which is driven complementarily with the second thin film transistor in response to the emission control signal to selectively supply a reference voltage on a third supply voltage line to the capacitor. Luminous panel. 16. The electroluminescent pixel of claim 15, wherein And a fifth thin film transistor for selectively electro-connecting a drain electrode of the first thin film transistor to a gate electrode thereof in response to the emission control signal. Controlling the amount of current flowing in the electroluminescent diode connected to the supply voltage line in each of the regions divided by the plurality of gate lines, the plurality of data lines, the plurality of gate lines and the radiation control line, and the plurality of data lines. A driving method of an electroluminescent display device displaying an image on an electroluminescent panel comprising a thin film transistor and a electroluminescent pixel comprising a capacitor for storing a control voltage supplied to a gate electrode of a first thin film transistor. Supplying pixel driving voltages on the data lines on the electroluminescent panel; The gate line on the electroluminescent panel is sequentially-enabled so that each of the electroluminescent pixels is combined with either the sum of the threshold voltages of the thin film transistor and the electroluminescent diode and the sum of the voltage on the supply voltage line and the difference voltage. Causing a pixel driving voltage to charge each of the capacitors of the electroluminescent pixel; And And sequentially disabling the gate line on the electroluminescent panel so that each of the electroluminescent pixels emits light according to a voltage stored in a capacitor.

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