CN116129805A

CN116129805A - Pixel circuit, driving method thereof, display panel and display device

Info

Publication number: CN116129805A
Application number: CN202211641521.6A
Authority: CN
Inventors: 王丽
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-12-20
Filing date: 2022-12-20
Publication date: 2023-05-16

Abstract

A pixel circuit, a driving method thereof, a display panel and a display device are provided, and belong to the technical field of display. The pixel circuit comprises a light-emitting control circuit, a driving circuit and a negative feedback circuit. Wherein the light emission control circuit is capable of controlling the potential of each of the first to fourth nodes in the pixel circuit. The driving circuit can control the potential of the third node based on the potentials of the first node and the second node. When the third node and the fourth node are turned on, the light emitting element can emit light based on the potential of the third node. The negative feedback circuit can adjust the potential of the first node based on the potential of the target node in the third node and the fourth node, so that the potential of the first node and the potential of the target node are changed identically, and further the driving circuit can control the potential of the third node based on the adjusted potential of the first node, so that the light-emitting element can be reliably driven to emit light, and the display effect of the display panel can be ensured to be better.

Description

Pixel circuit, driving method thereof, display panel and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a pixel circuit, a driving method thereof, a display panel and a display device.

Background

Organic light-emitting diode (OLED) display panels are widely used in various display devices due to their self-luminescence, fast response speed, low energy consumption, and the like.

In the related art, an OLED display panel generally includes: a substrate, and a plurality of pixels located on the substrate. Each pixel includes a pixel circuit and a light emitting element. The pixel circuit includes a driving transistor, and is coupled to a plurality of signal terminals (e.g., gate signal terminals) and the light emitting element, respectively. The pixel circuit is used for generating driving current through the driving transistor and transmitting the driving current to the light-emitting element based on signals provided by the plurality of signal terminals so as to drive the light-emitting element to emit light, and therefore the OLED display panel can display pictures required to be displayed.

However, the driving current transmitted to the light emitting element by the pixel circuit is changed due to the bias state of the driving transistor (e.g., the negative bias state of the P-type transistor) in the pixel circuit, so that the light emitting element cannot emit light reliably, and the display effect of the OLED display panel is poor.

Disclosure of Invention

The technical scheme is as follows:

In one aspect, there is provided a pixel circuit including:

the light-emitting control circuit is respectively coupled with a grid signal end, a reset signal end, a light-emitting control signal end, a data signal end, an initial power end, a first node, a second node, a third node and a fourth node, and is used for controlling the on-off of the data signal end and the second node, the on-off of the initial power end and the fourth node, the on-off of the third node and the first node, the on-off of the initial power end and the second node, and the on-off of the third node and the fourth node, and the on-off of the first power end and the second node, and the on-off of the third node and the fourth node, respectively, in response to the light-emitting control signal provided by the light-emitting control signal end.

A driving circuit coupled to the first node, the second node, and the third node, respectively, for controlling a potential of the third node based on a potential of the first node and a potential of the second node;

And the negative feedback circuit is coupled with the first node, is also coupled with a target node in the fourth node and the third node, and is used for adjusting the potential of the first node based on the potential of the target node, the fourth node is also used for being coupled with a first pole of a light emitting element, a second pole of the light emitting element is also coupled with a second power supply end, and the light emitting element is used for emitting light based on the potential of the first pole and the potential of the second pole.

Optionally, the negative feedback circuit includes: and a coupling element for adjusting the potential of the first node based on the potential of the target node by having a coupling effect.

Optionally, the coupling element package: and one end of the coupling capacitor is coupled with the target node, and the other end of the coupling capacitor is coupled with the first node.

Optionally, the target node is the fourth node.

Optionally, the driving circuit includes: a driving transistor;

the gate of the driving transistor is coupled to the first node, the first pole of the driving transistor is coupled to the second node, and the second pole of the driving transistor is coupled to the third node.

Optionally, the driving transistor is a P-type transistor.

Optionally, the light-emitting control circuit is further configured to adjust a potential of the first node based on a first power signal provided by the first power terminal; the light emission control circuit includes:

the data writing sub-circuit is respectively coupled with the grid signal end, the data signal end and the second node and is used for responding to the grid driving signal and controlling the on-off of the data signal end and the second node;

the compensation sub-circuit is respectively coupled with the gate signal end, the third node and the first node and is used for responding to the gate driving signal and controlling the on-off of the third node and the first node;

the reset sub-circuit is respectively coupled with the grid signal end, the reset signal end, the initial power end, the first node and the fourth node, and is used for controlling the on-off of the initial power end and the fourth node in response to the grid driving signal and controlling the on-off of the initial power end and the first node in response to the reset signal;

the light-emitting control sub-circuit is respectively coupled with the light-emitting control signal end, the first power end, the second node, the third node and the fourth node and is used for responding to the light-emitting control signal, controlling the on-off of the first power end and the second node and controlling the on-off of the third node and the fourth node;

And the regulating sub-circuit is respectively coupled with the first power supply end and the first node and is used for regulating the potential of the first node based on the first power supply signal.

Optionally, the data writing sub-circuit includes: a data writing transistor; the compensation sub-circuit includes: a compensation transistor; the reset sub-circuit includes: a first reset transistor and a second reset transistor; the light emission control sub-circuit includes: a first light emission control transistor and a second light emission control transistor; the conditioning sub-circuit includes: a storage capacitor;

the grid electrode of the data writing transistor is coupled with the grid electrode signal end, the first electrode of the data writing transistor is coupled with the data signal end, and the second electrode of the data writing transistor is coupled with the second node;

the grid electrode of the compensation transistor is coupled with the grid electrode signal end, the first electrode of the compensation transistor is coupled with the third node, and the second electrode of the compensation transistor is coupled with the first node;

the grid electrode of the first reset transistor is coupled with the reset signal end, the first pole of the first reset transistor is coupled with the initial power end, and the second pole of the first reset transistor is coupled with the first node;

A gate of the second reset transistor is coupled to the gate signal terminal, a first pole of the second reset transistor is coupled to the initial power terminal, and a second pole of the second reset transistor is coupled to the fourth node;

the grid electrode of the first light-emitting control transistor is coupled with the light-emitting control signal end, the first electrode of the first light-emitting control transistor is coupled with the first power end, and the second electrode of the first light-emitting control transistor is coupled with the second node;

the grid electrode of the second light-emitting control transistor is coupled with the light-emitting control signal end, the first electrode of the second light-emitting control transistor is coupled with the third node, and the second electrode of the second light-emitting control transistor is coupled with the fourth node;

one end of the storage capacitor is coupled with the first power supply end, and the other end of the storage capacitor is coupled with the first node.

Optionally, the data writing transistor, the first light emitting control transistor, the second light emitting control transistor and the second reset transistor are P-type transistors; the first reset transistor and the compensation transistor are both N-type transistors;

Wherein, the gate signal terminal includes: a first gate signal terminal and a second gate signal terminal which are different in potential of the supplied gate driving signal; the initial power supply terminal comprises: a first initial power supply terminal and a second initial power supply terminal which are different in potential of the initial power supply signal are provided;

the grid electrode of the data writing transistor and the grid electrode of the second reset transistor are coupled with the first grid electrode signal end, and the grid electrode of the compensation transistor is coupled with the second grid electrode signal end;

the first pole of the first reset transistor is coupled to the first initial power supply terminal, and the second pole of the second reset transistor is coupled to the second initial power supply terminal.

Optionally, in the pixel circuit, an active layer material of the P-type transistor includes: a low temperature polysilicon material; the active layer material of the N-type transistor comprises: an oxide material.

In another aspect, there is provided a driving method of a pixel circuit, applied to the pixel circuit as described in the above aspect, the method comprising:

the first stage, the luminous control circuit responds to the reset signal provided by the reset signal end to control the connection between the initial power end and the first node;

the second stage, the said luminescent control circuit responds to the gate driving signal that the signal end of the gate provides, control the said initial power end to turn on with the fourth node, control the data signal end to turn on with the second node, and control the third node to turn on with the said first node;

A third stage, in which the light emission control circuit responds to a light emission control signal provided by a light emission control signal end, controls the first power end to be conducted with the second node, controls the third node to be conducted with the fourth node, and controls the potential of the third node based on the potential of the first node and the potential of the second node, so that the light emitting element emits light based on the potentials of the first pole and the second pole of the light emitting element;

a fourth stage in which a negative feedback circuit adjusts the potential of the first node based on the potential of a target node in the third node and the fourth node so that the potential change of the first node is the same as the potential change of the target node;

wherein the first, second and third phases are located in a refresh frame and the fourth phase is located in a hold frame following the refresh frame.

Optionally, the negative feedback circuit adjusts the potential of the first node based on the potential of the target node in the third node and the fourth node, including:

the negative feedback circuit adjusts the potential of the first node based on the potential of the target node in the third node and the fourth node by having a coupling function.

In still another aspect, there is provided a display panel including: a substrate, and a plurality of pixels on the substrate;

wherein at least one pixel comprises: a light emitting element, and a pixel circuit as described in the above aspect, the pixel circuit being coupled to the light emitting element and configured to drive the light emitting element to emit light.

In still another aspect, there is provided a display device including: a signal supply circuit and a display panel as described in the above aspects;

the signal providing circuit is coupled with each signal terminal of the pixel coupling in the display panel and is used for providing a signal to each signal terminal.

In summary, the beneficial effects brought by the technical solution provided by the embodiments of the present disclosure at least may include:

a pixel circuit, a driving method thereof, a display panel and a display device are provided. The pixel circuit comprises a light-emitting control circuit, a driving circuit and a negative feedback circuit. Wherein the light emission control circuit is capable of controlling the potential of each of the first to fourth nodes in the pixel circuit. The driving circuit can control the potential of the third node based on the potentials of the first node and the second node. When the third node and the fourth node are turned on, the light emitting element can emit light based on the potential of the third node. The negative feedback circuit can adjust the potential of the first node based on the potential of the target node in the third node and the fourth node, so that the potential of the first node and the potential of the target node are changed identically, and further the driving circuit can control the potential of the third node based on the adjusted potential of the first node, so that the light-emitting element can be reliably driven to emit light, and the display effect of the display panel can be ensured to be better.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a brightness waveform diagram when different gray-scale images are displayed in a switching manner according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of another pixel circuit provided in an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a further pixel circuit provided in an embodiment of the disclosure;

FIG. 5 is a schematic diagram of a further pixel circuit according to an embodiment of the disclosure;

fig. 6 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure;

FIG. 7 is a timing diagram of signal terminals coupled to a pixel circuit according to an embodiment of the disclosure;

fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings.

For display products such as OLED display panels, display panels are typically driven at low or high frequencies to display pictures. Wherein the low frequency and the high frequency are relatively speaking, the low frequency generally refers to a few hertz (Hz) or tens of Hz, such as the common 1Hz and 10Hz. High frequency generally refers to hundreds of Hz, such as the usual 120Hz. Compared with the high-frequency driving mode, the low-frequency driving mode is beneficial to reducing the system power consumption and improving the cruising ability of the display panel. However, for refreshing the picture, the picture is smoother under high-frequency driving, and when the picture is driven under low-frequency driving, the refreshing feeling can be obviously perceived by human eyes due to longer frame period time, so that the flicker problem is more likely to occur.

For example, taking low frequency 1Hz as an example, a LongV driving method in which the charging time is unchanged during low frequency driving relative to high frequency driving, at a fundamental frequency of 120Hz, a total of 120 subframes (sub-frames) including 1 refresh Frame and 119 hold frames are generally included in a 1Hz Frame period, and data writing can be performed in the refresh Frame, and a picture can be maintained in the hold Frame, that is, a state of a display picture is maintained. The low frequency 1Hz frame period duration is typically 1 second(s). When different gray-scale pictures are displayed in a switching mode, the working voltage of the driving transistor in the OLED display panel can be changed, and the threshold voltage Vth of the driving transistor cannot be effectively compensated. In this way, the driving current generated by the driving transistor to drive the light emitting element to emit light is different, and thus the luminance is continuously changed in the holding frame, and the luminance is continuously increased or continuously decreased.

In addition, for example, in the case of the display of the black screen to the white screen being switched, since the threshold voltage Vth is smaller than the threshold voltage Vth when the black screen is displayed, the threshold voltage Vth needs to be gradually changed from one state to another after the switching, and the threshold voltage Vth can be stabilized with the lapse of time, that is, no change occurs, so that the luminance change in the holding frame of the previous several frames is obvious after the screen switching, and the display abnormality is perceived by human eyes, and is expressed as a screen refreshing feeling, and a so-called low-frequency smear occurs.

For example, in connection with fig. 1, which illustrates a luminance schematic after black-plane switching, a low frequency of 10Hz is taken as an example. The TE signal refers to a refresh frame, and the waveform change after the TE signal refers to the brightness change in the hold frame. Referring to fig. 1, it can be seen that when a white frame with a gray level of L0 is switched to a black frame with a gray level of L255, the luminance decay of the first frame is generally more obvious after the switching, and then the luminance decay problem is also existed in the multiple frames, but the decay degree is gradually reduced until the luminance tends to be stable. When a white picture with the gray level of L255 is switched to a black picture with the gray level of L32, the brightness of the first frame is generally obviously increased after the switching, and then the brightness of a plurality of frames is increased, but the increasing degree is gradually reduced until the brightness is stabilized. That is, when switching from a white screen having a gray level of L0 to a black screen having a gray level of L255 under low frequency driving of 10Hz, it appears that the frame luminance is kept continuously lowered; when the gray level is changed from the white screen with the gray level of L255 to the black screen with the gray level of L32, the frame brightness is kept continuously increased.

The process of decreasing the threshold voltage Vth from large to small may be referred to as a negative shift, and the process of increasing the threshold voltage Vth from small to large may be referred to as a positive shift, where the positive shift and the negative shift are relatively speaking. And, the black and white images are also relatively speaking, and are not intended to limit specific gray scale values. As described above with reference to fig. 1, the screen of the gray level L0 and the screen of the gray level L32 may be referred to as a black screen with respect to the white screen of the gray level L255.

It should be further noted that, the embodiment of the present disclosure focuses on improving the low-frequency smear problem, and mainly solves the problem of picture refresh blocking caused by that the threshold voltage Vth of the driving transistor cannot be compensated for a long time in a holding frame in the process of picture refresh under low-frequency driving, unlike the common FFR problem and the afterimage problem. Among them, FFR (first frame ratio) problem means: the brightness of the first frame is insufficient when the picture is switched. The afterimage problem refers to: the problem of the content of the previous frame of picture remains.

Currently, in order to improve the low frequency smear problem, a frame inserting driving is commonly used, such as inserting a high frequency frame during the frame switching, i.e. switching from the low frequency driving to the high frequency driving. Then, after refreshing the multi-frame picture, the low frequency driving is switched. E.g., from 1Hz to 120Hz and then to 1Hz. However, the high frequency insertion time is too long (e.g., 2 to 3 seconds), which is disadvantageous for reducing power consumption, which is contrary to the original purpose of low frequency driving, and does not meet the application requirements.

The embodiment of the disclosure provides a pixel circuit design, which can effectively inhibit brightness attenuation of a hold frame during low-frequency driving, improve the smear problem of low-frequency picture refreshing, and can not influence the effect of reducing power consumption.

Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. As shown in fig. 2, the pixel circuit includes: a light emission control circuit 01, a driving circuit 02, and a negative feedback circuit 03.

The light emission control circuit 01 is coupled (i.e., electrically connected) to the Gate signal terminal Gate, the reset signal terminal Re, the light emission control signal terminal EM, the Data signal terminal Data, the initial power supply terminal Vinit, the first power supply terminal VDD, the first node N1, the second node N2, the third node N3, and the fourth node N4, respectively. The light emission control circuit 01 is configured to respond to a Gate driving signal provided by a Gate signal terminal Gate, control on-off of a Data signal terminal Data and a second node N2, control on-off of an initial power supply terminal Vinit and a fourth node N4, and control on-off of a third node N3 and a first node N1, respond to a reset signal provided by a reset signal terminal Re, control on-off of the initial power supply terminal Vinit and the first node N1, respond to a light emission control signal provided by a light emission control signal terminal EM, control on-off of a first power supply terminal VDD and the second node N2, and control on-off of the third node N3 and the fourth node N4.

For example, the light emission control circuit 01 may control the Data signal terminal Data to be turned on with the second node N2, control the initial power terminal Vinit to be turned on with the fourth node N4, and control the third node N3 to be turned on with the first node N1 when the potential of the Gate driving signal provided by the Gate signal terminal Gate is an effective potential. At this time, the Data signal provided by the Data signal terminal Data can be further transmitted to the second node N2 to charge the second node N2. The initial power signal provided by the initial power terminal Vinit may be further transmitted to the fourth node N4 to reduce noise of the fourth node N4. And, the potential of the first node N1 and the potential of the third node N3 may affect each other. And, the light emission control circuit 01 may control the Data signal terminal Data to be decoupled from the second node N2, control the initial power terminal Vinit to be decoupled from the fourth node N4, and control the third node N3 to be decoupled from the first node N1 when the potential of the Gate driving signal provided by the Gate signal terminal Gate is an inactive potential.

Similarly, the light emission control circuit 01 may control the initial power supply terminal Vinit to be turned on with the first node N1 when the potential of the reset signal provided by the reset signal terminal Re is an effective potential. At this time, the initial power signal provided by the initial power terminal Vinit may be further transmitted to the first node N1 to reduce noise of the first node N1. And, the light emission control circuit 01 may control the initial power supply terminal Vinit to be decoupled from the first node N1 when the potential of the reset signal supplied from the reset signal terminal Re is an inactive potential.

Similarly, when the potential of the light emission control signal provided by the light emission control signal terminal EM is an effective potential, the light emission control circuit 01 may control the first power supply terminal VDD to be turned on with the second node N2, and control the third node N3 to be turned on with the fourth node N4. At this time, the first power signal provided by the first power terminal VDD may be further transmitted to the second node N2, and the signal transmitted to the third node N3 may be further transmitted to the fourth node N4. And, the light emission control circuit 01 may control the first power supply terminal VDD to be decoupled from the second node N2 and control the third node N3 to be decoupled from the fourth node N4 when the potential of the light emission control signal provided by the light emission control signal terminal EM is an inactive potential.

Among the effective potential and the ineffective potential, one potential may be a high potential and the other potential may be a low potential, and the high potential and the low potential are also relatively speaking here. In addition, in the light emission control circuit 01, for example, a transistor coupled to the Gate signal terminal Gate, if the transistor is an N-type transistor, the effective potential of the Gate driving signal provided by the Gate signal terminal Gate may be a high potential, and the ineffective potential of the Gate driving signal may be a low potential. If the transistor is a P-type transistor, the active potential of the gate drive signal may be low and the inactive potential of the gate drive signal may be high for the transistor. The other transistors are the same and will not be described in detail.

The driving circuit 02 is coupled to the first node N1, the second node N2, and the third node N3, respectively. The driving circuit 02 is configured to control the potential of the third node N3 based on the potential of the first node N1 and the potential of the second node N2.

For example, when applied to an OLED display panel, the driving circuit 02 may generate a light emission driving signal (i.e., driving current) that drives the OLED to emit light based on the potential of the first node N1 and the potential of the second node N2, and transmit the light emission driving signal to the third node N3.

The negative feedback circuit 03 is coupled to the first node N1 and is also coupled to a target node of the fourth node N4 and the third node N3. I.e. may be coupled to the fourth node N4 or the third node N3, although in some other embodiments may be coupled to the fourth node N4 and/or the third node N3. The negative feedback circuit 03 is configured to adjust the potential of the first node N1 based on the potential of the target node. The fourth node N4 is further configured to be coupled to a first pole of the light emitting element L1, a second pole of the light emitting element L1 is further coupled to the second power source terminal VSS, and the light emitting element L1 is configured to emit light based on the potential of the first pole and the potential of the second pole.

For example, when the light emission control circuit 01 controls the third node N3 to be turned on with the fourth node N4, the potential of the third node N3 (e.g., the light emission driving signal generated by the driving circuit 02) may be further transmitted to the fourth node N4. The light emitting element L1 emits light based on the voltage difference between the light emission driving signal and the second power supply signal supplied from the second power supply terminal VSS. Alternatively, one of the first and second poles of the light emitting element L1 may be an anode and the other pole may be a cathode. The embodiments of the present disclosure will be described with reference to the first electrode being an anode and the second electrode being a cathode. On the basis, the potential of the first power signal provided by the first power terminal VDD may be a high potential, and the potential of the second power signal provided by the second power terminal VSS may be a low potential.

It should be noted that, in the embodiment of the present disclosure, the negative feedback circuit 03 may adjust the potential of the first node N1 based on the potential of the target node, so that the potential change of the first node N1 is the same as the potential change of the target node. The potential change includes: a change pattern (e.g., decrease) and a change in magnitude (e.g., decrease the same magnitude of potential at the same time). In this way, the indirect reverse regulation driving circuit 02 can generate a negative feedback based on a signal generated by the potential of the first node N1 (e.g., a light-emitting driving signal in the form of a driving current). For example, in a scenario of low-frequency driving the OLED display panel, when the potential of the target node decreases, the negative feedback circuit 03 may control the potential of the first node N1 to decrease synchronously with the potential of the target node, so that the driving current generated by the reverse increasing driving circuit 02 based on the potential of the first node N1 suppresses the problem of luminance degradation in the holding frame caused by the decrease in the potential of the target node, thereby effectively improving the low-frequency smear problem.

In summary, the embodiments of the present disclosure provide a pixel circuit. The pixel circuit comprises a light-emitting control circuit, a driving circuit and a negative feedback circuit. Wherein the light emission control circuit is capable of controlling the potential of each of the first to fourth nodes in the pixel circuit. The driving circuit can control the potential of the third node based on the potentials of the first node and the second node. When the third node and the fourth node are turned on, the light emitting element can emit light based on the potential of the third node. The negative feedback circuit can adjust the potential of the first node based on the potential of the target node in the third node and the fourth node, so that the potential of the first node and the potential of the target node are changed identically, and further the driving circuit can control the potential of the third node based on the adjusted potential of the first node, so that the light-emitting element can be reliably driven to emit light, and the display effect of the display panel can be ensured to be better.

Alternatively, the light emission control circuit 01 may be further configured to adjust the potential of the first node N1 based on the first power signal provided by the first power terminal VDD.

On this basis, as can be seen with reference to the schematic diagram of the structure of another pixel circuit shown in fig. 3, the light emission control circuit 01 described in the embodiment of the present disclosure may include: a data writing sub-circuit 011, a compensating sub-circuit 012, a resetting sub-circuit 013, a light emission control sub-circuit 014, and an adjusting sub-circuit 015.

The Data writing sub-circuit 011 may be coupled to the Gate signal terminal Gate, the Data signal terminal Data, and the second node N2, respectively, and may be used for controlling the on-off of the Data signal terminal Data and the second node N2 in response to the Gate driving signal.

For example, the Data writing sub-circuit 011 may control the Data signal terminal Data to be turned on with the second node N2 when the potential of the received gate driving signal is an active potential, and may control the Data signal terminal Data to be decoupled from the second node N2 when the potential of the received gate driving signal is an inactive potential.

The compensation sub-circuit 012 may be coupled to the Gate signal terminal Gate, the third node N3, and the first node N1, respectively, and may be used to control on-off of the third node N3 and the first node N1 in response to the Gate driving signal.

For example, the compensation sub-circuit 012 may control the third node N3 to be turned on with the first node N1 when the potential of the received gate driving signal is an active potential, and may control the third node N3 to be decoupled from the first node N1 when the potential of the received gate driving signal is an inactive potential.

The reset sub-circuit 013 may be coupled to the Gate signal terminal Gate, the reset signal terminal Re, the initial power supply terminal Vinit, the first node N1, and the fourth node N4, respectively, and may be configured to control on-off of the initial power supply terminal Vinit and the fourth node N4 in response to the Gate driving signal, and to control on-off of the initial power supply terminal Vinit and the first node N1 in response to the reset signal.

For example, the reset sub-circuit 013 may control the initial power supply terminal Vinit to be turned on with the fourth node N4 when the potential of the received gate driving signal is an active potential, and may control the initial power supply terminal Vinit to be decoupled from the fourth node N4 when the potential of the received gate driving signal is an inactive potential. Similarly, the reset sub-circuit 013 may control the initial power terminal Vinit to be connected to the first node N1 when the potential of the received reset signal is an active potential, and may control the initial power terminal Vinit to be disconnected from the first node N1 when the potential of the received reset signal is an inactive potential.

The light emission control sub-circuit 014 may be coupled with the light emission control signal terminal EM, the first power supply terminal VDD, the second node N2, the third node N3 and the fourth node N4, respectively, and may be used to control the on-off of the first power supply terminal VDD and the second node N2 and the on-off of the third node N3 and the fourth node N4 in response to the light emission control signal.

For example, the light emission control sub-circuit 014 may control the first power supply terminal VDD to be turned on with the second node N2 and the third node N3 to be turned on with the fourth node N4 when the potential of the received light emission control signal is an effective potential, and may control the first power supply terminal VDD to be decoupled from the second node N2 and the third node N3 to be decoupled from the fourth node N4 when the potential of the received light emission control signal is an ineffective potential.

The regulator sub-circuit 015 may be coupled to the first power supply terminal VDD and the first node N1, respectively, and is configured to regulate the potential of the first node N1 based on the first power supply signal.

Optionally, the negative feedback circuit 03 according to the embodiment of the present disclosure may include: a coupling element. The coupling element may be used to adjust the potential of the first node N1 based on the potential to the target node by having a coupling effect. By way of example, the structure of yet another pixel circuit shown with reference to fig. 4 can be seen: the coupling element in the embodiments of the present disclosure may include: and a coupling capacitor C1.

One end of the coupling capacitor C1 may be coupled to the target node, and the other end of the coupling capacitor C1 may be coupled to the first node N1. Of course, in some other embodiments, the coupling element may be another electronic element with the same coupling effect, such as a coupling transformer.

Optionally, the target node described in the embodiments of the present disclosure may be the fourth node N4. That is, as shown in fig. 4, one end of the coupling capacitor C1 may be coupled with the fourth node N4. Accordingly, the coupling capacitance C1 may adjust the potential of the first node N1 based on the potential of the fourth node N4. Because the fourth node N4 is directly coupled to the light emitting element L1, the potential of the first node N1 can be further reliably adjusted, so as to form a better negative feedback mechanism, thereby avoiding the variation of the driving current for driving the light emitting element L1 to emit light and effectively improving the low-frequency smear problem.

Alternatively, as can be seen with reference to the structure of still another pixel circuit shown in fig. 5, the target node may be the third node N3. That is, one end of the coupling capacitor C1 may be coupled with the third node N3.

Alternatively, as can be seen with continued reference to fig. 4 and 5, the driving circuit 02 described in the embodiments of the present disclosure may include: the transistor T1 is driven.

The gate of the driving transistor T1 may be coupled to the first node N1, the first pole of the driving transistor T1 may be coupled to the second node N2, and the second pole of the driving transistor T1 may be coupled to the third node N3.

Note that, in the transistor, one of the first and second poles may be a source (S) pole, and the other may be a drain (D) pole.

Alternatively, the driving transistor T1 may be a P-type transistor. Accordingly, the effective potential received by the device is low, and the threshold voltage Vth can drift negatively when the device is in a negative bias state for a long time. On this basis, when the potential of the target node decreases due to the negative shift of the threshold voltage Vth of the driving transistor T1, the negative feedback circuit 03 can control the potential of the first node N1 to decrease synchronously through its coupling action, that is, the gate potential of the driving transistor T1 decreases, and further, the gate-source voltage difference Vgs of the driving transistor increases, the driving current generated by the driving transistor T1 increases accordingly, so as to form negative feedback as described in the above embodiment, suppress the phenomenon of continuous attenuation of the frame brightness under the low frequency driving caused by DTFT NBTS, and improve the low frequency smear problem. DTFT NBTS is generally used to measure the stability of the drive transistor characteristics under long-term negative bias.

Alternatively, as can be seen with continued reference to fig. 4 and 5, the data write sub-circuit 011 can include: data is written to the transistor T2. The compensation subcircuit 012 may include: compensating transistor T3. The reset sub-circuit 013 may comprise: a first reset transistor T4 and a second reset transistor T5. The light emission control sub-circuit 014 may include: a first light emission control transistor T6 and a second light emission control transistor T7. The regulator sub-circuit 015 may include: and a storage capacitor Cst.

The Gate of the Data writing transistor T2 may be coupled to the Gate signal terminal Gate, the first pole of the Data writing transistor T2 may be coupled to the Data signal terminal Data, and the second pole of the Data writing transistor T2 may be coupled to the second node N2.

The Gate of the compensation transistor T3 may be coupled to the Gate signal terminal Gate, the first pole of the compensation transistor T3 may be coupled to the third node N3, and the second pole of the compensation transistor T3 may be coupled to the first node N1.

The gate of the first reset transistor T4 may be coupled to the reset signal terminal Re, the first pole of the first reset transistor T4 may be coupled to the initial power terminal Vinit, and the second pole of the first reset transistor T4 may be coupled to the first node N1.

The Gate of the second reset transistor T5 may be coupled to the Gate signal terminal Gate, the first pole of the second reset transistor T5 may be coupled to the initial power terminal Vinit, and the second pole of the second reset transistor T5 may be coupled to the fourth node N4.

The gate of the first light emitting control transistor T6 may be coupled to the light emitting control signal terminal EM, the first pole of the first light emitting control transistor T6 may be coupled to the first power supply terminal VDD, and the second pole of the first light emitting control transistor T6 may be coupled to the second node N2.

The gate of the second light-emitting control transistor T7 may be coupled to the light-emitting control signal terminal EM, the first pole of the second light-emitting control transistor T7 may be coupled to the third node N3, and the second pole of the second light-emitting control transistor T7 may be coupled to the fourth node N4.

One end of the storage capacitor Cst may be coupled to the first power supply terminal VDD, and the other end of the storage capacitor Cst may be coupled to the first node N1.

Alternatively, referring to fig. 4 and 5, in the embodiment of the present disclosure, the data writing transistor T2, the first light emitting control transistor T6, the second light emitting control transistor T7, and the second reset transistor T5 may be P-type transistors as well as the driving transistor T1. The first reset transistor T4 and the compensation transistor T3 may be both N-type transistors.

Alternatively, the active layer material of the P-type transistor may include: low temperature polysilicon (low temperature poly-silicon, LTPS) material. The active layer material of the N-type transistor may include: oxide (oxide) materials. On this basis, a pixel circuit including both P-type and N-type transistors may be referred to as an LTPO pixel circuit, and a pixel circuit including only P-type transistors may be referred to as an LTPS pixel circuit.

The pixel circuits shown in fig. 4 and 5 are LTPO pixel circuits, and are each a new coupling capacitance C1 based on a 7T1C (i.e., 7 transistors and 1 storage capacitance) pixel circuit structure. That is, the pixel circuit design manner provided by the embodiments of the present disclosure may be applicable to LTPO pixel circuits of 7T 1C. Of course, in some other embodiments, the same applies to LTPO pixel circuits of other configurations (e.g., 6T 1C). Alternatively, the same applies to the LTPS pixel circuit described in the above embodiment.

Since the transistor of the oxide material has a low leakage characteristic, by providing the second reset transistor T5 for resetting the anode (i.e., the fourth node N4) of the light emitting element L1 as an oxide N-type transistor, the anode of the light emitting element L1 can be noise-reduced and reset at a high frequency, low frequency components at the time of low frequency driving can be reduced, the voltage holding rate of a long frame period at the time of low frequency driving can be effectively improved, and the human eye flicker visibility can be reduced.

It should be noted that, with continued reference to fig. 4 and 5, based on the LTPO pixel circuit design, the Gate signal terminal Gate may include: the first Gate signal terminal Gate-P and the second Gate signal terminal Gate-N are provided with different potentials of the Gate driving signals. The initial power terminal Vinit includes: the first initial power terminal Vinit-1 and the second initial power terminal Vinit-2 which are different in potential of the initial power signal are provided.

The Gate of the data writing transistor T2 and the Gate of the second reset transistor T5, which are P-type transistors, may be coupled to the first Gate signal terminal Gate-P, and the Gate of the compensation transistor T3, which is an N-type transistor, may be coupled to the second Gate signal terminal Gate-N. A first pole of the first reset transistor T4, which is an N-type transistor, may be coupled to the first initial power terminal Vinit-1, and a second pole of the second reset transistor T5, which is a P-type transistor, may be coupled to the second initial power terminal Vinit-2. And on the basis, the effective potential of the Gate driving signal provided by the first Gate signal terminal Gate-P is low relative to the ineffective potential. The effective potential of the Gate driving signal provided by the second Gate signal terminal Gate-N is high with respect to the ineffective potential.

Fig. 6 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure, which is applied to the pixel circuit shown in any one of fig. 2 to 5. As shown in fig. 6, the method includes:

in step 601, in the first stage, the light-emitting control circuit responds to a reset signal provided by the reset signal terminal to control the initial power supply terminal to be conducted with the first node.

At this time, the initial power signal provided by the initial power terminal may be transmitted to the first node, so as to reset the first node. Accordingly, this first phase may also be referred to as a reset phase.

In step 602, in the second stage, the light emission control circuit controls the initial power supply terminal to be turned on with the fourth node, controls the data signal terminal to be turned on with the second node, and controls the third node to be turned on with the first node in response to the gate driving signal provided by the gate signal terminal.

At this time, the data signal provided by the data signal terminal may be transmitted to the second node, so as to charge the second node. And the potential of the first node and the potential of the third node can mutually influence, thereby realizing the compensation of the threshold voltage. Accordingly, this first phase may also be referred to as the data write and Vth compensation phase.

In step 603, in the third stage, the light emission control circuit controls the first power supply terminal to be turned on with the second node and controls the third node to be turned on with the fourth node in response to the light emission control signal provided by the light emission control signal terminal, and the driving circuit controls the potential of the third node based on the potential of the first node and the potential of the second node, so that the light emitting element emits light based on the potentials of the first pole and the second pole of the light emitting element.

At this time, a path may be formed between the first power supply terminal and the fourth node, and the pixel circuit may generate a driving current through the driving transistor and transmit the driving current to the fourth node, that is, to the first electrode of the light emitting element, so as to drive the light emitting element to emit light. Accordingly, this third phase may also be referred to as a lighting phase.

In step 604, in the fourth stage, the negative feedback circuit adjusts the potential of the first node based on the potentials of the target nodes in the third node and the fourth node, so that the potential change of the first node is the same as the potential change of the target node.

For example, as is clear from the description of the above embodiments, the negative feedback circuit can adjust the potential decrease of the first node in synchronization when the potential of the target node decreases due to the negative bias state of the driving transistor, so as to increase the driving current generated by the driving circuit based on the adjusted potential of the first node in the opposite direction, thereby suppressing the problem of luminance degradation in the holding frame caused by the potential decrease of the target node, and effectively improving the problem of low frequency smear. Accordingly, this fourth stage may also be referred to as a negative feedback stage.

Wherein the first, second and third phases may be located in a refresh frame and the fourth phase may be located in a hold frame following the refresh frame.

Optionally, as shown in fig. 4 and 5, the negative feedback circuit 03 according to the embodiment of the present disclosure includes a coupling capacitor C1. Accordingly, in step 604, the negative feedback circuit adjusts the potential of the first node based on the potentials of the target nodes in the third node and the fourth node, which may include: the negative feedback circuit adjusts the potential of the first node based on the potential of the target node in the third node and the fourth node by having a coupling effect.

Taking the structure shown in fig. 4 as an example, fig. 7 shows a timing diagram of signal terminals coupled to a pixel circuit. As shown in fig. 7, the driving process of the pixel circuit may include a refresh frame and a hold frame that are sequentially performed. Taking 1Hz low frequency driving as an example, as described in the above embodiment, at 120Hz fundamental frequency, 1 refresh frame and 119 hold frames are typically included for 120 subframes in a 1Hz frame period.

The refresh frame may include a first phase (i.e., a reset phase), a second phase (i.e., a data writing and Vth compensation phase), and a third phase (i.e., a light emitting phase) that are sequentially performed.

In the first stage t1, the potential of the Gate driving signal provided by the first Gate signal terminal Gate-P may be a high potential, the potential of the Gate driving signal provided by the second Gate signal terminal Gate-N may be a low potential, the potential of the reset signal provided by the reset signal terminal Re may be a high potential, and the potential of the light emission control signal provided by the light emission control signal terminal EM may be a high potential. Accordingly, among the plurality of transistors included in the pixel circuit shown in fig. 4, the first reset transistor T4 may be turned on, and the remaining transistors such as the data writing transistor T2, the compensation transistor T3, the second reset transistor T5, the first light emission control transistor T6, and the second light emission control transistor T7 may be turned off. At this time, the initial power signal provided by the first initial power terminal Vinit-1 may be transmitted to the first node N1 through the turned-on first reset transistor T4 to perform noise reduction reset on the first node N1, and accordingly, the driving transistor T1 may be turned off. Since the driving transistor T1 is a P-type transistor, the potential of the initial power signal may be high. That is, in the first stage T1, the potential of the driving transistor T1 can be reset to V _Vinit-1 ，V _Vinit-1 Refers to the potential of the initial power signal.

In the second stage t2, the potential of the Gate driving signal provided by the first Gate signal terminal Gate-P may be a low potential, the potential of the Gate driving signal provided by the second Gate signal terminal Gate-N may be a high potential, the potential of the reset signal provided by the reset signal terminal Re may be a low potential, and the potential of the light emission control signal provided by the light emission control signal terminal EM may be a high potential. Accordingly, among the plurality of transistors included in the pixel circuit shown in fig. 4, the data writing transistor T2, the second reset transistor T5, and the compensation transistor T3 may all be turned on, and the remaining transistors such as the first reset transistor T4, the first light emission control transistor T6, and the second light emission control transistor T7 may all be turned off. At this time, the Data signal provided by the Data signal terminal Data can be transmitted to the second node N2 through the turned-on Data writing transistor T2. The initial power signal provided by the second initial power terminal Vinit-2 may be transmitted to the fourth node N4 through the turned-on second reset transistor T5, so as to perform noise reduction and reset on the fourth node N4 (i.e., the anode of the light emitting element L1), so as to prepare for the subsequent light emitting stage, and improve the light emitting contrast. The driving transistor T1 may be regarded as a diode connection, and the storage capacitor Cst may be charged until the potential charged to the first node N1 becomes: vdata+vth. Where Vdata is the potential of the data signal, and Vth is the threshold voltage of the driving transistor T1.

In the third stage t3, the potential of the Gate driving signal provided by the first Gate signal terminal Gate-P may be a high potential, the potential of the Gate driving signal provided by the second Gate signal terminal Gate-N may be a low potential, the potential of the reset signal provided by the reset signal terminal Re may be a low potential, and the potential of the light emission control signal provided by the light emission control signal terminal EM may be a low potential. Accordingly, among the plurality of transistors included in the pixel circuit shown in fig. 4, the first light emitting control transistor T6 and the second light emitting control transistor T7 are turned on, and the driving transistor T1 is kept turned on under the action of the storage capacitor Cst, and the remaining transistors such as the data writing transistor T2, the first reset transistor T4, the second reset transistor T5, the compensation transistor T3, etc. may be turned off. At this time, a path may be formed between the first power supply terminal VDD and the fourth node N4 through the first light emitting control transistor T6, the driving transistor T1 and the second light emitting control transistor T7, which are sequentially connected in series and all turned on, and the driving transistor T1 may generate a driving current based on the potential of the first node N1 and the potential of the second node N2, and transmit the driving current to the anode of the light emitting element L1 through the fourth node N4 to drive the light emitting element L1 to emit light. In the second phase T2, the driving current generated after the compensation by the compensation transistor T3 is independent of the threshold voltage Vth of the driving transistor T1. After this phase, the potential Vn1 of the first node N1 may be: vn1=vdata+vth. The potential Vn4 of the fourth node N4 may be: vn4=vss+voled. Wherein Vss is the potential of the second power signal provided by the second power terminal Vss coupled to the cathode of the light emitting element L1, and Voled is the voltage across the anode and the cathode of the light emitting element L1. Based on the calculation formula of Vn4, the potential of the fourth node N4 is related to the voltage across the two poles of the light emitting element L1 in the light emitting state, and the voltage across the light emitting element L1 is generally positively related to the driving current flowing through the light emitting element L1, that is, the larger the driving current is, the larger the voltage across is, and the brighter the brightness is; conversely, the smaller the drive current, the smaller the cross-voltage and hence the darker the brightness.

After that, a holding frame is entered, the potential of the Gate driving signal supplied from the second Gate signal terminal Gate-N may be held at a low potential, and the potential of the reset signal supplied from the reset signal terminal Re may be held at a low potential. Accordingly, among the plurality of transistors included in the pixel circuit shown in fig. 4, the first reset transistor T4 and the compensation transistor T3 may be always in an off state, and the potential of the first node N1 may be stored and maintained by the storage capacitor Cst without being affected again by the data signal.

Since the P-type driving transistor T1 is always in a negative bias state, the threshold voltage Vth of the driving transistor T1 is inevitably shifted in the negative direction, and the generated driving current is reduced, so that the luminance degradation problem described in the above embodiments occurs in the hold frame. In the embodiment of the present disclosure, when the driving current decreases, that is, the potential of the fourth node N4 decreases due to the negative shift of the threshold voltage Vth of the driving transistor T1, the potential of the first node N1 is pulled to decrease synchronously by the coupling action of the coupling capacitor C1 on the holding frame, that is, the gate potential of the driving transistor T1 decreases. As can be seen from this, the gate-source voltage difference Vgs of the driving transistor T1 increases accordingly, so that the generated driving current also increases, so-called negative feedback is formed, the problem of continuous attenuation of the luminance in the holding frame due to the negative bias state of the driving transistor T1 is suppressed, the low-frequency smear phenomenon is effectively improved, and the display effect is ensured to be better.

Further, referring to fig. 7, it can be seen that the potential of the Gate driving signal supplied from the first Gate signal terminal Gate-P and the potential of the light emission control signal supplied from the light emission control signal terminal EM may include a high potential and a low potential. So that the first and second light emission control transistors T6 and T7 may be in a high frequency (e.g., 240 Hz) on state for achieving brightness adjustment. And the second reset transistor T5 is also in a high-frequency (e.g., 120 Hz) on state, so as to be used for resetting the anode of the light emitting element L1 at a high frequency, thereby improving the flicker phenomenon and further ensuring that the display effect can be better.

In summary, the embodiments of the present disclosure provide a driving method of a pixel circuit. In the method, the pixel circuit includes a light emission control circuit capable of controlling the potential of each of the first to fourth nodes in the pixel circuit. The pixel circuit includes a driving circuit capable of controlling a potential of the third node based on potentials of the first node and the second node. When the third node and the fourth node are turned on, the light emitting element can emit light based on the potential of the third node. The negative feedback circuit included in the pixel circuit can adjust the potential of the first node based on the potentials of the target nodes in the third node and the fourth node, so that the potential of the first node and the potential of the target node change the same, and the driving circuit can control the potential of the third node based on the adjusted potential of the first node, so that the light-emitting element can be reliably driven to emit light, and the display effect of the display panel can be ensured to be good.

Fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the disclosure. As shown in fig. 8, the display panel includes: a substrate B1, and a plurality of pixels P1 on the substrate B1.

Wherein the at least one pixel P1 includes: the light emitting element L1, and the pixel circuit 00 shown in any one of fig. 2 to 5, the pixel circuit 00 is coupled to the light emitting element L1 and is used for driving the light emitting element L1 to emit light.

For example, referring to fig. 2 to 5, the pixel circuit 00 may be coupled to an anode of the light emitting element L1, and a cathode of the light emitting element L1 may be coupled to the second power source terminal VSS. The pixel circuit 00 may transmit a light emission driving signal to the anode of the light emitting element L1, and the light emitting element L1 may emit light under the voltage difference of the light emission driving signal and the second power signal provided from the second power terminal VSS.

Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 9, the display device includes: a signal supply circuit 100, and a display panel 000 as shown in fig. 8.

As can be seen from fig. 8, the signal providing circuit 100 can be coupled to each signal terminal coupled to the pixel P1 of the display panel 000, and is configured to provide a signal to each signal terminal.

For example, the signal supply circuit 100 may include a gate driving circuit and a source driving circuit. The Gate driving circuit may be coupled to a Gate signal terminal Gate coupled to the pixel circuit 00 in the pixel P1, and is configured to provide a Gate driving signal to the Gate signal terminal Gate. The source driving circuit may be coupled to the Data signal terminal Data coupled to the pixel circuit 00 in the pixel P1, and is used for providing the Data signal to the Data signal terminal Data.

Optionally, the display device described in the embodiments of the present disclosure may include: organic light-emitting diode (OLED) display devices, cell phones, tablet computers, flexible display devices, televisions, and any other products or components having display functions.

The terminology used in the description of the embodiments of the disclosure is for the purpose of describing the embodiments of the disclosure only and is not intended to be limiting of the disclosure. Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs.

For example, in the presently disclosed embodiments, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless explicitly defined otherwise.

Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items.

"upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed.

"and/or" means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims

1. A pixel circuit, the pixel circuit comprising:

2. The pixel circuit of claim 1, wherein the negative feedback circuit comprises: and a coupling element for adjusting the potential of the first node based on the potential of the target node by having a coupling effect.

3. The pixel circuit of claim 2, wherein the coupling element comprises: and one end of the coupling capacitor is coupled with the target node, and the other end of the coupling capacitor is coupled with the first node.

4. A pixel circuit according to any one of claims 1 to 3, wherein the target node is the fourth node.

5. A pixel circuit according to any one of claims 1 to 3, wherein the drive circuit comprises: a driving transistor;

6. The pixel circuit of claim 5, wherein the drive transistor is a P-type transistor.

7. A pixel circuit according to any one of claims 1 to 3, and 6, wherein the light emission control circuit is further configured to adjust the potential of the first node based on a first power supply signal supplied from the first power supply terminal; the light emission control circuit includes:

8. The pixel circuit of claim 7, wherein the data writing sub-circuit comprises: a data writing transistor; the compensation sub-circuit includes: a compensation transistor; the reset sub-circuit includes: a first reset transistor and a second reset transistor; the light emission control sub-circuit includes: a first light emission control transistor and a second light emission control transistor; the conditioning sub-circuit includes: a storage capacitor;

9. The pixel circuit according to claim 8, wherein the data writing transistor, the first light emission control transistor, the second light emission control transistor, and the second reset transistor are P-type transistors; the first reset transistor and the compensation transistor are both N-type transistors;

10. The pixel circuit of claim 9, wherein the active layer material of the P-type transistor in the pixel circuit comprises: a low temperature polysilicon material; the active layer material of the N-type transistor comprises: an oxide material.

11. A driving method of a pixel circuit, characterized in that the method is applied to the pixel circuit according to any one of claims 1 to 10, the method comprising:

12. The method of claim 11, wherein the negative feedback circuit adjusts the potential of the first node based on the potential of a target node in the third node and the fourth node, comprising:

13. A display panel, the display panel comprising: a substrate, and a plurality of pixels on the substrate;

wherein at least one pixel comprises: a light emitting element, and a pixel circuit as claimed in any one of claims 1 to 10, coupled to the light emitting element, for driving the light emitting element to emit light.

14. A display device, characterized in that the display device comprises: a signal supply circuit as claimed in claim 13;