CN116301170A - Low-dropout linear voltage regulator capable of reducing subthreshold swing and implementation method thereof - Google Patents
Low-dropout linear voltage regulator capable of reducing subthreshold swing and implementation method thereof Download PDFInfo
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Abstract
The invention discloses a low dropout linear voltage regulator for reducing subthreshold swing and an implementation method thereof, wherein the low dropout linear voltage regulator comprises: the open-loop LDO circuit is used for providing stable grid voltage for the second MOS tube, the second MOS tube and the dynamic substrate bias circuit; wherein: the drain electrode of the second MOS tube is electrically connected with the power supply voltage, and the source electrode of the second MOS tube provides load current for a connected load; and the dynamic substrate bias circuit is arranged between the source electrode of the second MOS tube and the substrate and is used for reversely adjusting the substrate bias voltage of the second MOS tube according to the change of the output voltage of the second MOS tube working in the subthreshold region when the load current or the load resistance value changes, so that the output voltage of the source electrode end of the second MOS tube is adjusted. The subthreshold swing of the LDO can be greatly reduced through the invention, so that larger load current variation can be tolerated within a certain output voltage variation range.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a low dropout linear voltage regulator for reducing subthreshold swing and an implementation method thereof.
Background
The LDO (Low-dropout Regulator) is widely applied to electronic systems and has the characteristics of Low noise and small output voltage ripple. LDOs are generally used as important circuits of power management modules, and can be used for voltage regulation output to supply power to a plurality of circuit modules.
The subthreshold swing (Subthreshold Swing) is an important index for measuring the performance of LDO, and the subthreshold swing is the source leakage current I of the transistor in LDO ds Every time an order of magnitude is raised, the gate voltage V gs Is a variable amount of (a). For example, the amount of change in gate voltage required for ten times the change in source-drain current of a transistor in an LDO, also called S factor, needs to be as small as possible in order to obtain as large a load change range as possible within a small output voltage change range, so that a small subthreshold swing is required as much as possible to obtain a certain output voltage change range, and a larger load current change can be tolerated.
Therefore, the smaller the subthreshold swing of the LDO is, the better, and the subthreshold swing of the conventional LDO structure is difficult to meet the requirement of the power management chip with high performance requirement.
Disclosure of Invention
The invention aims to provide a low-dropout linear voltage regulator which greatly reduces subthreshold swing compared with a traditional LDO structure so as to meet the requirement of a power management chip with very high performance requirements.
Specifically, the technical scheme of the invention is as follows:
a low dropout linear regulator for reducing subthreshold swing, comprising: the open-loop LDO circuit, the second MOS tube and the dynamic substrate bias circuit; wherein:
the open-loop LDO circuit is used for providing stable grid voltage for the second MOS tube, so that the second MOS tube works in a subthreshold region;
the drain electrode of the second MOS tube is electrically connected with the power supply voltage, the source electrode of the second MOS tube is used as the output end of the low-dropout linear voltage regulator to provide output voltage, and the connected load provides load current; the source electrode of the second MOS tube is electrically connected with the substrate and the dynamic substrate bias circuit;
the dynamic substrate bias circuit is used for reversely adjusting the substrate bias voltage provided for the second MOS tube according to the change of the output voltage output by the source electrode of the second MOS tube working in the subthreshold region when the load current or the load resistance value of the load connected to the source electrode end of the second MOS tube changes, so as to adjust the output voltage of the source electrode end of the second MOS tube.
In some embodiments, the open loop LDO circuit specifically includes:
the first operational amplifier, the first MOS tube, the first voltage dividing resistor and the second voltage dividing resistor; wherein:
the non-inverting input end of the first operational amplifier is connected with a reference voltage, the output end of the first operational amplifier is electrically connected with the grid electrode of the first MOS tube, and the output end of the first operational amplifier is also electrically connected with the grid electrode of the second MOS tube;
the drain electrode of the first MOS tube is connected with the power supply voltage, the substrate of the first MOS tube is grounded, and the source electrode of the first MOS tube is grounded after passing through a first voltage dividing resistor and a second voltage dividing resistor; and the connecting middle point of the first voltage dividing resistor and the second voltage dividing resistor is electrically connected with the inverting input end of the first operational amplifier.
In some embodiments, the dynamic substrate bias circuit is specifically selected from subtractor modulation circuit, switch capacitance modulation circuit, and triangular wave modulation circuit; in any mode, based on the detected change condition of the output voltage of the source electrode output of the second MOS tube, the substrate bias voltage of the second MOS tube is reversely adjusted.
In some embodiments, the subtractor modulation circuit specifically includes: the second operational amplifier, the third resistor and the fourth resistor; wherein:
the non-inverting input end of the second operational amplifier is connected with a reference voltage; the inverting input end of the second operational amplifier is electrically connected with the source electrode end of the second MOS tube through a third resistor, and the output end of the second operational amplifier is connected with the inverting input end of the second operational amplifier through a fourth resistor; and the output end of the second operational amplifier is electrically connected with the substrate of the second MOS tube and is used for providing the adjusted substrate bias voltage for the second MOS tube.
In some embodiments, the switched-capacitor modulation circuit specifically includes: a first switch, a third switch, a second switch, a fourth switch, a first polarity capacitance unit and a second capacitance; the first switch and the third switch are controlled to be on-off by a first clock signal, the second switch and the fourth switch are controlled to be on-off by a second clock signal, and the first clock signal and the second clock signal are opposite; wherein:
the first end of the first switch is electrically connected with the source electrode end of the second MOS tube, the second end of the first switch is electrically connected with the first end of the second switch, and the second end of the second switch is electrically connected with the substrate of the second MOS tube;
the connection intermediate point of the first switch and the second switch is electrically connected with the positive electrode end of the first polarity capacitor unit, and the negative electrode end of the first polarity capacitor unit is grounded after passing through the third switch; the middle point of connection between the third switch and the first polarity capacitor unit is connected with reference voltage through the fourth switch; the first end of the second capacitor is connected to the substrate of the second MOS tube, and the second end of the second capacitor is grounded.
In some embodiments, the first polarity capacitor unit is formed by connecting a plurality of polarity capacitors in series or in parallel.
In some embodiments, the triangular wave modulation circuit specifically includes: the device comprises a comparator, a third MOS tube, a third capacitor, a fifth voltage dividing resistor and a sixth voltage dividing resistor; wherein:
the non-inverting input end of the comparator is electrically connected with the source electrode of the second MOS tube, the inverting input end of the comparator is connected with external triangular waves, the output end of the comparator is electrically connected with the grid electrode of the third MOS tube, and the drain electrode of the third MOS tube is connected with reference voltage after passing through a sixth voltage dividing resistor and a fifth voltage dividing resistor; the source electrode of the third MOS tube is grounded; the middle point of connection between the fifth voltage dividing resistor and the sixth voltage dividing resistor is electrically connected with the first end of the third capacitor, the second end of the third capacitor is grounded, and the first end of the third capacitor is also electrically connected with the substrate of the second MOS tube.
In some embodiments, the first MOS transistor and the second MOS transistor are both NMOS transistors.
In some embodiments, the ratio of the width to length ratios of the first MOS transistor to the second MOS transistor is 1: K.
the application also discloses a realization method for reducing subthreshold swing of the low dropout linear voltage regulator, which is applied to any one of the low dropout linear voltage regulators for reducing subthreshold swing, and comprises the following steps: providing a stable grid voltage for the second MOS tube through an open-loop LDO circuit, so that the second MOS tube works in a subthreshold region; and dynamically adjusting the substrate bias voltage of the second MOS tube according to the output voltage of the source electrode of the second MOS tube working in the sub-threshold region through a dynamic substrate bias circuit, so that the substrate bias voltage of the second MOS tube changes reversely along with the output voltage of the source electrode of the second MOS tube.
Compared with the prior art, the invention reversely adjusts the substrate bias voltage of the second MOS tube according to the output voltage of the low-dropout linear voltage regulator by the dynamic substrate bias circuit, so that the threshold voltage of the second MOS tube changes along with the same direction of the output voltage, and further adjusts the output voltage, so that the corresponding output voltage change range is smaller in the same load current change or the same load resistance change range, or larger load current change can be tolerated in the same output voltage change range. Therefore, the subthreshold swing of the low dropout linear voltage regulator is reduced, so that larger load current variation can be tolerated within a certain output voltage variation range.
Drawings
The above features, technical features, advantages and implementation of the present invention will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a schematic circuit connection diagram of one embodiment of a low dropout linear regulator of the present application;
FIG. 2 is a circuit diagram of another embodiment of a low dropout linear regulator of the present application;
FIG. 3 is a circuit diagram of a subtractor modulation circuit in accordance with the present application;
FIG. 4 is a circuit diagram of a specific circuit connection of the switched-capacitor modulation circuit of the present application;
FIG. 5 is a circuit diagram of a triangular wave modulation circuit in the present application;
fig. 6 is a schematic diagram of control logic of the triangular wave modulation circuit in the present application.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
For simplicity of the drawing, only the parts relevant to the invention are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In this context, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In one embodiment, referring to fig. 1 of the specification, the low dropout linear regulator provided by the present invention includes: an open loop LDO circuit 10, a second MOS transistor M2, and a dynamic substrate bias circuit 20; wherein:
the open-loop LDO circuit 10 is configured to provide a stable gate voltage to the second MOS transistor M2, so that the second MOS transistor M2 works in a subthreshold region;
the drain electrode of the second MOS transistor M2 is electrically connected to the power supply voltage, and the source electrode of the second MOS transistor M2 is electrically connected to the dynamic substrate bias circuit 20;
the dynamic substrate bias circuit 20 is configured to dynamically adjust the substrate bias voltage of the second MOS transistor M2 according to the output voltage of the second MOS transistor M2 operating in the subthreshold region, so as to reduce the subthreshold swing.
In this embodiment, the open-loop LDO circuit 10 can be designed with a conventional LDO structure, and is mainly used for providing a stable gate voltage to the second MOS transistor M2, and the source electrode of the second MOS transistor M2 is connected to the load R load And the dynamic substrate bias circuit 20 is arranged between the source electrode of the second MOS tube M2 and the substrate, and the dynamic substrate bias circuit 20 reversely adjusts the substrate bias voltage of the second MOS tube M2 according to the output voltage output by the source electrode of the second MOS tube M2, so that the low-dropout linear voltage regulator can tolerate larger load current change within a certain output voltage change range, and the subthreshold swing is greatly reduced.
In the above embodiment, as shown in fig. 2, the open-loop LDO circuit specifically includes: the first operational amplifier AMP1, the first MOS tube M1, the first voltage dividing resistor R1 and the second voltage dividing resistor R2; wherein:
the non-inverting input terminal of the first operational amplifier AMP1 is connected with a reference voltage V ref The output end of the first operational amplifier AMP1 is electrically connected with the gate of the first MOS transistor M1, and the output end of the first operational amplifier AMP1 is also electrically connected with the gate of the second MOS transistor M2;
the drain electrode of the first MOS tube M1 is connected with a power supply voltage, the substrate of the first MOS tube M1 is grounded, and the source electrode of the first MOS tube M1 is grounded after passing through a first voltage dividing resistor R1 and a second voltage dividing resistor R2; the connection intermediate point a of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is electrically connected to the inverting input terminal of the first operational amplifier AMP 1.
In this embodiment, on the basis of the conventional LDO structure, a dynamic substrate bias circuit is added between the source electrode of the second MOS transistor and the substrate, so that the substrate bias voltage of the second MOS transistor M2 is changed according to the output voltage of the source electrode of the second MOS transistor, thereby reducing the subthreshold swing.
For an LDO, the smaller the subthreshold swing, the better the performance, that is, the same load resistance change or the same load current change, the smaller the output voltage fluctuation range of the LDO, the smaller the subthreshold swing of the LDO, and the better the performance of the LDO. Conversely, the same variation range of the output voltage of the LDO, and a larger variation range of the corresponding load current, the better the subthreshold swing of the LDO.
Preferably, the open-loop LDO circuit is further configured to set the resistances of the first voltage dividing resistor and the second voltage dividing resistor, so that the output voltage at the source end of the second MOS transistor reaches the set rated voltage.
Specifically, in the open loop LDO circuit of the present embodiment, the first operational amplifier AMP1 is a negative feedback, the final adjustment thereof is such that the voltages at the positive and negative inputs are the same (virtual short and disconnection: the voltages at the two inputs of the operational amplifier are the same as virtual short circuit, but there is no current relationship therebetween, the voltages at the two inputs are kept at the same value only by the negative feedback), so that after the negative feedback is operated, the negative feedback loop will keep the intermediate connection point A of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 at V ref And (3) a reference voltage. The output end of the first operational amplifier AMP1 is connected with the grid electrodes of the first MOS tube M1 and the second MOS tube M2, so that stable grid voltage (equivalent to voltage clamping) is provided for the first MOS tube M1 and the second MOS tube M2, and the second MOS tube M2 works in a subthreshold region.
The size of the first MOS tube M1 and the second MOS tube M2 is placed according to the proportion K, the circuit utilizes the first voltage dividing resistor R1, the second voltage dividing resistor R2 and the first operational amplifier AMP1, the first MOS tube M1 forms a loop, and the source terminal of the first MOS tube M1 can obtain a preset proportion voltage:
in the above formula (1), V s1 The source voltage of the first MOS transistor M1; v (V) ref Is the reference voltage; r is R 1 Is the resistance value of the first voltage dividing resistor, R 2 The resistance of the second voltage dividing resistor.
Connecting the second MOS tube M2 with the grid electrode of the first MOS tube M1, and placing the first MOS tube M1 and the second MOS tube M2 according to the size K, when
V at the time of out =V s1 Therefore, the output voltage of the source electrode of the second MOS tube M2 can reach the preset proportional voltage.
The drain-source current formulas of the two MOS tubes are shown as (2) and (3), and the current of the MOS tubes is along with V in a saturation/subthreshold region gs Is increased by an increase in (a).
Wherein I is Saturation The drain-source current of the MOS tube working in the saturation region is I Subthreshold value Source leakage current when the MOS tube works in a subthreshold region; v (V) T Is the thermal voltage of the MOS tube,
is the substrate coefficient of the MOS tube, W/L is the width-to-length ratio of the MOS tube, V th Is the threshold voltage of the MOS tube, C ox Capacitance per unit area of gate oxide layer, mu n Electron mobility for inversion layer; v (V) gs The gate source voltage of the MOS tube; c (C) d Is the unit capacitance.
At this time if it flows through the load R load Is the current I of (2) d Variation, V out The voltage will also vary. Examples of the examplesDescription of R load Resistance value is reduced, I d The gate-source voltage V of the second MOS transistor M2 is increased gs2 And also becomes large. Due to the gate voltage V of the second MOS transistor M2 g2 Unchanged, V out And becomes smaller. Obviously the same V gs2 When the second MOS transistor M2 works in the subthreshold region, the current change is larger.
In this embodiment, the subthreshold swing concept, i.e., I, is introduced d Current change by 10 times, V gs2 Is a voltage change of the voltage of the power supply. In order to make V as small as possible out Obtaining R as large as possible within a variable range load The range of variation requires as small subthreshold swing as possible to achieve a certain V out The maximum load current variation can be tolerated within the variation range.
In general, for an NMOS transistor, its threshold voltage can be expressed as:
wherein: v (V) th Is the threshold voltage of the MOS tube, V th0 The threshold voltage of the MOS transistor when the substrate voltage is 0; phi F For fermi potential, gamma is the body effect coefficient, V SB Is the source and substrate voltage of the MOS tube.
As can be seen from equation (4), in the conventional LDO structure, the substrate of the second MOS transistor is generally grounded, so the threshold voltage is generally fixed. Unlike the present embodiment, a substrate bias circuit is disposed between the source of the second MOS transistor and the substrate, as shown in FIG. 2, and the dynamic substrate bias circuit is implemented by detecting the output voltage V of the source terminal (i.e. LDO output terminal) of the second MOS transistor M2 out Correspondingly and proportionally reversely adjusting the substrate bias voltage V of the second MOS tube M2 sub2 As output R load V when the current becomes small out The voltage is increased, and under the adjustment of the dynamic substrate bias circuit, the substrate bias voltage V of the second MOS tube sub2 The voltage is controlled to be reduced, so that the source and substrate voltages V of the second MOS transistor M2 are reduced SB2 Becoming large; when outputting R load When the current of (2) becomes large, V out The voltage is reduced and the voltage is reduced,v under the adjustment of a dynamic substrate bias circuit sub2 The voltage is controlled to be increased, so that the source and substrate voltages V of the second MOS transistor M2 are achieved SB2 And (3) reducing.
In combination with equation (4), it can be seen that the source, substrate voltage V of M2 SB2 When the current is increased, the threshold voltage of M2 is increased, and when the current is changed with the same current by combining a subthreshold region current formula in the formula (3), V th2 Become large to cause V gs2 Also synchronously gets larger, and the gate voltage is stable and unchanged, V out Will become smaller.
Corresponding to the circuit in FIG. 2, when the output R load When the current of (2) becomes large, V out The voltage is reduced, the substrate bias voltage V of the second MOS transistor M2 sub2 The voltage will correspondingly rise, thereby the source and substrate voltages V of the second MOS transistor M2 SB2 Reduce and then make the threshold voltage V of the second MOS transistor M2 th2 And becomes smaller. Combining the subthreshold region current formula in (3), V when the same current is applied th2 V can be made smaller gs2 Also decrease synchronously, i.e. V out And becomes large. So after adding the dynamic substrate bias circuit, output R load The current change of (2) is of the same magnitude, V out The voltage can meet the requirement only by changing smaller voltage, namely the subthreshold swing is reduced.
And the body effect coefficient gamma is about 0.3-0.4 along with different processes, the gain of the loop is naturally smaller than 1, and the stability of the loop is very easy to ensure.
With respect to dynamic substrate bias circuits, a variety of implementations may be employed, with only a few specific implementations of dynamic substrate bias circuits being shown below, the present application including but not limited to the following specific implementations.
(1) Subtractor modulation circuit
One implementation of the subtractor modulation circuit, as shown in fig. 3, includes: a second operational amplifier AMP2, a third resistor R3, and a fourth resistor R4; wherein:
the non-inverting input terminal of the second operational amplifier AMP2 is connected with the reference voltage V ref The method comprises the steps of carrying out a first treatment on the surface of the The inverting input terminal of the second operational amplifier AMP2 is connected with the source electrode of the second MOS tube M2 through a third resistor R3The output end of the second operational amplifier AMP2 is connected to the inverting input end of the second operational amplifier AMP2 through a fourth resistor R4; and the output end of the second operational amplifier AMP2 is electrically connected to the substrate of the second MOS transistor M2, and is configured to provide the adjusted substrate bias voltage to the second MOS transistor M2.
The fourth resistor R4 constitutes a subtracting circuit by the second operational amplifier AMP2 and the third resistor R3, in which case:
then it can be realized that when V out When the voltage changes, V sub2 The voltage varies inversely.
(2) Switched capacitor modulation circuit
The switch capacitance modulation circuit realizes the modulation of the substrate bias voltage of the second MOS tube through mutually exclusive external clock control logic.
One implementation manner of the switched capacitor modulation circuit, as shown in fig. 4, specifically includes: a first switch K1, a third switch K3, a second switch K2, a fourth switch K4, a first polarity capacitance unit C1 and a second capacitance C2; the first switch K1 and the third switch K3 are both controlled to be on-off by a first clock signal phi 1, the second switch K2 and the fourth switch K4 are both controlled to be on-off by a second clock signal phi 2, and the first clock signal phi 1 and the second clock signal phi 2 are opposite; wherein:
the first end of the first switch K1 is electrically connected with the source electrode end of the second MOS tube M2, the second end of the first switch K1 is electrically connected with the first end of the second switch K2, and the second end of the second switch K2 is electrically connected with the substrate of the second MOS tube M2;
the connection intermediate point of the first switch and the second switch is electrically connected with the positive electrode end of the first polarity capacitor unit C1, and the negative electrode end of the first polarity capacitor unit C1 is grounded after passing through the third switch K3; the third switch K3 is connected to the middle point of the connection of the first polarity capacitor unit C1, and is connected to the reference voltage V through the fourth switch K4 ref The method comprises the steps of carrying out a first treatment on the surface of the One end of the second capacitor C2 is connected to the substrate of the second MOS transistor M2, and the other end of the second capacitor C2 is grounded.
The first polarity capacitor unit C1 may be a single polarity capacitor (as shown in fig. 4), or may be formed by connecting a plurality of polarity capacitors in series and/or parallel.
V can be realized in FIG. 4 by mutually exclusive external clock control logics of phi 1 and phi 2 sub2 The specific working process is as follows, when the phi 1 switch is turned on, C1+ turns on V out C1-is connected to ground, the storage voltage at C1 is V out . When the phi 2 switch is turned on, C1+ turns on V sub2 And C1-turn on V ref . This structure can realize:
n in formula (6) is a positive integer, corresponding to the case n=1 in fig. 4. When the number of C1 in series-parallel connection in the topology of FIG. 4 is adjusted, the proportion modulation of arbitrary N times or 1/N times can be realized.
(3) Triangular wave modulation circuit
The triangular wave modulation circuit outputs an output voltage V between an externally input fixed frequency triangular wave and the source electrode of the second MOS tube M2 out And comparing, and adjusting the substrate bias voltage output to the second MOS tube M2 according to the comparison result.
In one implementation manner of the triangular wave modulation circuit, as shown in fig. 5, the triangular wave modulation circuit specifically includes: the comparator comp, the third MOS tube M3, the third capacitor C3, the fifth voltage dividing resistor R5 and the sixth voltage dividing resistor R6; wherein:
the non-inverting input end of the comparator comp is electrically connected with the source electrode of the second MOS tube M2 and is used for receiving the output voltage output by the source electrode of the second MOS tube; the inverting input end of the comparator comp is connected with an external triangular wave, the output end of the comparator comp is electrically connected with the grid electrode of the third MOS tube M3, and the drain electrode of the third MOS tube M3 is connected with a reference voltage V after passing through a sixth voltage dividing resistor R6 and a fifth voltage dividing resistor R5 ref The method comprises the steps of carrying out a first treatment on the surface of the The third MThe source electrode of the OS tube M3 is grounded; the connection intermediate point B of the fifth voltage dividing resistor R5 and the sixth voltage dividing resistor R6 is electrically connected with the first end of the third capacitor C3, and the second end of the third capacitor C3 is grounded; and the first end of the third capacitor C3 is further electrically connected to the substrate of the second MOS transistor (or the connection intermediate point B between the fifth voltage dividing resistor R5 and the sixth voltage dividing resistor R6 is electrically connected to the substrate of the second MOS transistor).
Specifically, as shown in fig. 6, the comparator comp outputs the external input fixed frequency triangular wave received by the negative input end and the output voltage V received by the positive input end and outputted by the source electrode of the second MOS tube out The comparison result, that is, the output signal Vc of the comparator comp is output to the third MOS transistor M3 (M3 in fig. 5 is an NMOS transistor) to control the connection state of the voltage dividing resistor R6, so that the sixth voltage dividing resistor R6 is connected to the voltage dividing circuit R5, R6 according to the duty ratio D of the Vc signal.
When V is out When the duty ratio D of Vc becomes larger, R6 is connected into the circuit for a longer time, and finally V is caused sub2 The voltage drops.
Equation (7) is a substrate bias voltage representation in a triangular wave modulation circuit, and as can be seen from equation (7), V is increased with the increase of D sub2 The corresponding proportional decrease.
The above description provides several specific dynamic substrate bias circuits, and of course, other specific circuit implementations are not limited in this application, and any modulation circuit provided between the source electrode of the second MOS transistor and the substrate and used for reversely adjusting the substrate bias voltage of the second MOS transistor according to the output voltage output by the source electrode of the second MOS transistor may be regarded as the dynamic substrate bias circuit of this application, which is within the protection scope of this application.
In the above embodiment, the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are all NMOS transistors. Of course, PMOS transistors may be used, and if PMOS transistors are used, the corresponding connection relationship is equivalently changed.
Finally, the application discloses a method for realizing the low dropout linear voltage regulator to reduce the subthreshold swing, which is applied to the low dropout linear voltage regulator of any one of the embodiments, and comprises the following steps:
s100, providing stable grid voltage for the second MOS tube through an open-loop LDO circuit; enabling the second MOS tube to work in a subthreshold region;
s200, dynamically adjusting the substrate bias voltage of the second MOS tube according to the output voltage of the source electrode of the second MOS tube working in the subthreshold region through a dynamic substrate bias circuit arranged between the source electrode of the second MOS tube and the substrate, so that the substrate bias voltage of the second MOS tube changes reversely along with the output voltage of the source electrode of the second MOS tube, and the output voltage of the source electrode end of the second MOS tube is adjusted.
The circuit structure of the low dropout linear regulator in the above embodiment may adopt the low dropout linear regulator for reducing the subthreshold swing in any of the foregoing embodiments, and in order to reduce repetition, the description is omitted here.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (10)
1. A low dropout linear regulator for reducing subthreshold swing, comprising: the open-loop LDO circuit, the second MOS tube and the dynamic substrate bias circuit; wherein:
the open-loop LDO circuit is used for providing stable grid voltage for the second MOS tube, so that the second MOS tube works in a subthreshold region;
the drain electrode of the second MOS tube is electrically connected with the power supply voltage, the source electrode of the second MOS tube is used as the output end of the low-dropout linear voltage regulator to provide output voltage and load current for a connected load; the source electrode of the second MOS tube is electrically connected with the substrate and the dynamic substrate bias circuit;
the dynamic substrate bias circuit is used for reversely adjusting the substrate bias voltage provided for the second MOS tube according to the change of the output voltage output by the source electrode of the second MOS tube working in the subthreshold region when the load current or the load resistance value of the load connected to the source electrode end of the second MOS tube changes, so as to adjust the output voltage of the source electrode end of the second MOS tube.
2. The low dropout linear regulator for reducing subthreshold swing of claim 1, wherein said open loop LDO circuit specifically comprises:
the first operational amplifier, the first MOS tube, the first voltage dividing resistor and the second voltage dividing resistor; wherein:
the non-inverting input end of the first operational amplifier is connected with a reference voltage, the output end of the first operational amplifier is electrically connected with the grid electrode of the first MOS tube, and the output end of the first operational amplifier is also electrically connected with the grid electrode of the second MOS tube;
the drain electrode of the first MOS tube is connected with the power supply voltage, the substrate of the first MOS tube is grounded, and the source electrode of the first MOS tube is grounded after passing through a first voltage dividing resistor and a second voltage dividing resistor; and the connecting middle point of the first voltage dividing resistor and the second voltage dividing resistor is electrically connected with the inverting input end of the first operational amplifier.
3. The low dropout linear regulator for reducing a subthreshold swing according to claim 1 or 2, wherein the dynamic substrate bias circuit reversely adjusts the substrate bias voltage of the second MOS transistor based on the detected change of the output voltage of the source electrode output of the second MOS transistor by specifically using any one of a subtractor modulation circuit, a switched capacitor modulation circuit and a triangular wave modulation circuit.
4. A low dropout linear regulator for reducing a subthreshold swing according to claim 3, wherein said subtractor modulating circuit specifically comprises: the second operational amplifier, the third resistor and the fourth resistor; wherein:
the non-inverting input end of the second operational amplifier is connected with a reference voltage; the inverting input end of the second operational amplifier is electrically connected with the source electrode end of the second MOS tube through a third resistor, and the output end of the second operational amplifier is connected with the inverting input end of the second operational amplifier through a fourth resistor; and the output end of the second operational amplifier is electrically connected with the substrate of the second MOS tube and is used for providing the adjusted substrate bias voltage for the second MOS tube.
5. The low dropout linear regulator for reducing a subthreshold swing according to claim 3, wherein said switched-capacitor modulation circuit specifically comprises: a first switch, a third switch, a second switch, a fourth switch, a first polarity capacitance unit and a second capacitance; the first switch and the third switch are controlled to be on-off by a first clock signal, the second switch and the fourth switch are controlled to be on-off by a second clock signal, and the first clock signal and the second clock signal are opposite; wherein:
the first end of the first switch is electrically connected with the source electrode end of the second MOS tube, the second end of the first switch is electrically connected with the first end of the second switch, and the second end of the second switch is electrically connected with the substrate of the second MOS tube;
the connection intermediate point of the first switch and the second switch is electrically connected with the positive electrode end of the first polarity capacitor unit, and the negative electrode end of the first polarity capacitor unit is grounded after passing through the third switch; the middle point of connection between the third switch and the first polarity capacitor unit is connected with reference voltage through the fourth switch; the first end of the second capacitor is connected to the substrate of the second MOS tube, and the second end of the second capacitor is grounded.
6. The low dropout linear regulator for reducing a sub-threshold swing according to claim 5, wherein said first polarity capacitor unit is comprised of a plurality of polarity capacitors connected in series or in parallel.
7. The low dropout linear regulator for reducing a subthreshold swing according to claim 3, wherein said triangular wave modulation circuit specifically comprises: the device comprises a comparator, a third MOS tube, a third capacitor, a fifth voltage dividing resistor and a sixth voltage dividing resistor; wherein:
the non-inverting input end of the comparator is electrically connected with the source electrode of the second MOS tube, the inverting input end of the comparator is connected with external triangular waves, the output end of the comparator is electrically connected with the grid electrode of the third MOS tube, and the drain electrode of the third MOS tube is connected with reference voltage after passing through a sixth voltage dividing resistor and a fifth voltage dividing resistor; the source electrode of the third MOS tube is grounded; the middle point of connection between the fifth voltage dividing resistor and the sixth voltage dividing resistor is electrically connected with the first end of the third capacitor, the second end of the third capacitor is grounded, and the first end of the third capacitor is also electrically connected with the substrate of the second MOS tube.
8. The low dropout linear regulator for reducing a subthreshold swing according to any one of claims 1 to 7, wherein said first MOS transistor and said second MOS transistor are NMOS transistors.
9. The low dropout linear regulator for reducing a subthreshold swing according to claim 2, wherein a ratio of width to length of the first MOS transistor to the second MOS transistor is 1: K.
10. a method for implementing a low dropout linear regulator for reducing a subthreshold swing, the method being applied to a low dropout linear regulator for reducing a subthreshold swing according to any one of claims 1 to 9, the method comprising:
providing a stable grid voltage for the second MOS tube through an open-loop LDO circuit; enabling the second MOS tube to work in a subthreshold region;
and dynamically adjusting the substrate bias voltage of the second MOS tube according to the output voltage of the source electrode of the second MOS tube working in the sub-threshold region through a dynamic substrate bias circuit arranged between the source electrode of the second MOS tube and the substrate, so that the substrate bias voltage of the second MOS tube changes reversely along with the output voltage of the source electrode of the second MOS tube, and the output voltage of the source electrode end of the second MOS tube is adjusted.
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| CN202310921883.9A CN116700419A (en) | 2023-05-26 | 2023-05-26 | Low-dropout linear voltage regulator capable of reducing subthreshold swing and implementation method thereof |
| CN202310601003.XA CN116301170B (en) | 2023-05-26 | 2023-05-26 | Low-dropout linear voltage regulator capable of reducing subthreshold swing and implementation method thereof |
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| US20190011944A1 (en) * | 2016-03-25 | 2019-01-10 | Panasonic Intellectual Property Management Co., Ltd. | Regulator circuit |
| US20210080991A1 (en) * | 2019-09-18 | 2021-03-18 | Nuvoton Technology Corporation | Substrate bias generating circuit |
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2023
- 2023-05-26 CN CN202310921883.9A patent/CN116700419A/en active Pending
- 2023-05-26 CN CN202310601003.XA patent/CN116301170B/en active Active
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| JP2006155359A (en) * | 2004-11-30 | 2006-06-15 | Sanyo Electric Co Ltd | Voltage step-down circuit |
| JP2007148561A (en) * | 2005-11-24 | 2007-06-14 | New Japan Radio Co Ltd | Stabilized power supply circuit |
| CN1828470A (en) * | 2006-02-15 | 2006-09-06 | 启攀微电子（上海）有限公司 | Circuit for enhancing driving capability of low voltage-difference linear voltage manostat |
| CN105242738A (en) * | 2015-11-25 | 2016-01-13 | 成都信息工程大学 | Resistance-free reference voltage source |
| US20190011944A1 (en) * | 2016-03-25 | 2019-01-10 | Panasonic Intellectual Property Management Co., Ltd. | Regulator circuit |
| CN107463198A (en) * | 2017-08-11 | 2017-12-12 | 天津大学 | Low-temperature coefficient reference voltage source applied to LVDS drive circuits |
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| US20210080991A1 (en) * | 2019-09-18 | 2021-03-18 | Nuvoton Technology Corporation | Substrate bias generating circuit |
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| CN116301170B (en) | 2023-08-18 |
| CN116700419A (en) | 2023-09-05 |
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