CN116299463B - Small sar imaging system and method based on rear end of general computing device - Google Patents
Small sar imaging system and method based on rear end of general computing device Download PDFInfo
- Publication number
- CN116299463B CN116299463B CN202310548877.3A CN202310548877A CN116299463B CN 116299463 B CN116299463 B CN 116299463B CN 202310548877 A CN202310548877 A CN 202310548877A CN 116299463 B CN116299463 B CN 116299463B
- Authority
- CN
- China
- Prior art keywords
- module
- imaging
- main control
- servo
- parameters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/9004—SAR image acquisition techniques
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a small sar imaging system and method based on the back end of general computing equipment, comprising a front end and a back end; the front end is used for transmitting radar signals to a target, receiving target echo signals and acquiring radar motion information; the back end is used for imaging task management and imaging processing of echo signals; the system can be deployed, radar imaging is realized rapidly, the compatibility of the sar imaging system is improved effectively, the sar imaging system has better suitability, the use difficulty of the sar imaging system is reduced, and the use cost is saved.
Description
Technical Field
The invention belongs to the technical field of sar imaging, and particularly relates to a small sar imaging system and method based on the rear end of general computing equipment.
Background
The radar imaging can obtain the distribution of the scattering sources of the targets, and is widely applied to the research of radar wave stealth technology. The commonly used radar imaging method mainly comprises two methods of sar imaging and Isar imaging, the sar imaging irradiates a fixed target area through a radar moving along a certain path (generally linear movement), and a target area image is obtained through radar waveform design and coherent processing.
At present, the sar imaging system uses FPGA and dsp to perform signal processing such as pulse compression, and most of the existing systems are directly connected with a dsp chip, and output results enter a general purpose computer through an i/o bus or a wireless data link.
In the past, the problems of hardware performance and software optimization are limited, and strict environmental requirements are met under the background of main requirements, and most of the existing sar imaging systems mainly use special computing processors, such as DSPs (digital Signal processors), FPGA (field programmable Gate array) chips and the like, for signal processing of sar imaging. The method has the problems of complex development, difficult iteration, expensive equipment, difficult transplanting and the like.
Disclosure of Invention
The invention aims to provide a small-sized sar imaging system and method based on the rear end of general purpose computing equipment, which are used for solving the problems that the existing majority of sar imaging systems provided in the background art mainly use special computing processors, such as DSPs (digital signal processors), FPGA (field programmable gate array) chips and the like for signal processing of sar imaging, and the problems of complex development, difficult iteration, expensive equipment, difficult transplantation and the like.
In order to solve the technical problems, the invention adopts the following technical scheme:
a miniature sar imaging system based on the back end of general computing equipment comprises a front end and a back end, wherein the front end is used for transmitting radar pulse signals to a detection target, receiving echo signals of the detection target and acquiring radar motion information; the back end is used for imaging task management and imaging processing of the echo signals.
According to the technical scheme, the front end comprises a radio frequency module, a servo module, a pos module and an FPGA module; the servo module is used for controlling the rotation of a radar antenna, searching a radar detection target and determining the radar position; the pos module is used for positioning the radar and providing high-precision position, attitude reference and speed information of the radar; the FPGA module is used for connecting the front end and other external equipment; and the PCIE bus is connected with the rear end and used for controlling the servo module and the radio frequency module.
According to the technical scheme, the radio frequency module comprises a transmitter and an acquisition module, the transmitter is used for transmitting pulse signals to the detection target, and the acquisition module is used for acquiring echo signals reflected by the detection target.
According to the technical scheme, the rear end comprises a driving module, a main control module and an imaging module; the main control module comprises a PCIE bus, and the drive module is loaded with a drive for driving the PCIE bus; the main control module is used for calculating and writing radio frequency parameters, servo parameters and imaging parameters, controlling imaging tasks, receiving user instructions, and sending working states and working results; the imaging module is used for processing echo signal imaging data.
A miniature sar imaging method based on the back end of a general purpose computing device, wherein the imaging comprises the following steps:
step S1, a main control program and an imaging process are started, the imaging process defaults to a pending mode, the main control program initializes a shared memory space, and a PCIE bus comprises a file data cache module, a signal data cache module, an imaging parameter cache module, an imaging result cache module and a register module;
step S2, the main control program receives user task parameters, and converts the task parameters through the main control module to obtain application parameters of the servo module and the radio frequency module;
step S3, writing the obtained application parameters of the servo module and the radio frequency module into a register module, reading the application parameters by an FPGA module, driving the servo module to execute the application parameters by the FPGA module after the application parameters of the servo module and the radio frequency module in the register module are read by the FPGA module, enabling the servo module to be aligned with an imaging area, starting a radar and collecting signals;
step S4, the main control program sends an instruction through a pipeline, the imaging process is set into a working mode, and the imaging process starts to intermittently sleep to read a cache state identifier in the shared memory so as to check whether new echo data is written in;
step S5, the FPGA module writes the application parameters and the acquisition signals of the servo module and the radio frequency module into the file data cache module through the PCIE bus;
and S6, the main control program reads the cache identification in the file data cache module, if the cache identification is full, the cache identification is stored into the hard disk through the DMA, and if the cache identification is not changed, the data is continuously read.
Step S7, the imaging process writes the application parameters and imaging parameters of the servo module and the radio frequency module into an imaging parameter buffer module, and invokes an imaging algorithm, wherein the imaging algorithm reads imaging parameters and echo signals from the imaging parameter buffer module, and writes the results into an imaging result buffer module after imaging is executed, and the imaging process reads the imaging result buffer module to obtain imaging results and sends the imaging results to a main control program through a pipeline;
and S8, the main control program reads the pipeline to obtain an imaging result, and the imaging result is forwarded to the user by the Ethernet.
According to the above technical scheme, in step S5, the FPGA module writes the application parameters and the acquisition signals of the servo module and the radio frequency module into the file data buffer module in a ping-pong manner.
Compared with the prior art, the invention has the following beneficial effects:
the system of the invention can ensure that the sar imaging system is not limited by hardware performance and software optimization any more, can be rapidly deployed on a general-purpose computer, and can rapidly realize radar imaging, thereby effectively improving the compatibility of the sar imaging system, ensuring that the sar imaging system has better suitability, reducing the use difficulty of the sar imaging system and saving the use cost.
Drawings
FIG. 1 is a schematic diagram of a system according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 1, a small sar imaging system based on a rear end of a general purpose computing device comprises a front end and a rear end, wherein the front end is used for transmitting radar pulse signals to a detection target, receiving echo signals of the detection target and acquiring radar motion information; the back end is used for imaging task management and imaging processing of the echo signals.
The front end comprises a radio frequency module, a servo module, a pos module and an FPGA module; the servo module is used for controlling the rotation of a radar antenna, searching a radar detection target and determining the radar position; the pos module is used for positioning the radar and providing high-precision position, attitude reference and speed information of the radar; the FPGA module is used for connecting the front end and other external equipment; and the PCIE bus is connected with the rear end and used for controlling the servo module and the radio frequency module.
The radio frequency module comprises a transmitter and an acquisition module, wherein the transmitter is used for transmitting pulse signals to the detection target, and the acquisition module is used for acquiring echo signals reflected by the detection target.
The rear end comprises a driving module, a main control module and an imaging module; the main control module comprises a PCIE bus, and the drive module is loaded with a drive for driving the PCIE bus; the main control module is used for calculating and writing radio frequency parameters, servo parameters and imaging parameters, controlling imaging tasks, receiving user instructions, and sending working states and working results; the imaging module is used for processing echo signal imaging data.
The system of the invention can ensure that the sar imaging system is not limited by hardware performance and software optimization any more, can be rapidly deployed on a general-purpose computer, and can rapidly realize radar imaging, thereby effectively improving the compatibility of the sar imaging system, ensuring that the sar imaging system has better suitability, reducing the use difficulty of the sar imaging system and saving the use cost.
Example two
This embodiment is a further refinement of embodiment one.
A miniature sar imaging method based on the back end of a general purpose computing device, wherein the imaging comprises the following steps:
step S1, a main control program and an imaging process are started, the imaging process defaults to a pending mode, the main control program initializes a shared memory space, and a PCIE bus comprises a file data cache module, a signal data cache module, an imaging parameter cache module, an imaging result cache module and a register module;
step S2, the main control program receives user task parameters, and converts the task parameters through the main control module to obtain application parameters of the servo module and the radio frequency module;
step S3, writing the obtained application parameters of the servo module and the radio frequency module into a register module, reading the application parameters by an FPGA module, driving the servo module to execute the application parameters by the FPGA module after the application parameters of the servo module and the radio frequency module in the register module are read by the FPGA module, enabling the servo module to be aligned with an imaging area, starting a radar and collecting signals;
step S4, the main control program sends an instruction through a pipeline, the imaging process is set into a working mode, and the imaging process starts to intermittently sleep to read a cache state identifier in the shared memory so as to check whether new echo data is written in;
step S5, the FPGA module writes the application parameters and the acquisition signals of the servo module and the radio frequency module into the file data cache module through the PCIE bus;
and S6, the main control program reads the cache identification in the file data cache module, if the cache identification is full, the cache identification is stored into the hard disk through the DMA, and if the cache identification is not changed, the data is continuously read.
Step S7, the imaging process writes the application parameters and imaging parameters of the servo module and the radio frequency module into an imaging parameter buffer module, and invokes an imaging algorithm, wherein the imaging algorithm reads imaging parameters and echo signals from the imaging parameter buffer module, and writes the results into an imaging result buffer module after imaging is executed, and the imaging process reads the imaging result buffer module to obtain imaging results and sends the imaging results to a main control program through a pipeline;
and S8, the main control program reads the pipeline to obtain an imaging result, and the imaging result is forwarded to the user by the Ethernet.
In step S5, the FPGA module writes the application parameters and the acquisition signals of the servo module and the radio frequency module into the file data caching module in a ping-pong mode.
The ping-pong data writing means that the sending module (upper stage) continues to execute and stores the result in the buffer of the ping path without waiting for the end of the processing of the receiving module (lower stage), the upper stage continues to execute until a certain moment, the processing of the lower stage module completes to store the result in the pong path, thus the lower stage module does not need to wait for the execution to continue, the upper stage does not need to wait for the execution to continue, and the data of the result stored in one buffer area is used instead, and the other buffer is used for storing the data.
Further, in step S2, the servo module parameter refers to a servo module orientation, the servo horizontal orientation determines a track angle according to the target point position and the current position of the flight, then the track angle is determined by adding a preset yaw angle to the rotation, the servo pitch angle is given by the user, and the radio frequency parameter refers to an echo signal parameter obtained from a configuration file, such as a signal repetition frequency, a pulse width, and the like.
Example III
The invention is characterized in that: the working process comprises the following steps:
1. the method comprises the steps that an operating system is powered on and started to automatically start a main control program and an imaging process, the imaging process defaults to a pending mode, the main control program initializes a shared memory space, and two file data caching modules comprising a bufferA and a bufferB are opened up in the shared memory space; the two signal data caching modules comprise a bufferC module, a bufferD module, an imaging parameter caching module, an imaging result caching module and a register module.
2. The FPGA module performs system self-checking, and the result is written into a register through a PCIE bus;
3. the main control program reads the specific shared memory address and reports the self-checking state to the user through the Ethernet;
4. after the self-checking is finished, the user sends task parameters through the Ethernet according to the opportunity;
5. the main control program receives the user task parameters, and obtains the application parameters of the servo module and the radio frequency module at the front end after calculation;
6. the application parameters of the servo module and the radio frequency module are written into the register, and are read by the FPGA module autonomously, and the servo module is driven to execute the application parameters, the servo module is aligned to the imaging area, and the radar is started and starts to acquire signals;
7. the main control program sends an instruction through a pipeline, an imaging process is set into a working mode, and the imaging process starts to intermittently sleep to read a cache state identifier in the shared memory;
8. the FPGA module writes application parameters and acquisition signals of the servo module and the radio frequency module into a file data cache buffer A or a buffer B through a PCIE bus, and when the cache mark in the shared memory is full, the FPGA module writes the application parameters and the acquisition signals of the servo module and the radio frequency module into the file data cache module in a ping-pong mode;
9. when the main control program reads the cache mark to be full, the cache mark is stored into a hard disk through DMA, and the stored data is also read in a Ping-Pong mode;
10. the imaging process monitors and stores the catalog state of the BufferA, bufferB data file, and when a new file appears, the file is written into the signal data cache BufferC or bufferD in sequence;
11. the imaging process reads the buffer mark of the bufferC or the bufferD to be full, writes the application parameters, the acquisition signals and the configured default imaging parameters of the servo module and the radio frequency module into the imaging parameter buffer module, calls an imaging algorithm through a system api blocking mode, reads the imaging parameters and the echo signals from the imaging parameter buffer module, performs imaging calculation after the imaging process reads enough echo data, writes the result into the imaging result buffer module after imaging is executed, and then self-destructs. The imaging process destroys the backward blocking in the imaging algorithm, reads the imaging result obtained by the imaging result caching module and sends the imaging result to the main control software through the pipeline;
12. the main control program reads the pipeline to obtain an imaging result, and forwards the imaging graph and the position information of the graph to a user through the Ethernet;
13. the imaging process rewrites the buffer mark of the signal data buffer module to be not full, starts to read the buffer mark of another section of data buffer, reads data in a ping-pong mode, and executes imaging;
14. the user sends a standby instruction through the Ethernet, the main control software writes standby parameters into the register module, the front end stops signal transmission, and signals are acquired and written into by PCIE;
15. the user sends a new imaging task to execute tasks of other parameters;
16. and the user sends a shutdown command, the main control firstly executes a standby instruction, and then invokes the system api to power off and shutdown.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (2)
1. A small-sized sar imaging method based on the back end of general computing equipment is characterized in that: the imaging method is based on an imaging system, the imaging system comprises a front end and a rear end, wherein the front end is used for transmitting radar pulse signals to a detection target, receiving echo signals of the detection target and acquiring radar motion information; the back end is used for imaging task management and imaging processing of the echo signals;
the front end comprises a radio frequency module, a servo module, a pos module and an FPGA module; the servo module is used for controlling the rotation of a radar antenna, searching a radar detection target and determining the radar position; the pos module is used for positioning the radar and providing high-precision position, attitude reference and speed information of the radar; the FPGA module is used for connecting the front end and other external equipment; the PCIE bus is connected with the rear end and is used for controlling the servo module and the radio frequency module;
the radio frequency module comprises a transmitter and an acquisition module, the transmitter is used for transmitting pulse signals to the detection target, and the acquisition module is used for acquiring echo signals reflected by the detection target;
the rear end comprises a driving module, a main control module and an imaging module; the main control module comprises a PCIE bus, and the drive module is loaded with a drive for driving the PCIE bus; the main control module is used for calculating and writing radio frequency parameters, servo parameters and imaging parameters, controlling imaging tasks, receiving user instructions, and sending working states and working results; the imaging module is used for processing echo signal imaging data;
imaging using an imaging system, the imaging comprising the steps of:
step S1, starting a main control program and an imaging process, wherein the imaging process defaults to a pending mode, the main control program initializes a shared memory space, and a PCIE bus comprises a file data cache module, a signal data cache module, an imaging parameter cache module, an imaging result cache module and a register module;
step S2, the main control program receives user task parameters, and converts the task parameters through the main control module to obtain application parameters of the servo module and the radio frequency module;
step S3, writing the obtained application parameters of the servo module and the radio frequency module into a register module, reading the application parameters by an FPGA module, driving the servo module to execute the application parameters by the FPGA module after the application parameters of the servo module and the radio frequency module in the register module are read by the FPGA module, enabling the servo module to be aligned with an imaging area, starting a radar and collecting signals;
step S4, the main control program sends an instruction through a pipeline, the imaging process is set into a working mode, and the imaging process starts to intermittently sleep to read a cache state identifier in the shared memory so as to check whether new echo data is written in;
step S5, the FPGA module writes the application parameters and the acquisition signals of the servo module and the radio frequency module into the file data cache module through the PCIE bus;
step S6, the main control program reads the cache identification in the file data cache module, if the cache identification is full, the cache identification is stored into the hard disk through the DMA, and if the cache identification is not changed, the data is continuously read;
step S7, the imaging process writes the application parameters and imaging parameters of the servo module and the radio frequency module into an imaging parameter buffer module, and invokes an imaging algorithm, wherein the imaging algorithm reads imaging parameters and echo signals from the imaging parameter buffer module, and writes the results into an imaging result buffer module after imaging is executed, and the imaging process reads the imaging result buffer module to obtain imaging results and sends the imaging results to a main control program through a pipeline;
and S8, the main control program reads the pipeline to obtain an imaging result, and the imaging result is forwarded to the user by the Ethernet.
2. The method for imaging a small sar based on a back end of a general purpose computing device according to claim 1, wherein: in step S5, the FPGA module writes the application parameters and the acquisition signals of the servo module and the radio frequency module into the file data caching module in a ping-pong mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310548877.3A CN116299463B (en) | 2023-05-16 | 2023-05-16 | Small sar imaging system and method based on rear end of general computing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310548877.3A CN116299463B (en) | 2023-05-16 | 2023-05-16 | Small sar imaging system and method based on rear end of general computing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116299463A CN116299463A (en) | 2023-06-23 |
| CN116299463B true CN116299463B (en) | 2023-08-08 |
Family
ID=86803490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310548877.3A Active CN116299463B (en) | 2023-05-16 | 2023-05-16 | Small sar imaging system and method based on rear end of general computing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116299463B (en) |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102590811A (en) * | 2012-01-13 | 2012-07-18 | 西安电子科技大学 | Small FMCW-based (frequency modulated continuous wave) SAR (synthetic aperture radar) imaging system by using FPGA (field programmable gate array) |
| CN103869292A (en) * | 2014-04-02 | 2014-06-18 | 清华大学 | General purpose radar imaging processing system based on embedded GPU |
| CN104471443A (en) * | 2012-05-17 | 2015-03-25 | 深层成像技术有限公司 | A system and method using near and far field ulf and elf interferometry synthetic aperture radar for subsurface imaging |
| CN107229051A (en) * | 2017-05-26 | 2017-10-03 | 西安电子科技大学 | Video SAR echo simulation Parallel Implementation methods based on GPU |
| CN108051786A (en) * | 2017-10-30 | 2018-05-18 | 北京航天福道高技术股份有限公司 | A kind of broadband target simulator verification platform and verification method |
| CN108958638A (en) * | 2017-05-18 | 2018-12-07 | 中国科学院电子学研究所 | Ultrahigh speed SAR data recorder and data record method |
| CN110133650A (en) * | 2019-05-24 | 2019-08-16 | 电子科技大学 | A kind of short distance rcs measurement electronic system based on step frequency synthetic aperture radar |
| KR102156253B1 (en) * | 2019-10-01 | 2020-09-15 | 엘아이지넥스원 주식회사 | Method and system for estimating precise altitude information using SAR mounted on multi unmanned aerial vehicles |
| CN113359134A (en) * | 2021-06-07 | 2021-09-07 | 西安电子科技大学 | SAR data distributed real-time imaging processing system and method based on embedded GPU |
| CN113885028A (en) * | 2021-09-18 | 2022-01-04 | 西安电子科技大学 | Multi-server multi-GPU-based satellite-borne SAR imaging real-time processing method |
| CN114167436A (en) * | 2021-11-22 | 2022-03-11 | 桂林理工大学 | Single-frequency water measuring laser radar |
| EP4099055A1 (en) * | 2021-05-31 | 2022-12-07 | Nokia Technologies Oy | Synthetic aperture imaging |
| CN115687228A (en) * | 2023-01-03 | 2023-02-03 | 中国科学院国家空间科学中心 | Satellite-borne solid-state storage system and method based on PCIe bus |
| WO2023015067A2 (en) * | 2021-06-25 | 2023-02-09 | Northeastern University | Millimeter-wave massive mmo fmcw radar with binary-phase-coded ofdm |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3499807B1 (en) * | 2017-12-12 | 2020-06-03 | Nxp B.V. | Reconfigurable ethernet receiver and an analog front-end circuit thereof |
| US11609305B2 (en) * | 2019-12-27 | 2023-03-21 | Intel Corporation | Online radar phase calibration through static environment measurements |
| US20220318162A1 (en) * | 2021-03-30 | 2022-10-06 | Micron Technology, Inc. | Interpolation acceleration in a processor memory interface |
| US11802957B2 (en) * | 2021-03-30 | 2023-10-31 | Micron Technology, Inc. | Increasing cache hits for synthetic aperture radar |
-
2023
- 2023-05-16 CN CN202310548877.3A patent/CN116299463B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102590811A (en) * | 2012-01-13 | 2012-07-18 | 西安电子科技大学 | Small FMCW-based (frequency modulated continuous wave) SAR (synthetic aperture radar) imaging system by using FPGA (field programmable gate array) |
| CN104471443A (en) * | 2012-05-17 | 2015-03-25 | 深层成像技术有限公司 | A system and method using near and far field ulf and elf interferometry synthetic aperture radar for subsurface imaging |
| CN103869292A (en) * | 2014-04-02 | 2014-06-18 | 清华大学 | General purpose radar imaging processing system based on embedded GPU |
| CN108958638A (en) * | 2017-05-18 | 2018-12-07 | 中国科学院电子学研究所 | Ultrahigh speed SAR data recorder and data record method |
| CN107229051A (en) * | 2017-05-26 | 2017-10-03 | 西安电子科技大学 | Video SAR echo simulation Parallel Implementation methods based on GPU |
| CN108051786A (en) * | 2017-10-30 | 2018-05-18 | 北京航天福道高技术股份有限公司 | A kind of broadband target simulator verification platform and verification method |
| CN110133650A (en) * | 2019-05-24 | 2019-08-16 | 电子科技大学 | A kind of short distance rcs measurement electronic system based on step frequency synthetic aperture radar |
| KR102156253B1 (en) * | 2019-10-01 | 2020-09-15 | 엘아이지넥스원 주식회사 | Method and system for estimating precise altitude information using SAR mounted on multi unmanned aerial vehicles |
| EP4099055A1 (en) * | 2021-05-31 | 2022-12-07 | Nokia Technologies Oy | Synthetic aperture imaging |
| CN113359134A (en) * | 2021-06-07 | 2021-09-07 | 西安电子科技大学 | SAR data distributed real-time imaging processing system and method based on embedded GPU |
| WO2023015067A2 (en) * | 2021-06-25 | 2023-02-09 | Northeastern University | Millimeter-wave massive mmo fmcw radar with binary-phase-coded ofdm |
| CN113885028A (en) * | 2021-09-18 | 2022-01-04 | 西安电子科技大学 | Multi-server multi-GPU-based satellite-borne SAR imaging real-time processing method |
| CN114167436A (en) * | 2021-11-22 | 2022-03-11 | 桂林理工大学 | Single-frequency water measuring laser radar |
| CN115687228A (en) * | 2023-01-03 | 2023-02-03 | 中国科学院国家空间科学中心 | Satellite-borne solid-state storage system and method based on PCIe bus |
Non-Patent Citations (1)
| Title |
|---|
| 刘海文.毫米波SAR信号采集与成像关键技术的研究与实现.中国优秀硕士学位论文全文数据库信息科技辑.2023,正文第15-16页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116299463A (en) | 2023-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109946666B (en) | Millimeter wave radar signal processing system based on MPSoC | |
| US9632173B2 (en) | Method, device and system for processing radar signals | |
| CN105760311B (en) | Trim command response method and system and operating system | |
| CN101414252B (en) | Data processing apparatus | |
| CN215180868U (en) | Long-distance and multi-target millimeter wave radar signal processing platform based on MPSOC | |
| CN116299463B (en) | Small sar imaging system and method based on rear end of general computing device | |
| US20090138628A1 (en) | Multi-bus architecture for mass storage system-on-chip controllers | |
| CN110068809A (en) | A kind of wave control processing module for phased-array radar | |
| CN105676197A (en) | Array radar echo simulator and simulation method thereof | |
| CN110727634A (en) | Embedded intelligent computer framework facing to object side data processing | |
| CN112731302A (en) | STM32 and FPGA-based reverse radar signal processing system and method | |
| CN105389268B (en) | Data storage system and its operation method | |
| CN202217051U (en) | LFMCW radar system | |
| CN105974365A (en) | Universal processing platform for radar signals | |
| CN116482725B (en) | Open satellite navigation baseband signal processing method, device and receiver | |
| CN113255254A (en) | DSP and ZYNQ architecture controller and data transmission design method | |
| CN110825687B (en) | Dual-mode tracking method based on DSP multi-core architecture | |
| CN107729269A (en) | A kind of NANDFlash to FPGA internal blocks RAM caching method | |
| CN105573190A (en) | Wave beam control system | |
| CN103577110A (en) | System on chip and read-write method thereof | |
| CN110554974B (en) | Method for increasing running multiple of full-digital satellite attitude and orbit control software running platform | |
| CN106680777A (en) | Apparatus used for carrying out partial acquisition on radar echo data and method thereof | |
| CN113311421A (en) | Target high-precision on-satellite real-time positioning resolving system | |
| CN113625934B (en) | Efficient annular cache ADC acquisition method | |
| CN217690050U (en) | FPGA program dynamic loading device and satellite signal acquisition preprocessing board card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |