CN116264769A - 具有嵌入于栅极沟槽中的字线的半导体装置 - Google Patents

具有嵌入于栅极沟槽中的字线的半导体装置 Download PDF

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CN116264769A
CN116264769A CN202211596922.4A CN202211596922A CN116264769A CN 116264769 A CN116264769 A CN 116264769A CN 202211596922 A CN202211596922 A CN 202211596922A CN 116264769 A CN116264769 A CN 116264769A
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polysilicon film
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藤本稔泰
松本義弘
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Micron Technology Inc
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Abstract

本公开涉及具有嵌入于栅极沟槽中的字线的半导体装置。本文中公开一种设备，其包含半导体衬底，其具有源极/漏极区和位于所述源极/漏极区之间的栅极沟槽；和栅电极，其经由栅极绝缘膜嵌入于所述栅极沟槽中。所述栅电极包含位于所述栅极沟槽的底部的第一多晶硅膜和堆叠于所述第一多晶硅膜上的金属膜。所述第一多晶硅膜掺杂有硼。

Description

具有嵌入于栅极沟槽中的字线的半导体装置
技术领域
本公开涉及半导体装置，且特定来说，涉及具有嵌入于栅极沟槽中的字线的半导体装置。
背景技术
用于半导体存储器装置(例如DRAM)中的一些单元晶体管具有其中含有金属材料的栅电极嵌入于栅极沟槽中的配置。单元晶体管的GIDL近年来一直都有问题，需要降低GIDL。
发明内容
在一个方面中，本公开涉及一种设备，其包括：半导体衬底，其具有源极/漏极区和位于所述源极/漏极区之间的栅极沟槽；和栅电极，其经由栅极绝缘膜嵌入于所述栅极沟槽中，其中所述栅电极包含位于所述栅极沟槽的底部的第一多晶硅膜和堆叠于所述第一多晶硅膜上的金属膜，且其中所述第一多晶硅膜掺杂有硼。
在另一方面中，本公开涉及一种设备，其包括：半导体衬底，其具有源极/漏极区和位于所述源极/漏极区之间的栅极沟槽；和栅电极，其经由栅极绝缘膜嵌入于所述栅极沟槽中，其中所述栅电极包含位于所述栅极沟槽底部的的第一导电膜、堆叠于所述第一导电膜上的第二导电膜和堆叠于所述第二导电膜上的第三导电薄膜，且其中所述第二导电膜的逸出功低于所述第一导电膜的逸出功且高于所述第三导电薄膜的逸出功。
在又一方面中，本公开涉及一种方法，其包括：在半导体衬底中形成栅极沟槽；用栅极绝缘膜覆盖所述栅极沟槽的内壁；和经由所述栅极绝缘膜在所述栅极沟槽中嵌入栅电极，其中所述嵌入所述栅电极包含：在所述栅极沟槽的底部形成掺杂有硼的多晶硅膜；在所述掺杂有硼的多晶硅膜上形成金属膜；和在所述金属膜上形成掺杂有磷的多晶硅膜。
附图说明
图1是示出根据本公开的实施例的半导体存储器装置的一部分的示意性平面视图；
图2是示出根据本公开的实施例的半导体存储器装置的一部分的示意性透视图；
图3是表示沟道的深度与电场之间的关系的图表；
图4A到4C是表示当单元晶体管断开时字线的电势与关联于相邻字线的接通和关断的阈值电压、接通电流和电荷增益当中的关系的图表；
图5A到12A是用于解释根据本公开的实施例的半导体存储器装置的制造工艺的示意性平面视图；
图5B到12B是沿着图5A到12A中分别示出的线B-B的示意性截面视图；和
图5C到12C是沿着图5A到12A中分别示出的线C-C的示意性截面视图。
具体实施方式
下文将参考附图详细地解释本公开的各种实施例。以下详细描述参考附图，借助于图示来展示本公开的特定方面和各种实施例。所述详细描述提供使所属领域的技术人员能够实践本公开的这些实施例的足够细节。在不脱离本公开的范围的情况下可以利用其它实施例，且可以做出结构、逻辑和电改变。本文所公开的各种实施例不一定相互排斥，因为一些所公开的实施例可与一或多个其它所公开的实施例组合以形成新的实施例。
图1和2分别是示出根据本公开的实施例的半导体存储器装置的一部分的示意性平面视图和示意性透视图。根据本公开的半导体存储器装置是DRAM并且包含通过STI区2分割的多个有源区10、沿X方向与有源区10交叉的多个字线20，以及沿Y方向与有源区10交叉的多个位线41。有源区10是的一部分。字线20中的两个沿X方向与有源区10中的每一个交叉。以此方式，每一有源区10划分成三个源极/漏极区。中心源极/漏极区通过位触点31连接到位线41中的对应位线。位于两侧上源极/漏极区中的两个分别通过单元触点32连接到对应单元电容器42。
如图2所示，栅极沟槽13形成于有源区10中以沿X方向延伸。源极/漏极区11和12沿Y方向设置在栅极沟槽13的两侧上。栅极沟槽13的内壁覆盖有由例如氧化硅制成的栅极绝缘膜14。充当栅电极的字线20经由栅极绝缘膜14嵌入于栅极沟槽13中。字线20由位于栅极沟槽13的底部的多晶硅膜21、堆叠于多晶硅膜21上的金属膜22和堆叠于金属膜22上的多晶硅膜23形成。由例如氮化硅制成的栅极帽绝缘膜24设置于多晶硅膜23上方。多晶硅膜21掺杂有硼，且因此其导电类型是P型。同时，多晶硅膜23掺杂有磷，且因此其导电类型是N型。金属膜22由例如氮化钛制成。在此配置下，当预先确定的接通电势施加到字线20时环绕栅极沟槽13形成沟道，使得源极/漏极区11和12彼此电连接。
多晶硅膜23的材料的逸出功约为4.1，且因此多晶硅膜23松弛施加到沟道的上部区的电场以减小GIDL。因此，关断泄漏电流减小，进而使得刷新特性改进。另外，金属膜22使得字线20的电阻为低。金属膜22的材料的逸出功为约4.5到约4.7。因此，金属膜22防止单元晶体管的阈值电压过度下降，进而减小关断泄漏电流。多晶硅膜21的材料的逸出功为约5.2。因此，多晶硅膜21松弛施加到沟道的下部区的电场以减小GIDL。如上文所描述，在本发明的实施例中，具有大逸出功的多晶硅膜21位于栅极沟槽13的底部，与多晶硅膜21相比具有较小逸出功和较低电阻值的金属膜22位于多晶硅膜21上，且与金属膜22相比具有较小逸出功的多晶硅膜23位于金属膜22上。因此，有可能使工作线20的电阻为低并且减小单元晶体管的关断泄漏电流。优选的是，多晶硅膜23比多晶硅膜21厚，且金属硅膜22比多晶硅膜23厚以便足够地获得上文所描述的效应。多晶硅膜21的厚度可设置为15nm。
图3示出沟道的深度与电场之间的关系的图表。在图3中，实线表示本发明的实施例中的一实施例中的特性，且虚线表示在其中省略多晶硅膜21的情况下的特性。从图3发现，在本发明的实施例中，电场在120nm或更大的深度处松弛。图4A到4C示出当单元晶体管断开时字线20的电势Vnwl与关联于相邻字线20的接通和关断的阈值电压Vt、接通电流Ion和电荷增益当中的关系的图表。在图4A到4C中，附图标记A0、B0和C0表示在其中多晶硅膜21的厚度为零的情况下的特性，附图标记A15、B15和C15表示在其中多晶硅膜21为15nm的情况下的特性，且附图标记A25、B25和C25表示在其中多晶硅膜21的厚度为25nm的情况下的特性。如图4A所示，往往会通过设置多晶硅膜21来增加单元晶体管的阈值电压Vt。因此，为了在设置了多晶硅膜21的同时降低阈值电压Vt，使得在单元晶体管关断的情况下字线20的电势Vnwl更靠近0V。如图4B中所示，往往会通过设置多晶硅膜21来减小单元晶体管的接通电流Ion。因此，为了在设置了多晶硅膜21的同时获得足够的接通电流Ion，使得在单元晶体管关断的情况下字线20的电势Vnwl更靠近0V。相比于其中不设置多晶硅膜21的情况，如图4C中所示，当使得在单元晶体管关断的情况下字线20的电势Vnwl更靠近0V时，与相邻字线20的接通和关断相关联的电荷增益很大程度地减小。因此，大大改进行锤击特性。
接下来，描述根据本公开的实施例的半导体存储器装置的制造工艺。第一，如图5A到5C中所示，通过使用由例如氧化硅制成的硬掩模4蚀刻半导体衬底来形成有源区10，并且接着在有源区10之间的空间中嵌入由例如氧化硅制成的STI区2。随后，形成沿X方向延伸的栅极沟槽13。每一有源区10被指配有栅极沟槽13中的两个。接下来，通过热氧化在栅极沟槽13的内壁上形成由氧化硅制成的栅极绝缘膜14。随后，如图6A到6C中所示，在整个表面上沉积掺杂有硼的多晶硅膜21a，借此栅极沟槽13中嵌入有掺杂有硼的多晶硅膜21a。如图7A到7C中所示，随后回蚀刻掺杂有硼的多晶硅膜21a，使得多晶硅膜21保留在栅极沟槽13的底部与有源区10交叉。将保留的多晶硅膜21的厚度控制为约15nm。
接下来，如图8A到8C中所示，在整个表面上沉积由例如氮化钛制成的金属膜22a，借此在栅极沟槽13中嵌入金属膜22a。随后回蚀刻金属膜22a，使得金属膜22保留在位于栅极沟槽13的底部的多晶硅膜21上，如图9A到9C中所示。随后，如图10A到10C中所示，在整个表面上沉积经磷掺杂的多晶硅膜23a，借此在栅极沟槽13中嵌入掺杂有磷的多晶硅膜23a。随后回蚀刻掺杂有磷的多晶硅膜23a，使得多晶硅膜23保留在栅极沟槽13中的金属膜22上，如图11A到11C中所示。接下来，如图12A到12C中所示，在整个表面上沉积由例如氮化硅制成的栅极帽绝缘膜24，借此栅极沟槽13被完全嵌入。此后，依序执行位触点31和单元触点32的形成、位线41的形成、单元电容器42的形成等等。以此方式，根据本发明的实施例的半导体存储器装置完成。
虽然已在特定优选实施例和实例的上下文中公开各种实施例，但所属领域的技术人员将理解，本公开的范围超出具体公开的实施例，扩展到其它替代性实施例且/或使用实施例和其明显的变体和等同方案。另外，基于本公开，在本公开的范围内的其它修改对于所属领域的技术人员将是显而易见的。还预期可进行实施例的具体特征和方面的各种组合或子组合且仍然落入本公开的范围内。应理解，所公开的实施例的各种特征和方面可彼此组合或替代彼此以便形成所公开实施例的变化模式。因此，希望本公开中的至少一些的范围不应受上文所描述的特定所公开实施例的限制。

Claims (20)

1.一种设备，其包括：
半导体衬底，其具有源极/漏极区和位于所述源极/漏极区之间的栅极沟槽；和
栅电极，其经由栅极绝缘膜嵌入于所述栅极沟槽中，
其中所述栅电极包含位于所述栅极沟槽的底部的第一多晶硅膜和堆叠于所述第一多晶硅膜上的金属膜，且
其中所述第一多晶硅膜掺杂有硼。
2.根据权利要求1所述的设备，其中所述金属膜包括氮化钛。
3.根据权利要求2所述的设备，其中所述栅电极另外包含堆叠于所述金属膜上的第二多晶硅膜。
4.根据权利要求3所述的设备，其中所述第二多晶硅膜在导电类型上不同于所述第一多晶硅膜。
5.根据权利要求4所述的设备，其中所述第二多晶硅膜掺杂有磷。
6.根据权利要求5所述的设备，其中所述第一多晶硅膜比所述金属膜薄。
7.根据权利要求6所述的设备，其中所述第一多晶硅膜比所述第二多晶硅膜薄。
8.根据权利要求7所述的设备，其中所述第二多晶硅膜比所述金属膜薄。
9.根据权利要求1所述的设备，其另外包括：
位线，其耦合到所述源极/漏极区中的一个；和
单元电容器，其耦合到所述源极/漏极区中的另一个。
10.一种设备，其包括：
半导体衬底，其具有源极/漏极区和位于所述源极/漏极区之间的栅极沟槽；和
栅电极，其经由栅极绝缘膜嵌入于所述栅极沟槽中，
其中所述栅电极包含位于所述栅极沟槽底部的的第一导电膜、堆叠于所述第一导电膜上的第二导电膜和堆叠于所述第二导电膜上的第三导电薄膜，且
其中所述第二导电膜的逸出功低于所述第一导电膜的逸出功且高于所述第三导电薄膜的逸出功。
11.根据权利要求10所述的设备，其中所述第二导电膜包括金属材料。
12.根据权利要求11所述的设备，其中所述第二导电膜包括氮化钛。
13.根据权利要求11所述的设备，其中所述第一和第三导电膜包括掺杂有彼此不同的杂质的多晶硅。
14.根据权利要求13所述的设备，其中所述第一导电膜掺杂有硼。
15.根据权利要求14所述的设备，其中所述第三导电薄膜掺杂有磷。
16.一种方法，其包括：
在半导体衬底中形成栅极沟槽；
用栅极绝缘膜覆盖所述栅极沟槽的内壁；和
经由所述栅极绝缘膜在所述栅极沟槽中嵌入栅电极，其中所述嵌入所述栅电极包含：
在所述栅极沟槽的底部形成掺杂有硼的多晶硅膜；
在所述掺杂有硼的多晶硅膜上形成金属膜；和
在所述金属膜上形成掺杂有磷的多晶硅膜。
17.根据权利要求16所述的方法，其中所述形成所述掺杂有硼的多晶硅膜包含用所述掺杂有硼的多晶硅膜填充所述栅极沟槽并且回蚀刻所述掺杂有硼的多晶硅膜。
18.根据权利要求17所述的方法，其中所述形成所述金属膜包含用所述金属膜填充所述栅极沟槽并且回蚀刻所述金属膜。
19.根据权利要求18所述的方法，其中所述形成所述掺杂有磷的多晶硅膜包含用所述掺杂有磷的多晶硅膜填充所述栅极沟槽并且回蚀刻所述掺杂有磷的多晶硅膜以便在所述栅极沟槽的上部区处形成空间。
20.根据权利要求19所述的方法，其另外包括用绝缘材料填充所述空间。
CN202211596922.4A 2021-12-13 2022-12-12 具有嵌入于栅极沟槽中的字线的半导体装置 Pending CN116264769A (zh)

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