CN116246566B - Display panel and electronic equipment - Google Patents
Display panel and electronic equipment Download PDFInfo
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- CN116246566B CN116246566B CN202310113691.5A CN202310113691A CN116246566B CN 116246566 B CN116246566 B CN 116246566B CN 202310113691 A CN202310113691 A CN 202310113691A CN 116246566 B CN116246566 B CN 116246566B
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- 208000032005 Spinocerebellar ataxia with axonal neuropathy type 2 Diseases 0.000 description 3
- 208000033361 autosomal recessive with axonal neuropathy 2 spinocerebellar ataxia Diseases 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
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- 230000001276 controlling effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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Abstract
The application provides a display panel and electronic equipment, wherein the display panel comprises a plurality of scanning lines extending along a first direction, a plurality of data lines extending along a second direction, a plurality of pixel units defined by the intersection of the scanning lines and the data lines, a plurality of driving circuits and a plurality of selection circuits, the pixel units are respectively and electrically connected with the data lines and the scanning lines through corresponding driving circuits, each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel and the second sub-pixel are alternately arranged at intervals along the second direction and are electrically connected with the same data line, the third sub-pixel is alternately arranged along the second direction and is electrically connected with the data line adjacent to the data line electrically connected with the first sub-pixel and the second sub-pixel, and the selection circuits are electrically connected with the corresponding scanning lines and are used for selecting scanning signals or switching off signals to be transmitted on the corresponding scanning lines according to first control signals or selecting the scanning signals or switching off signals to be transmitted on the corresponding scanning lines according to second control signals.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel and an electronic device.
Background
Display technology has long been one of the important research directions in electronic devices. At present, when the display panel performs black display, that is, when the display panel is in a state of zero gray scale, if the voltages required to be charged by two pixels on the same data line are different, there will be a voltage variation on the data line, and because the data line in the display panel usually has parasitic capacitance, the voltage variation will generate unnecessary power consumption through the parasitic capacitance, so as to cause power consumption loss.
Disclosure of Invention
The application discloses a display panel, which can solve the technical problem of unnecessary power consumption and power consumption loss caused by the fact that the display panel performs black display.
In a first aspect, the present application provides a display panel, the display panel including a plurality of scan lines extending in a first direction, a plurality of data lines extending in a second direction, a plurality of pixel units defined by intersections of the scan lines and the data lines, and a plurality of driving circuits, the pixel units being electrically connected to the data lines and the scan lines, respectively, through the corresponding driving circuits, the pixel units including first sub-pixels, second sub-pixels, and third sub-pixels, the first sub-pixels and the second sub-pixels being alternately arranged at intervals in the second direction and electrically connected to the same data line, and the third sub-pixels being arranged at intervals in the second direction and electrically connected to the data lines adjacent to the data lines electrically connected to the first sub-pixels and the second sub-pixels, the display panel further including a plurality of selection circuits electrically connected to the corresponding scan lines, for selecting a scan signal or a turn-off signal on the corresponding scan lines according to a first control signal or a turn-off signal or selecting the scan signal on the corresponding scan lines according to the control signal or the turn-off signal.
The selection circuit selects the scanning signal or the closing signal to transmit on the corresponding scanning line, so that the driving circuit of the corresponding row can be closed, the data line cannot charge the pixel units of the corresponding row, frequent changes of voltage signals transmitted on the data line are reduced, power consumption caused by parasitic capacitance on the data line is reduced, power consumption loss is reduced, and power consumption loss of the display panel is reduced.
Optionally, the selection circuit selects the scan signal or the off signal to be transmitted on the scan line of the odd-numbered row according to the first control signal, and the selection circuit selects the scan signal or the off signal to be transmitted on the scan line of the even-numbered row according to the second control signal.
Optionally, the selection circuit includes a first transistor and a second transistor, where a gate of the first transistor is electrically connected to a gate of the second transistor, and is configured to receive the first control signal or the second control signal, a source of the first transistor is configured to receive the scan signal, and a drain of the first transistor is electrically connected to a drain of the second transistor and the scan line; the source of the second transistor is used for receiving the closing signal.
Optionally, the first transistor is PMOS, and the second transistor is NMOS; or the first transistor is NMOS, and the second transistor is PMOS.
Optionally, the display panel further includes a control circuit, the control circuit controls the voltage values of the first control signal and the second control signal according to a first display signal, so that the first transistor is turned on under the control of the first control signal and the second transistor is turned off under the control of the first control signal in an X frame time; the first transistor is turned off under the control of the second control signal, and the second transistor is turned on under the control of the second control signal.
Optionally, the control circuit controls the voltage values of the first control signal and the second control signal according to a first display signal, so that the first transistor is turned off under the control of the first control signal and the second transistor is turned on under the control of the first control signal in the Y frame time; the first transistor is turned on under the control of the second control signal, and the second transistor is turned off under the control of the second control signal, wherein the value of X is equal to the value of Y, and the X frame and the Y frame are continuous frames.
Optionally, the control circuit controls the voltage values of the first control signal and the second control signal according to a second display signal, the first transistor is turned on under the control of the first control signal, and the second transistor is turned off under the control of the first control signal; the first transistor is turned on under the control of the second control signal, and the second transistor is turned off under the control of the second control signal.
Optionally, the driving circuit includes a driving transistor, when the driving transistor is a PMOS, the off signal has a first voltage value, and when the driving transistor is an NMOS, the off signal has a second voltage value, where the first voltage value is greater than the second voltage value.
Optionally, the display panel further includes a first scan driving circuit and a second scan driving circuit, where the first scan driving circuit and the second scan driving circuit are electrically connected to two ends of the scan line, respectively, and are used for generating the scan signal.
In a second aspect, the present application further provides an electronic device, where the electronic device includes a housing and the display panel according to the first aspect, and the housing is used to carry the display panel.
Drawings
For a clearer description of the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a display panel according to an embodiment of the application.
Fig. 2 is a schematic diagram of a possible waveform of a data signal in the related art.
Fig. 3 is a schematic diagram of signal waveforms according to an embodiment of the present application.
Fig. 4 is a schematic signal waveform diagram according to another embodiment of the present application.
Fig. 5 is a schematic diagram of signal waveforms according to another embodiment of the present application.
Fig. 6 is a schematic top view of an electronic device according to an embodiment of the application.
Reference numerals illustrate: the display panel-1, the first direction-D1, the scan line-11, the second direction-D2, the data line-12, the pixel unit-13, the first sub-pixel-131, the second sub-pixel-132, the third sub-pixel-133, the driving circuit-14, the selection circuit-15, the first transistor-T1, the second transistor-T2, the gate-g, the drain-D, the source-s, the control circuit-16, the first scan driving circuit-17, the second scan driving circuit-18, the electronic device-2, and the housing-21.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of a display panel according to an embodiment of the application. The display panel 1 includes a plurality of scan lines 11 extending along a first direction D1, a plurality of data lines 12 extending along a second direction D2, a plurality of pixel units 13 defined by the scan lines 11 and the data lines 12 intersecting each other, and a plurality of driving circuits 14, the pixel units 13 are electrically connected to the data lines 12 and the scan lines 11 through the corresponding driving circuits 14, respectively, the pixel units 13 include a first sub-pixel 131, a second sub-pixel 132, and a third sub-pixel 133, the first sub-pixel 131 and the second sub-pixel 132 are alternately arranged at intervals along the second direction D2 and are electrically connected to the same data line 12, the third sub-pixel 133 is arranged at intervals along the second direction D2 and is electrically connected to the data line 12 adjacent to the data line 12 electrically connected to the first sub-pixel 131 and the second sub-pixel 132, the display panel 1 further includes a plurality of selection circuits 15, the selection circuits 15 are electrically connected to the corresponding scan lines 11, and the scanning lines are alternately turned off or turned on according to a control signal, and the scanning signal is turned off according to a control signal applied to the first or the scanning signal is turned off according to the control signal transmission of the scanning signal 11.
Note that, the first sub-pixel 131, the second sub-pixel 132, and the third sub-pixel 133 may be a red color pixel, a blue color pixel, and a green color pixel, respectively. The scan signal is transmitted on the corresponding scan line 11, so as to control the driving circuit 14 to be turned on, so that the data signal transmitted on the data line 12 can be transmitted to the corresponding pixel unit 13 through the driving circuit 14, so as to charge the corresponding pixel unit 13, and the other side of the pixel unit 13 is generally used for receiving a common voltage signal, thereby realizing the picture display function of the display panel 1. In general, due to circuit design, parasitic capacitance exists on the data line 12, and when the voltage value of the data signal transmitted on the data line 12 changes, a calculation formula of capacitance power consumption is calculated according to the following formula:
wherein W is the power consumption of the capacitor, f is the switching frequency of the voltage value of the data signal, Is the voltage variation value of the data signal. It can be seen that the capacitive power consumption is positively correlated to the switching frequency and the voltage variation value of the voltage value of the data signal.
For example, referring to fig. 2 together, fig. 2 is a schematic diagram of a possible waveform of a data signal in the related art. Wherein H is the inverse of the switching frequency of the voltage value of the data signal, i.e., h=1/f. In the related art, when the display panel 1 performs black display, that is, when displaying a frame with zero gray scale, since the first sub-pixel 131 and the second sub-pixel 132 are alternately arranged at intervals along the second direction D2 and are electrically connected to the same Data line 12, as shown in fig. 2, data1 is the waveform of the Data signal charged by the first sub-pixel 131 and the second sub-pixel 132, and needs to be switched every other line; data2 is the waveform of the Data signal charged to the third subpixel 131. Therefore, according to the calculation formula of the capacitance power consumption, the parasitic capacitance on the data line 12 will generate larger capacitance power consumption, and the power consumption generated by the parasitic capacitance on the data line 12 is unnecessary power consumption.
In this embodiment, since the selection circuit 15 is electrically connected to the scan line 11, the scan signal or the off signal can be selected to be transmitted on the scan line 11 according to the first control signal or the second control signal, so as to switch on or off the driving circuit 14, so as to control whether the data signal transmitted on the data line 12 charges the pixel units 13 of the corresponding row, thereby reducing the switching frequency of the data signal.
For example, when the display panel 1 performs black display, since the data signals for charging the first sub-pixel 131 and the second sub-pixel 132 need to be switched once every other line, the selection circuit 15 may select the scan signal to be transmitted to the driving circuit 14 electrically connected to the first sub-pixel 131 according to the first control signal in one frame or several consecutive frame times, so as to turn on the driving circuit 14, so that the data signal charges the first sub-pixel 131, and select the off signal to be transmitted to the driving circuit 14 electrically connected to the second sub-pixel 132 according to the second control signal, so as to turn off the driving circuit 14, thereby avoiding the data signal from charging the second sub-pixel 132. In this way, the voltage value of the data signal does not change during one frame or several consecutive frames. At the same frame time, the selection circuit 15 selects the turn-off signal according to the first control signal to be transmitted to the driving circuit 14 electrically connected to the first sub-pixel 131, so as to turn off the driving circuit 14, avoid the data signal from charging the first sub-pixel 131, and select the scan signal according to the second control signal to be transmitted to the driving circuit 14 electrically connected to the second sub-pixel 132, so as to turn on the driving circuit 14, and enable the data signal to charge the second sub-pixel 132, thereby realizing that the data signal charges the first sub-pixel 131 and the second sub-pixel 132 at different frame times, respectively, and avoiding frequent switching of the voltage value of the data signal.
It will be appreciated that the switching frequency of the voltage value of the data signal is reduced from that of the related art once per row to that of once per frame or every few frames, thereby greatly reducing the switching frequency of the voltage value of the data signal and thus reducing the power consumption of the parasitic capacitance on the data line 12.
It can be appreciated that in this embodiment, since the selection circuit 15 selects the scan signal or the off signal to be transmitted on the corresponding scan line 11, the driving circuit 14 of the corresponding row can be turned off, so that the data line 12 cannot charge the pixel unit 13 of the corresponding row, thereby reducing frequent changes of the voltage signal transmitted on the data line 12, reducing power consumption generated by parasitic capacitance on the data line 12, and reducing power consumption loss of the display panel 1.
In a possible implementation, referring to fig. 1 again, the selection circuit 15 selects the scan signal or the off signal to be transmitted on the scan line 11 in the odd-numbered row according to the first control signal, and the selection circuit 15 selects the scan signal or the off signal to be transmitted on the scan line 11 in the even-numbered row according to the second control signal.
Specifically, the arrangement manner of the pixel units 13 is that the first sub-pixels 131 and the second sub-pixels 132 are alternately arranged at intervals along the second direction D2 and are electrically connected to the same data line 12, so that the first sub-pixels 131 and the second sub-pixels 132 are respectively located on the scan lines 11 of the odd-numbered rows and the even-numbered rows. It will be appreciated that the first sub-pixel 131 may be located on the scan line 11 of the odd-numbered row, and the second sub-pixel 132 may be located on the scan line 11 of the even-numbered row; the first sub-pixel 131 may be located on the scan line 11 of the even-numbered row, and the second sub-pixel 132 may be located on the scan line 11 of the odd-numbered row, which is not limited in the present application.
In this embodiment, the first sub-pixel 131 is located on the scan line 11 in the odd-numbered row, the second sub-pixel 132 is located on the scan line 11 in the even-numbered row, the selection circuit 15 selects a scan signal or a close signal according to a first control signal to transmit on the scan line 11 in the odd-numbered row, and the selection circuit 15 selects the scan signal or the close signal according to a second control signal to transmit on the scan line 11 in the even-numbered row, thereby realizing that the data signals respectively charge the first sub-pixel 131 and the second sub-pixel 132 in different frame times, and avoiding frequent switching of the voltage values of the data signals.
It will be appreciated that in other possible embodiments, the selection circuit 15 may control a part of the driving circuits 14 to be turned on and a part of the driving circuits 14 to be turned off according to the first control signal and the second control signal, respectively, in the same frame time, so as to realize that the data signal charges a part of the first sub-pixels 131 and a part of the second sub-pixels 132, and may also reduce the switching frequency of the voltage signal transmitted on the data line 12. Therefore, the present application does not limit the arrangement of the selection circuit 15 and the pixel unit 13 as long as the selection circuit 15 is not affected to reduce the switching frequency of the voltage signal transmitted on the data line 12.
In one possible implementation, referring to fig. 1 again, the selection circuit 15 includes a first transistor T1 and a second transistor T2, where a gate g of the first transistor T1 is electrically connected to a gate g of the second transistor T2, for receiving the first control signal or the second control signal, a source s of the first transistor T1 is for receiving the scan signal, and a drain d of the first transistor T1 is electrically connected to a drain d of the second transistor T2 and the scan line 11; the source s of the second transistor T2 is configured to receive the off signal.
Specifically, the first transistor T1 is turned on under the control of the first control signal or the second control signal, that is, a source-drain channel is formed between the source s and the drain d of the first transistor T1, so that the scanning signal is transmitted to the corresponding scanning line 11, and at the same time, the second transistor T2 is turned off under the control of the first control signal or the second control signal; or the first transistor T1 is turned off under the control of the first control signal or the second control signal, and at the same time, the second transistor T2 is turned on under the control of the first control signal or the second control signal, that is, a source-drain channel is formed between the source s and the drain d of the second transistor T2, so as to transmit the off signal to the corresponding scan line 11.
It will be appreciated that in other possible embodiments, the selection circuit 15 may be of other forms, as long as it does not affect the selective transmission of the scan signal and the off signal onto the scan line 11, as the application is not limited in this respect.
In one possible implementation, the first transistor T1 is a P-type metal oxide semiconductor field effect transistor (PMOS) and the second transistor T2 is a P-type metal oxide semiconductor field effect transistor (NEGATIVE CHANNEL METAL Oxide Semiconductor, NMOS); or the first transistor T1 is an NMOS, and the second transistor T2 is a PMOS.
Specifically, the first transistor T1 is a PMOS, and the second transistor T2 is an NMOS; or the first transistor T1 is an NMOS, and the second transistor T2 is a PMOS, in other words, the first transistor T1 and the second transistor T2 are transistors of complementary types. For example, the first transistor T1 is a PMOS, the second transistor T2 is an NMOS, and the first transistor T1 is turned on when the first control signal or the second control signal received by the gate g of the first transistor T1 is at a low level according to the characteristics of the PMOS and NMOS transistors; vice versa, when the first control signal or the second control signal received by the gate g of the first transistor T1 is at a high level, the first transistor T1 is turned off; when the first control signal or the second control signal received by the gate g of the second transistor T2 is at a high level, the second transistor T2 is turned on; vice versa, when the first control signal or the second control signal received by the gate g of the second transistor T2 is at a low level, the second transistor T2 is turned off.
It can be appreciated that in this embodiment, as shown in fig. 1, since the first transistor T1 and the second transistor T2 are complementary transistors, the first control signal or the second control signal may control the first transistor T1 and the second transistor T2 of a certain row to be turned on or off at the same time, thereby reducing the complexity of the circuit design of the display panel 1.
In one possible embodiment, please refer to fig. 1 and fig. 3 together, fig. 3 is a schematic diagram of signal waveforms provided in an embodiment of the present application. The display panel 1 further includes a control circuit 16, the control circuit 16 controls the voltage values of the first control signal and the second control signal according to a first display signal, so that the first transistor T1 is turned on under the control of the first control signal and the second transistor T2 is turned off under the control of the first control signal in an X frame time; the first transistor T1 is turned off under the control of the second control signal, and the second transistor T2 is turned on under the control of the second control signal.
It should be noted that, when the display panel 1 performs black display, X is a positive integer, it can be understood that the refresh frame rate does not affect the display panel 1 to display a black picture, so that, when the display panel 1 performs black display, the first transistor T1 is turned on under the control of the first control signal and the second transistor T2 is turned off under the control of the first control signal in X frame time by controlling the voltage values of the first control signal and the second control signal; the first transistor T1 is turned off under the control of the second control signal, and the second transistor T2 is turned on under the control of the second control signal, so that only the first and third sub-pixels 131 and 133 located in the odd-numbered rows are charged, and the second and third sub-pixels 132 and 133 located in the even-numbered rows are not charged. The waveforms of the first control signal, the second control signal and the Scan signal refer to the signal waveforms shown in fig. 3, where Scan1 is the waveform of the Scan signal transmitted on the Scan line of the first row, scan2 is the waveform of the Scan signal transmitted on the Scan line of the second row, and so on. For the principle that the first control signal and the second control signal control the waveforms of the scan signals, please refer to the above description, the disclosure is not repeated herein.
It can be appreciated that in the present embodiment, the control circuit 16 controls the voltage values of the first control signal and the second control signal according to the first display signal, so that only the first sub-pixel 131 and the third sub-pixel 133 located in the odd-numbered rows are charged in the X frame time, as shown in fig. 3, thereby avoiding frequent switching of the voltage values of the data signals on the data line 12, and reducing the power consumption loss of the parasitic capacitance on the data line 12.
In one possible embodiment, please refer to fig. 4, fig. 4 is a schematic diagram of signal waveforms provided in another embodiment of the present application. The control circuit 16 controls the voltage values of the first control signal and the second control signal according to a first display signal, so that the first transistor T1 is turned off under the control of the first control signal and the second transistor T2 is turned on under the control of the first control signal in a Y frame time; the first transistor T1 is turned on under the control of the second control signal, and the second transistor T2 is turned off under the control of the second control signal, wherein the value of X is equal to the value of Y, and the X frame and the Y frame are continuous frames.
The first display signal is a black display signal, and the control circuit 16 is configured to control voltage waveforms of the first control signal and the second control signal according to the first display signal, so as to control the display panel 1 to perform black display. Y is a positive integer, and the display panel 1 typically recharges the pixel unit 13 for each frame of display screen, so as to switch the display screen of the display panel 1. By X and Y frames being consecutive frames, it is meant that the display panel 1 displays a display screen of X frame time followed by a display screen of Y frame time, in other words, the display panel 1 should display a display screen of Y frame time followed by a display screen of X frame time.
Specifically, when the display panel 1 performs black display, it can be understood that the refresh frame rate does not affect the display panel 1 to display a black screen, so that the first transistor T1 is turned off under the control of the first control signal and the second transistor T2 is turned on under the control of the first control signal during the Y frame time by controlling the voltage values of the first control signal and the second control signal when the display panel 1 performs black display; the first transistor T1 is turned on under the control of the second control signal, and the second transistor T2 is turned off under the control of the second control signal, so that only the second and third sub-pixels 132 and 133 located in even rows are charged, and the first and third sub-pixels 131 and 133 located in odd rows are not charged. The waveforms of the first control signal, the second control signal, and the Scan signal refer to the signal waveforms shown in fig. 4, where Scan1 is the waveform of the Scan signal transmitted on the Scan line of the first row, scan2 is the waveform of the Scan signal transmitted on the Scan line of the second row, and so on. For the principle that the first control signal and the second control signal control the waveforms of the scan signals, please refer to the above description, the disclosure is not repeated herein.
It will be appreciated that in the present embodiment, the control circuit 16 controls the voltage values of the first control signal and the second control signal according to the first display signal, so that the first sub-pixel 131 and the third sub-pixel 133 located in the odd-numbered row are charged respectively in the X-frame time and the second sub-pixel 132 and the third sub-pixel 133 located in the even-numbered row are not charged in one continuous frame period time of the X-frame and the Y-frame; the second sub-pixel 132 and the third sub-pixel 133 located in even rows are charged during the Y frame time, and the first sub-pixel 131 and the third sub-pixel 133 located in odd rows are not charged, as shown in fig. 3 and 4, so that the voltage value of the data signal is only switched once during one continuous frame period time of the X frame and the Y frame, and the power consumption loss of the parasitic capacitance on the data line 12 is greatly reduced, so that the power consumption loss of the display panel 1 is reduced.
It will be appreciated that in other possible embodiments, the values of X and Y may be unequal, as long as it does not affect that the X and Y frames are consecutive frames, as the application is not limited in this regard.
In one possible embodiment, please refer to fig. 5, fig. 5 is a schematic diagram of signal waveforms provided in another embodiment of the present application. The control circuit 16 controls the voltage values of the first control signal and the second control signal according to a second display signal, the first transistor T1 is turned on under the control of the first control signal, and the second transistor T2 is turned off under the control of the first control signal; the first transistor T1 is turned on under the control of the second control signal, and the second transistor T2 is turned off under the control of the second control signal.
The second display signal is a non-black display signal, and the control circuit 16 is configured to control voltage waveforms of the first control signal and the second control signal according to the second display signal, so as to control the display panel 1 to display a normal display screen.
In this embodiment, the control circuit 16 controls the signal waveforms of the first control signal and the second control signal as shown in fig. 5, so that the data signal can charge the first sub-pixel 131, the second sub-pixel 132, and the third sub-pixel 133 in the same frame time, so as to realize that the display panel 1 displays a normal display screen. Wherein Scan1 is the waveform of the Scan signal transmitted on the Scan line of the first row, scan2 is the waveform of the Scan signal transmitted on the Scan line of the second row, and so on. For the principle that the first control signal and the second control signal control the waveforms of the scan signals, please refer to the above description, the disclosure is not repeated herein.
In one possible implementation, the driving circuit 14 includes a driving transistor, the off signal has a first voltage value when the driving transistor is PMOS, and the off signal has a second voltage value when the driving transistor is NMOS, wherein the first voltage value is greater than the second voltage value.
It should be noted that, referring to the above description, the transistor characteristics of NMOS and PMOS are not repeated herein. In this embodiment, since the first voltage value is greater than the second voltage value, when the driving transistor is PMOS, the turn-off signal has the first voltage value, so that when the second transistor T2 is turned on, the turn-off signal is transmitted to the corresponding scan line 11 to turn off the driving circuit 14, so as to avoid the data signal from charging the first sub-pixel 131 or the second sub-pixel 132 through the driving circuit 14; when the driving transistor is NMOS, the off signal has a second voltage value, so that when the second transistor T2 is turned on, the off signal is transmitted to the corresponding scan line 11 to turn off the driving circuit 14, so as to avoid the data signal from charging the first sub-pixel 131 or the second sub-pixel 132 through the driving circuit 14.
It can be appreciated that in the present embodiment, the driving transistor types in the different driving circuits 14 may be the same, and the voltage values of the off signals in the selection circuits 15 of each row are equal, so as to reduce the complexity of the circuit design of the display panel 1. In other possible embodiments, the driving transistor types in the driving circuit 14 may be different, and the same voltage values of the off signals may be different, which is not limited by the present application.
In one possible embodiment, referring to fig. 1 again, the display panel 1 further includes a first scan driving circuit 17 and a second scan driving circuit 18, where the first scan driving circuit 17 and the second scan driving circuit 18 are respectively electrically connected to two ends of the scan line 11 for generating the scan signal.
The ports of the first scan driving circuit 17 and the second scan driving circuit 18 for electrically connecting the same scan line 11 are the same, that is, the scan signals generated and transmitted by the first scan driving circuit 17 and the second scan driving circuit 18 on the same scan line 11 are the same. The first scan driving circuit 17 and the second scan driving circuit 18 are electrically connected to the control circuit 16, respectively, and generate the scan signals according to the control signals generated by the control circuit 16, respectively.
It can be understood that in the present embodiment, the scan signals generated and transmitted by the first scan driving circuit 17 and the second scan driving circuit 18 on the same scan line 11 are the same, so that the driving capability of the scan line 11 to drive the driving circuit 14 is stronger.
It will be appreciated that in other possible embodiments, the display panel 1 may also include only one scan driving module; the control signals generated by the control circuit 16 for the first scan driving circuit 17 and the second scan driving circuit 18 may be separate or may be a set of the same control signals, which is not limited in the present application.
The application also provides an electronic device 2, referring to fig. 6, fig. 6 is a schematic top view of the electronic device according to an embodiment of the application. The electronic device 2 comprises a housing 21 and the display panel 1 as described above, the housing 21 being adapted to carry the display panel 1. Specifically, the display panel 1 is described above, and the disclosure is not repeated here.
It should be noted that, in the embodiment of the present application, the electronic device 2 may be an electronic device 2 such as a television, a mobile phone, a smart phone, a tablet computer, an electronic reader, a portable device when worn, a notebook computer, etc., which may communicate with a data transfer server through the internet, where the data transfer server may be an instant messaging server, an SNS (Social Networking Services, social network service) server, etc., and the embodiment of the present application is not limited thereto.
It can be appreciated that in this embodiment, since the selection circuit 15 selects the scan signal or the off signal to be transmitted on the corresponding scan line 11, the driving circuit 14 of the corresponding row can be turned off, so that the data line 12 cannot charge the pixel unit 13 of the corresponding row, thereby reducing frequent changes of the voltage signal transmitted on the data line 12, reducing power consumption generated by parasitic capacitance on the data line 12, reducing power consumption loss, and enhancing endurance of the electronic device 2.
The principles and embodiments of the present application have been described herein with reference to specific examples, the description of the above embodiments being only for the purpose of aiding in the understanding of the core concept of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. The display panel comprises a plurality of scanning lines extending along a first direction, a plurality of data lines extending along a second direction, a plurality of pixel units and a plurality of driving circuits, wherein the pixel units are respectively and electrically connected with the data lines and the scanning lines through the corresponding driving circuits, the other side of each pixel unit is used for receiving a common voltage signal, each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel and the second sub-pixel are alternately arranged along the second direction at intervals and are electrically connected with the same data line, the third sub-pixel is arranged along the second direction at intervals and is electrically connected with the data line adjacent to the data line electrically connected with the first sub-pixel and the second sub-pixel, the display panel is further characterized by comprising a plurality of selection circuits which are electrically connected with the corresponding scanning lines and are used for controlling the switching of the scanning lines according to a first control signal and the switching of the scanning lines to the switching off or the scanning lines according to a first control signal and the switching of the scanning signals to the switching of the scanning lines to the first control signal and the switching of the scanning lines to the display panel to the switching off or the scanning signals to the display signals to the switching of the scanning lines according to the first signal and the switching of the scanning signals to the scanning signals or the switching of the scanning signals to the first signal and the scanning lines or the scanning signals to the display signals to the data lines to the off or the display signals to the display signals and the video signal.
2. The display panel according to claim 1, wherein the selection circuit selects the scan signal or the off signal to be transmitted on the scan line of an odd-numbered row according to the first control signal, and the selection circuit selects the scan signal or the off signal to be transmitted on the scan line of an even-numbered row according to the second control signal.
3. The display panel of claim 1, wherein the selection circuit comprises a first transistor and a second transistor, a gate of the first transistor is electrically connected to a gate of the second transistor for receiving the first control signal or the second control signal, a source of the first transistor is for receiving the scan signal, and a drain of the first transistor is electrically connected to a drain of the second transistor and the scan line; the source of the second transistor is used for receiving the closing signal.
4. The display panel of claim 3, wherein the first transistor is PMOS and the second transistor is NMOS; or the first transistor is NMOS, and the second transistor is PMOS.
5. The display panel according to claim 3, further comprising a control circuit that controls voltage values of the first control signal and the second control signal according to a first display signal such that the first transistor is turned on under control of the first control signal and the second transistor is turned off under control of the first control signal during an X frame time; the first transistor is turned off under the control of the second control signal, and the second transistor is turned on under the control of the second control signal.
6. The display panel according to claim 5, wherein the control circuit controls voltage values of the first control signal and the second control signal according to a first display signal such that the first transistor is turned off under control of the first control signal and the second transistor is turned on under control of the first control signal during a Y frame time; the first transistor is turned on under the control of the second control signal, and the second transistor is turned off under the control of the second control signal, wherein the value of X is equal to the value of Y, and the X frame and the Y frame are continuous frames.
7. The display panel according to claim 5, wherein the control circuit controls voltage values of the first control signal and the second control signal according to a second display signal, the first transistor is turned on under control of the first control signal, and the second transistor is turned off under control of the first control signal; the first transistor is turned on under the control of the second control signal, and the second transistor is turned off under the control of the second control signal.
8. The display panel of claim 1, wherein the drive circuit comprises a drive transistor, the off signal has a first voltage value when the drive transistor is PMOS, and a second voltage value when the drive transistor is NMOS, wherein the first voltage value is greater than the second voltage value.
9. The display panel of claim 1, further comprising a first scan driving circuit and a second scan driving circuit, wherein the first scan driving circuit and the second scan driving circuit are respectively electrically connected to two ends of the scan line for generating the scan signal.
10. An electronic device comprising a housing and the display panel of any one of claims 1-9, the housing being configured to carry the display panel.
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| CN202310113691.5A CN116246566B (en) | 2023-01-30 | 2023-01-30 | Display panel and electronic equipment |
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| CN202310113691.5A CN116246566B (en) | 2023-01-30 | 2023-01-30 | Display panel and electronic equipment |
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