CN110473489A - A kind of pixel arrangement structure of double grid panel - Google Patents
A kind of pixel arrangement structure of double grid panel Download PDFInfo
- Publication number
- CN110473489A CN110473489A CN201910655278.5A CN201910655278A CN110473489A CN 110473489 A CN110473489 A CN 110473489A CN 201910655278 A CN201910655278 A CN 201910655278A CN 110473489 A CN110473489 A CN 110473489A
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- Prior art keywords
- pixel
- sub
- cabling
- grid
- arrangement structure
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
Abstract
The present invention relates to field of display technology, in particular to a kind of pixel arrangement structure of double grid panel, the pixel arrangement driven by changing every data cabling, the sub-pixel of same type is connected into same data cabling by a corresponding transistor, it realizes that same data cabling drives same pixel, can be realized the purpose for reducing pure color power consumption.The pixel arrangement structure of the double grid panel of this programme design enables to existing every row switching once to become every frame switching once, greatly reduces driving IC to the frequency of the charge and discharge of data cabling, to reduce power consumption.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of pixel arrangement structure of double grid panel.
Background technique
With the continuous development of panel display technologies, display panel applications with their own characteristics are among common life, especially
It is the popularization of smart phone, panel technology has also obtained greatly applying.Smart phone of today pursue higher screen accounting and
Higher resolution, height screen accounting requires display panel to accomplish pole narrow frame, and high-res are intended to more pixels
Point and signal lead design, for driving IC, it is also desirable to design more signal output channels, will lead to IC cost in this way
Rise and volume become larger, then will affect the size of lower frame, in consideration of it, the panel of double grid (Dual Gate) framework meet the tendency of and
It is raw.For Dual Gate panel compared to general panels, Gate cabling is double, and Data cabling halves, Lai Shixian high-resolution and following
Frame narrows.But the pixel arrangement of current Dual Gate panel, in display pure color picture, such as when red, green, blue, on Data line
Voltage is not that every frame overturning is primary, but every a line will overturn and once will cause the excessive problem of display power consumption.
Summary of the invention
The technical problems to be solved by the present invention are: providing a kind of pixel arrangement structure of double grid panel.
In order to solve the above-mentioned technical problem, the scheme that the present invention uses are as follows:
A kind of pixel arrangement structure of double grid panel, including multiple main pixel regions, a plurality of data cabling and a plurality of
Grid cabling；
Each main pixel region includes three sub-pixel areas being arranged successively along the vertical direction, each sub-pixel
Area is located between two adjacent data cablings, set in each sub-pixel area there are two transistor and two different types of sons
The source electrode of pixel, the transistor in each sub-pixel area is connected respectively a data cabling, the crystalline substance in each sub-pixel area
The grid of body pipe is correspondingly connected with a grid cabling, and the drain electrode of the transistor in each sub-pixel area is correspondingly connected with a sub- picture
The sub-pixel of element, same type connects same data cabling by a corresponding transistor.
The beneficial effects of the present invention are:
The pixel arrangement that this programme is driven by changing every data cabling, passes through correspondence for the sub-pixel of same type
A transistor connect same data cabling, realize that same data cabling drives same pixel, can be realized reduction
The purpose of pure color power consumption.The pixel arrangement structure of the double grid panel of this programme design enables to existing every row switching is primary to become
It is primary for the switching of every frame, driving IC is greatly reduced to the frequency of the charge and discharge of data cabling, to reduce power consumption.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the pixel arrangement structure of double grid panel according to the present invention；
Label declaration:
1, data cabling；2, grid cabling；3, sub-pixel.
Specific embodiment
To explain the technical content, the achieved purpose and the effect of the present invention in detail, below in conjunction with embodiment and cooperate attached
Figure is explained.
The most critical design of the present invention is: the sub-pixel of same type is same by the connection of a corresponding transistor
Data cabling realizes that same data cabling drives same pixel, can be realized the purpose for reducing pure color power consumption.
Fig. 1 is please referred to, technical solution provided by the invention:
A kind of pixel arrangement structure of double grid panel, including multiple main pixel regions, a plurality of data cabling and a plurality of
Grid cabling；
Each main pixel region includes three sub-pixel areas being arranged successively along the vertical direction, each sub-pixel
Area is located between two adjacent data cablings, set in each sub-pixel area there are two transistor and two different types of sons
The source electrode of pixel, the transistor in each sub-pixel area is connected respectively a data cabling, the crystalline substance in each sub-pixel area
The grid of body pipe is correspondingly connected with a grid cabling, and the drain electrode of the transistor in each sub-pixel area is correspondingly connected with a sub- picture
The sub-pixel of element, same type connects same data cabling by a corresponding transistor.
As can be seen from the above description, the beneficial effects of the present invention are:
The pixel arrangement that this programme is driven by changing every data cabling, passes through correspondence for the sub-pixel of same type
A transistor connect same data cabling, realize that same data cabling drives same pixel, can be realized reduction
The purpose of pure color power consumption.The pixel arrangement structure of the double grid panel of this programme design enables to existing every row switching is primary to become
It is primary for the switching of every frame, driving IC is greatly reduced to the frequency of the charge and discharge of data cabling, to reduce power consumption.
Further, multiple main pixel regions is arranged in array.
Seen from the above description, multiple main pixel regions is arranged in array, can be rationally limited using panel
Display space, so that the display effect of the picture element of the sub-pixel in each main pixel region is more preferable.
Further, it is parallel to each other between adjacent two datas cabling, is parallel to each other between adjacent two grid cablings, and
The data cabling is mutually perpendicular to the grid cabling.
Further, the sub-pixel display color of the sub-pixel in each sub-pixel area is different.
Seen from the above description, can guarantee the color and brightness in each sub-pixel area, realization is displayed in red, green or
Blue.
Further, three sub-pixel areas being arranged successively along the vertical direction include first time pixel region, second of picture
Plain area and third time pixel region, the color of the sub-pixel in the first time pixel region are green and blue, second of picture
The color of sub-pixel in plain area is red and green, and the color of the sub-pixel in the third time pixel region is blue and red
Color.
Further, the grid of two transistors in the same sub-pixel area is connected respectively different grids and walks
The source electrode of line, two transistors in the same sub-pixel area is connected respectively different data cablings.
Seen from the above description, same face is connected when same root data cabling may be implemented by above-mentioned cabling design method
The sub-pixel of color, greatly reduces pure color power consumption at the problem of being able to solve the frequent charge and discharge of data cabling needs in this way.
Please refer to Fig. 1, the embodiment of the present invention one are as follows:
A kind of pixel arrangement structure of double grid panel includes multiple main pixel regions, a plurality of data cabling 1 and a plurality of
Grid cabling 2；
Each main pixel region includes three sub-pixel areas being arranged successively along the vertical direction, each sub-pixel
Area is located between two adjacent data cablings 1, set in each sub-pixel area there are two transistor and two it is different types of
For son as 3 elements, the source electrode of the transistor in each sub-pixel area is connected respectively a data cabling 1, in each sub-pixel area
The grid of transistor be correspondingly connected with a grid cabling 2, the drain electrode of the transistor in each sub-pixel area is correspondingly connected with one
The sub-pixel 3 of sub-pixel 3, same type connects same data cabling 1 by a corresponding transistor.
Multiple main pixel regions is arranged in array.
It is parallel to each other, is parallel to each other between adjacent two grid cablings 2, and the number between adjacent two datas cabling 1
It is mutually perpendicular to according to cabling 1 and the grid cabling 2.
The grid of two transistors in the same sub-pixel area is connected respectively different grid cablings 2, same
The source electrode of two transistors in sub-pixel area is connected respectively different data cablings 1.
The sub-pixel display color of sub-pixel 3 in each sub-pixel area is different.
Three sub-pixel areas being arranged successively along the vertical direction include first time pixel region, second of pixel region and third
Sub-pixel area, the color of the sub-pixel 3 in the first time pixel region are green and blue, the son in second of pixel region
The color of pixel 3 is red and green, and the color of the sub-pixel 3 in the third time pixel region is blue and red.
The pixel arrangement structure of traditional double grid panel when pixel charges can only the switching of every row it is primary, such as element charged
Cheng Zhong, if show green picture, the voltage of the second data cabling (being indicated in Fig. 1 with D2) write-in be with -5V → 0 → -5V →
0.High-frequency switching, next frame are+5V → 0 →+5V → 0.Frequency switch over, in this way, driving IC just need frequency
Numerous is that D2 carries out charge and discharge, consumes more power consumptions.
It is primary that the pixel arrangement structure of the double grid panel of this programme design can be realized every frame switching, such as charges in pixel
In the process, if show green picture, the voltage of the second data cabling (being indicated in Fig. 1 with D2) write-in -5V always, only under
When one frame, it is just switched to+5V, the i.e. voltage of the N frame of D2 are as follows: -5V, -5V, -5V.- 5V, then the voltage switching of the N+1 frame of D2
Are as follows:+5V ,+5V ,+5V.+ 5V, so as to improve the excessive problem of existing double grid panel power consumption.
In conclusion a kind of pixel arrangement structure of double grid panel provided by the invention, this programme is by changing every number
The sub-pixel of same type is connected same data by a corresponding transistor and walked by the pixel arrangement driven according to cabling
Line realizes that same data cabling drives same pixel, can be realized the purpose for reducing pure color power consumption.Pair of this programme design
The pixel arrangement structure of Grid screen enables to existing every row switching once to become every frame switching once, greatly reduces driving
IC is to the frequencies of the charge and discharge of data cabling, to reduce power consumption.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalents made by bright specification and accompanying drawing content are applied directly or indirectly in relevant technical field, similarly include
In scope of patent protection of the invention.
Claims (6)
1. a kind of pixel arrangement structure of double grid panel, which is characterized in that including multiple main pixel regions, a plurality of data cabling
With a plurality of grid cabling；
Each main pixel region includes three sub-pixel areas being arranged successively along the vertical direction, each sub-pixel position
Between two adjacent data cablings, set in each sub-pixel area there are two transistor and two different types of sub- pictures
The source electrode of element, the transistor in each sub-pixel area is connected respectively a data cabling, the crystal in each sub-pixel area
The grid of pipe is correspondingly connected with a grid cabling, and the drain electrode of the transistor in each sub-pixel area is correspondingly connected with a sub-pixel,
The sub-pixel of same type connects same data cabling by a corresponding transistor.
2. the pixel arrangement structure of double grid panel according to claim 1, which is characterized in that multiple main pixel regions
It arranges in array.
3. the pixel arrangement structure of double grid panel according to claim 1, which is characterized in that adjacent two datas cabling it
Between be parallel to each other, be parallel to each other between adjacent two grid cablings, and the data cabling is mutually perpendicular to the grid cabling.
4. the pixel arrangement structure of double grid panel according to claim 1, which is characterized in that the son in each sub-pixel area
The sub-pixel display color of pixel is different.
5. the pixel arrangement structure of double grid panel according to claim 4, which is characterized in that three along the vertical direction according to
The sub-pixel area of secondary arrangement includes first time pixel region, second of pixel region and third time pixel region, the first time pixel region
In the color of sub-pixel be green and blue, the color of the sub-pixel in second of pixel region is red and green, institute
The color of the sub-pixel in third time pixel region is stated as blue and red.
6. the pixel arrangement structure of double grid panel according to claim 1, which is characterized in that in the same sub-pixel area
The grid of two transistors is connected respectively different grid cablings, the source electrode of two transistors in the same sub-pixel area
It is connected respectively different data cablings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910655278.5A CN110473489B (en) | 2019-07-19 | 2019-07-19 | Pixel arrangement structure of double-gate panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910655278.5A CN110473489B (en) | 2019-07-19 | 2019-07-19 | Pixel arrangement structure of double-gate panel |
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| CN110473489A true CN110473489A (en) | 2019-11-19 |
| CN110473489B CN110473489B (en) | 2023-06-27 |
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| CN201910655278.5A Active CN110473489B (en) | 2019-07-19 | 2019-07-19 | Pixel arrangement structure of double-gate panel |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111028802A (en) * | 2019-12-12 | 2020-04-17 | 福建华佳彩有限公司 | Driving method of double-gate panel |
| CN113777839A (en) * | 2021-08-19 | 2021-12-10 | 深圳市华星光电半导体显示技术有限公司 | Display panel and mobile terminal |
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| EP2629281A1 (en) * | 2011-08-12 | 2013-08-21 | Shanghai Avic Optoelectronics Co. Ltd | Dual-gate driving transversely-arranged pixel structure and display panel |
| US20140071033A1 (en) * | 2012-09-07 | 2014-03-13 | Beijing Boe Optoelectronics Technology Co., Ltd. | Liquid Crystal Display And Driving Method Thereof |
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| US20180053478A1 (en) * | 2016-01-13 | 2018-02-22 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel and driving method thereof |
| US20180190216A1 (en) * | 2015-08-28 | 2018-07-05 | Boe Technology Group Co., Ltd. | Array substrate, display device and driving method |
| CN108628049A (en) * | 2018-05-31 | 2018-10-09 | 京东方科技集团股份有限公司 | array substrate, display panel and display device |
| CN109830203A (en) * | 2019-03-05 | 2019-05-31 | 武汉天马微电子有限公司 | Display panel and its driving method, display device |
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2019
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Patent Citations (7)
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|---|---|---|---|---|
| EP2629281A1 (en) * | 2011-08-12 | 2013-08-21 | Shanghai Avic Optoelectronics Co. Ltd | Dual-gate driving transversely-arranged pixel structure and display panel |
| US20140071033A1 (en) * | 2012-09-07 | 2014-03-13 | Beijing Boe Optoelectronics Technology Co., Ltd. | Liquid Crystal Display And Driving Method Thereof |
| CN104090440A (en) * | 2014-06-30 | 2014-10-08 | 上海天马微电子有限公司 | Pixel structure, liquid crystal display array substrate and liquid crystal display panel |
| US20180190216A1 (en) * | 2015-08-28 | 2018-07-05 | Boe Technology Group Co., Ltd. | Array substrate, display device and driving method |
| US20180053478A1 (en) * | 2016-01-13 | 2018-02-22 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel and driving method thereof |
| CN108628049A (en) * | 2018-05-31 | 2018-10-09 | 京东方科技集团股份有限公司 | array substrate, display panel and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111028802A (en) * | 2019-12-12 | 2020-04-17 | 福建华佳彩有限公司 | Driving method of double-gate panel |
| CN113777839A (en) * | 2021-08-19 | 2021-12-10 | 深圳市华星光电半导体显示技术有限公司 | Display panel and mobile terminal |
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| Publication number | Publication date |
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| CN110473489B (en) | 2023-06-27 |
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