CN116234322B - Memory, manufacturing method thereof and read-write control method - Google Patents

Abstract

The embodiment of the application provides a memory, a manufacturing method thereof and a read-write control method. In the memory provided by the embodiment of the application, the transistors in the two memory cells which are arbitrarily adjacent along the row direction are electrically connected through the source line, so that two rows of memory cells can be controlled simultaneously through the source line, the number of the source lines in the memory can be reduced, the wiring difficulty in the memory can be reduced, and the design cost and the manufacturing cost of the memory can be reduced.

Description

Memory, manufacturing method thereof and read-write control method

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a memory, a method for manufacturing the same, and a method for controlling read/write.

Background

With the development of semiconductor device integration technology, the variety of memories is increasing, and MRAM (Magnetoresistive Random Access Memory, magnetic random access memory) is one of the important research directions in the industry as a nonvolatile memory.

Currently, each memory cell in MRAM needs to be provided with a bit line, a word line, and a source line, which results in more wiring in MRAM, and increases the design cost and manufacturing cost of MRAM.

Disclosure of Invention

The application provides a memory, a manufacturing method thereof and a read-write control method thereof, which are at least used for overcoming the defects in the background technology.

Some embodiments of the present application provide a memory comprising: a plurality of rows and columns of memory cells, a plurality of rows of word lines, a plurality of columns of bit lines, and a plurality of columns of source lines;

the memory cell includes: a transistor and a magnetic tunnel junction; the transistor includes a first channel and a second channel;

one end of the magnetic tunnel junction is electrically connected with the drain electrode of the transistor, and the other end of the magnetic tunnel junction is electrically connected with the bit line; the grid electrode of the transistor in each memory cell of the same row is electrically connected with the word line; the source electrode of each transistor in a column of memory cells is electrically connected with two source lines at the same time, and the two source lines are electrically connected with a first channel and a second channel respectively; in any two adjacent columns of memory cells, one end of a source line is electrically connected with the source electrode of each transistor in one column of memory cells, and the other end of the source line is electrically connected with the source electrode of each transistor in the other column of memory cells.

Some embodiments of the present application provide a method for controlling reading and writing of a memory, including:

in the reading stage, controlling a transistor in a memory cell to be read to be in a conducting state through a word line, and transmitting a reading signal to a magnetic tunnel junction of the memory cell to be read through one of a bit line or one source line so that the other one of the bit line or the one source line senses stored data of the magnetic tunnel junction;

In the writing stage, the transistor in the memory cell to be written is controlled to be in a conducting state through the word line, and the direction of the magnetic tunnel junction in the memory cell to be written is controlled through the bit line and the two source lines, so that the storage signal transmitted by the bit line or the source line is written into the magnetic tunnel junction.

Some embodiments of the present application provide a method for manufacturing a memory, including:

forming a stacked structure of a plurality of source lines and a plurality of array arrangements on one side of a substrate based on a patterning process; the stacked structure comprises a source electrode, a sacrificial semiconductor structure and a drain electrode which are arranged in a stacked manner, wherein a first semiconductor layer and a second semiconductor layer are respectively arranged on two outer side walls of the sacrificial semiconductor structure, and the source electrodes of any two adjacent stacked structures along the row direction are connected with the same source line;

removing the sacrificial semiconductor structure;

forming word lines and grid electrodes at least partially positioned between the first semiconductor layer and the second semiconductor layer to obtain transistors arranged in an array; the grid electrodes of the transistors positioned in the same row are connected with the same word line;

sequentially forming a connection structure and a magnetic tunnel junction on one side of a source electrode of the transistor far away from the substrate;

a bit line is formed on a side of the magnetic tunnel junction remote from the substrate.

The beneficial technical effects that technical scheme that this application embodiment provided brought include:

in the memory provided by the embodiment of the application, one end of the source line is electrically connected with the source electrode of each transistor in one column of memory cells, and the other end of the source line is electrically connected with the source electrode of each transistor in the other column of memory cells, so that two columns of memory cells can be controlled simultaneously through one source line, the number of source lines in the memory can be reduced, the wiring difficulty in the memory can be reduced, and the design cost and the manufacturing cost of the memory can be reduced.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic circuit diagram of a memory according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a memory according to an embodiment of the present disclosure;

FIG. 3 is a schematic view of an AA cross-sectional configuration of the memory shown in FIG. 2 according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another memory according to an embodiment of the present disclosure;

FIG. 5 is a schematic flow chart of a method for manufacturing a memory according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a structure of a memory after a first photoresist structure and a first mask structure are obtained in a method for manufacturing a memory according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a memory manufacturing method according to an embodiment of the present disclosure after an initial stacked structure row is obtained;

FIG. 8 is a schematic diagram of a structure of a memory after a first arc-shaped groove is obtained in a method for manufacturing the memory according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a structure of a metal layer obtained in a method for manufacturing a memory according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a memory manufacturing method according to an embodiment of the present disclosure after obtaining bit lines;

FIG. 11 is a schematic diagram of a structure of a memory after a first planarization layer is obtained in the method for manufacturing a memory according to the embodiment of the present application;

FIG. 12 is a schematic diagram of a first flat structure obtained in the method for manufacturing a memory according to the embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a memory manufacturing method according to an embodiment of the present disclosure after obtaining stacked rows of structures;

fig. 14 is a schematic structural diagram of a semiconductor line obtained in the method for manufacturing a memory according to the embodiment of the present application;

Fig. 15 is a schematic structural diagram of a memory after obtaining a second flat layer in the method for manufacturing a memory according to the embodiment of the present application;

FIG. 16 is a schematic view of BB cross-sectional structure of the memory after the mask structure is formed in the structure shown in FIG. 14 in the method for manufacturing a memory according to the embodiment of the present application;

fig. 17 is a schematic structural diagram of a semiconductor layer manufactured based on the structure shown in fig. 15 in the manufacturing method of the memory according to the embodiment of the present application;

FIG. 18 is a schematic diagram of a structure of a memory after forming word lines in a method of fabricating the memory according to an embodiment of the present disclosure;

FIG. 19 is a schematic diagram of a structure of a memory after forming a connection structure in a method for manufacturing the memory according to an embodiment of the present disclosure;

fig. 20 is a schematic structural diagram of a memory after forming a package layer in the method for manufacturing a memory according to an embodiment of the present application.

Reference numerals illustrate:

100-a substrate;

200-a memory cell; 201-word lines; 2011-first subsection; 2012-a second subsection; 202-bit lines; 203-source line; 2031-a first portion of source line 203; 2032 a second portion of source line 203;

a 10-transistor;

11-source; a 12-semiconductor layer; 121-a first semiconductor layer; 122-a second semiconductor layer; 13-gate; 131-a first gate; 132-a second gate; 14-drain electrode; 15-a gate insulating layer; 151-a first gate insulating layer; 152-a second gate insulation layer;

A 20-magnetic tunnel junction; 30-a hard mask structure; 40-connecting structure; a 41-silicide structure; 42-a metal structure; 50-dielectric structure; 60-packaging layers; 70-isolating layer;

101-a first conductor layer; 102-a sacrificial semiconductor layer; 103-a second conductor layer; 104-a first photoresist structure; 105-a first mask structure;

106-an initial stacking structure row; 1011-source rows; 1021-initially sacrificial semiconductor rows; 1031-drain rows; 1071-protective structure;

108-a first arc-shaped groove; 109-a metal layer; 111-a first planar layer; 1111-a first planar structure;

112-stacking structural rows; 1121-sacrificial semiconductor rows; 113-semiconductor rows; 114-a second planar layer; 1151-a first sub-mask structure; 116-stacked configuration.

Detailed Description

Embodiments of the present application are described below with reference to the drawings in the present application. It should be understood that the embodiments described below with reference to the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and the technical solutions of the embodiments of the present application are not limited.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, information, data, steps, operations, elements, components, and/or groups thereof, etc. that may be implemented as desired in the art.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The memory according to the embodiments of the present application may be an MRAM, which is a nonvolatile magnetic random access memory, and data stored in the MRAM is stored in a magnetic state, not electric charges, and magnetic field polarities are not leaked over time like electric charges, so that information can be maintained even in the case of power failure.

Currently, MRAM often includes a plurality of memory cells arranged in an array, where each memory cell needs to be provided with a bit line, a word line, and a bit line, and the memory cells are often arranged in an array, which results in more wiring in the MRAM, which leads to an increase in design cost and manufacturing cost of the MRAM.

Moreover, the manufacturing precision of the semiconductor structure and the grid electrode of the vertical transistor in the MRAM memory cell is low, so that the performance of the VGAA transistor in the memory is different, and the performance of the memory is affected.

Moreover, the vertical transistor faces a bottleneck that the driving current is further increased. For example, as the size of the vertical transistor decreases, the on-state current of the vertical transistor decreases, and thus the driving performance of the transistor decreases, the turn-on speed is slower, and thus the performance of the memory is affected.

The memory, the manufacturing method thereof and the read-write control method aim to solve the technical problems in the prior art.

The technical scheme of the present application is described in detail below with specific examples.

An embodiment of the present application provides a memory, a schematic circuit diagram of which is shown in fig. 1, where the memory includes: a multi-row multi-column memory cell 200, a multi-row word line 201, a multi-column bit line 202, and a multi-column source line 203; the memory unit 200 includes: a transistor 10 and a magnetic tunnel junction 20; the transistor 10 includes a first channel and a second channel.

One end of the magnetic tunnel junction 20 is electrically connected to the drain 14 of the transistor 10, and the other end is electrically connected to the bit line 202; the source 11 of the transistor 10 in any two adjacent memory cells 200 in the row direction is electrically connected to the same source line 203, and the gate 13 of the transistor 10 in each memory cell 200 in the same row is electrically connected to the word line 201.

One end of the magnetic tunnel junction 20 is electrically connected to the drain 11 of the transistor 10, and the other end is electrically connected to the bit line 202; the gate 13 of the transistor 10 in each memory cell 200 of the same row is electrically connected to the word line 201; the source 11 of each transistor 10 in a column of memory cells 200 is electrically connected to two source lines 203 simultaneously, the two source lines 203 being electrically connected to a first channel and a second channel respectively; in any two adjacent columns of memory cells 200, one end of one source line 203 is electrically connected to the source 11 of each transistor 10 in one column of memory cells 200, and the other end of the source line 203 is electrically connected to the source 11 of each transistor 10 in the other column of memory cells 200.

In the memory provided in this embodiment of the present application, one end of one source line 203 is electrically connected to the source 11 of each transistor 10 in one column of memory cells 200, and the other end of the source line 203 is electrically connected to the source 11 of each transistor 10 in another column of memory cells 200, so that two columns of memory cells 200 can be controlled simultaneously by one source line 203, thereby reducing the number of source lines 203 in the memory, reducing the difficulty in routing the memory, and reducing the design cost and manufacturing cost of the memory.

In this embodiment, the plurality of memory cells 200 are arranged in an array, that is, the transistors 10 of each memory cell 200 are arranged in an array. As defined herein, the direction parallel to the extension of the word line 201 is a row, and the direction parallel to the extension of the source line 203 is a column. As shown in fig. 1, the transistors 10 of two memory cells in the same row are exemplarily shown in fig. 1, i.e. one memory cell 200 of each of two columns of memory cells 200 is shown.

In this embodiment, as shown in fig. 1, each memory cell 200 includes a transistor 10 and a magnetic tunnel junction 20, and the transistor 10 and the magnetic tunnel junction 20 are electrically connected. Optionally, one end of the magnetic tunnel junction 20 is electrically connected to the drain 14 of the transistor 10.

As shown in fig. 1, the sources 11 of the transistors 10 in any two adjacent memory cells 200 along the row direction are electrically connected with the same source line 203, so that three source lines 203 may be configured for any two adjacent memory cells 200, and compared with the memory of the related art, the number of the source lines 203 in the memory can be greatly reduced, so that the difficulty in arrangement of wires in the memory can be reduced, and the design cost and the manufacturing cost of the memory can be reduced.

In this embodiment, as shown in fig. 1, the other end of the magnetic tunnel junction 20 is electrically connected to the bit line 202, and the gate 13 of the transistor 10 in each memory cell 200 in the same row is electrically connected to the word line 201. When the transistor 10 is turned on by the word line 201, the data reading of the two columns of memory cells 200 can be controlled by the same source line 203 electrically connected to the two columns of memory cells 200, so that the data reading speed of the memory can be improved. The writing of data to the two columns of memory cells 200 can be controlled by three source lines 203.

Alternatively, in the embodiment of the present application, the magnetic tunnel junction 20 includes an MTJ (Magnetic Tunnel Junctions, magnetic tunnel junction), and the MRAM determines whether the stored data is "0" or "1" by detecting the MTJ resistance level "

Specifically, the MTJ includes a free layer, a tunneling layer, and a fixed layer, which are stacked in order. The magnetic field direction of the free layer can be changed, the magnetic field direction of the fixed layer is fixed, electrons can vertically pass through the device through the barrier of the tunneling layer under the action of an electric field, when the magnetic field direction of the free layer is the same as the magnetic field direction of the fixed layer, the MTJ presents a low resistance state of 0, and when the magnetic field direction of the free layer is opposite to the magnetic field direction of the fixed layer, the MTJ presents a high resistance state of 1.

In this embodiment, by setting the transistor 10 to include the first channel and the second channel, compared with the Shan Goudao transistor, the on-state current of the transistor 10 can be significantly improved, the driving capability and the opening speed of the transistor 10 can be improved, and then the performance of the memory can be improved.

In one embodiment of the present application, transistor 10 is a vertical transistor 10, with transistor 10 and magnetic tunnel junction 20 being stacked in a direction perpendicular to substrate 100.

In this embodiment, as shown in fig. 2, a schematic structure of a memory provided in this embodiment of the present application is shown in fig. 2, where the memory cells 200 are disposed on a side of the source line 203 away from the substrate 100, and the transistor 10 and the magnetic tunnel junction 20 of each memory cell 200 are stacked along a direction perpendicular to the substrate 100, and the source 11 of the transistor 10 in any two adjacent memory cells 200 along a row direction (i.e., the first direction in fig. 2) is electrically connected to the same source line 203.

It should be noted that fig. 2 is a schematic view of a partial cross-section of the reservoir, and thus, the source lines 203 on both sides in the first direction are only partially shown, and the non-illustrated portions of the two source lines 203 may be referred to as the source lines 203 located in the middle.

In one embodiment of the present application, the transistor 10 includes a source electrode 11, a semiconductor layer 12, and a drain electrode 14 sequentially stacked over a substrate 100; the semiconductor layer 12 includes a first semiconductor layer 121 and a second semiconductor layer 122, and the first semiconductor layer 121 and the second semiconductor layer 122 are disposed at an interval on the same side of the source electrode 11 to be in contact with the source electrode 11, respectively; the first semiconductor layer 121 includes a first channel in case of conduction, and the second semiconductor layer 122 includes a second channel in case of conduction; at least a portion of the gate electrode 13 is located at a spaced-apart region of the first semiconductor layer 121 and the second semiconductor layer 122.

In the embodiment of the present application, as shown in fig. 2, the source electrode 11, the semiconductor layer 12, and the drain electrode 14 are sequentially stacked in a direction perpendicular to the substrate 100. The gate 13 is also located between the source 11 and the drain 14, i.e. the gate 13 is arranged in the same layer as the semiconductor layer 12.

As shown in fig. 2, the first semiconductor layer 121 and the second semiconductor layer 122 are disposed at the same side of the source electrode 11 with a gap therebetween, and are in contact with the source electrode 11. The first semiconductor layer 121 includes a first channel in case of conduction, and the second semiconductor layer 122 includes a second channel in case of conduction.

In one embodiment of the present application, the first semiconductor layer 121 and the second semiconductor layer 122 are disposed at intervals in the row direction; the cross section of the source line 203 is in an arc shape with a notch at the top, one end of the same source line 203 close to the notch is a first part 2031, and the other end is a second part 2032; the first portion 2031 is connected to the first semiconductor layer 121 in at least some of the memory cells 200 in one column of memory cells 200, and the second portion 2032 is connected to the second semiconductor layer 122 in at least some of the memory cells 200 in another column of memory cells 200.

In this embodiment, as shown in fig. 2, the first semiconductor layer 121 and the second semiconductor layer 122 in the transistor 10 are disposed at intervals along the row direction, that is, along the first direction parallel to the substrate 100.

In this embodiment, as shown in fig. 4, the cross section of the source line 203 is in an arc shape with a notch at the top, and in the same source line 203, one end close to the notch is a first portion 2031, and the other end is a second portion 2032; the first portion 2031 is connected to the first semiconductor layer 121 in at least some of the memory cells 200 in one column of memory cells 200, and the second portion 2032 is connected to the second semiconductor layer 122 in at least some of the memory cells 200 in another column of memory cells 200.

Alternatively, in the embodiment of the present application, the source electrode 11 is made of a lightly doped semiconductor material, so that the conductivity of the source electrode 11 is smaller than that of the source line 203. As shown in fig. 1 and 2, in the transistor 10, the semiconductor layer 12 includes the first semiconductor layer 121 and the second semiconductor layer 122 that are disposed at intervals, in the on state, the first semiconductor layer 121 includes the first channel, and the second semiconductor layer 122 includes the second channel, which is equivalent to that each transistor 10 includes two sub-transistors connected in parallel, so that the on-state current of the transistor 10 is increased, and at the same time, the current passing through each sub-transistor can be reduced, thereby reducing the loss speed of the transistor 10 and prolonging the service life of the transistor 10.

Meanwhile, the source electrode 11 of the sub-transistor can be prevented from being physically isolated, the preparation process of the transistor can be simplified, and the manufacturing cost of the transistor can be reduced.

In one embodiment of the present application, the projection of source 11 onto substrate 100 covers the projection of part of source line 203 onto the substrate; in a radial plane of the source line 203, the cross-sectional shape of the source line 203 is an arc shape, and one side of the arc source line 203 is connected to the source 11 of each transistor 10 of one column of memory cells 200, and the other side is connected to the source 11 of each transistor 10 of another column of memory cells.

In this embodiment, as shown in fig. 2, the source line 203 is located between the substrate 100 and the transistor 10, and the projection of the source 11 of the transistor 10 on the substrate 100 covers the projection of a part of the source line 203 on the substrate 100, that is, the source 11 covers a part of the source line 203.

In this embodiment, as shown in fig. 2, in a radial plane of the source line 203, the cross-sectional shape of the source line 203 is arc, one side of the arc source line 203 is connected to the source 11 of each transistor 10 of one column of memory cells 200, and the other side is connected to the source 11 of each transistor 10 of another column of memory cells 200, so that two columns of memory cells 200 can be connected through one source line 203.

Those skilled in the art will appreciate that, compared to a source line having a straight line segment in cross-sectional shape, the source line 203 having an arc-shaped cross-sectional shape is adopted, so that a right-angled portion of the source line 203 can be avoided, and thus, a tip effect can be avoided, and the performance of the memory can be ensured.

In one embodiment of the present application, the gate 13 includes a first gate 13 and a second gate 13 connected to each other; the first gate electrode 131 is a gate electrode located between the spaced apart regions of the first and second semiconductor layers 121 and 122; the second gate electrode 132 is disposed on the outer sidewalls of the first semiconductor layer 121 and the second semiconductor layer 122, and is insulated from the first semiconductor layer 121, the second semiconductor layer 122, the source electrode 11, and the drain electrode 14.

In one embodiment of the present application, the gate 13 includes a first gate 13 and a second gate 13; the first gate electrode 13 is disposed between the two first semiconductor layers 121 and the second semiconductor layer 122, and is insulated from the first semiconductor layer 121, the second semiconductor layer 122, the source electrode 11, and the drain electrode 14; the second gate electrode 13 is disposed on an outer sidewall of the semiconductor layer 12 and is insulated from the semiconductor layer 12, the source electrode 11, and the drain electrode 14.

In this embodiment, as shown in fig. 2, the transistor 11 further includes a gate insulating layer 15, and optionally, in this embodiment, the gate insulating layer 15 is made of a high-k dielectric material.

Alternatively, as shown in fig. 2, the gate insulating layer 15 includes one first gate insulating layer 151 and two second gate insulating layers 152. The first gate insulating layer 151 conforms to the peripheral wall of the cavity formed by surrounding the source electrode 11, the inner sidewalls of the first semiconductor layer 121 and the second semiconductor layer 122, and the drain electrode 14; the second gate insulating layer 152 is conformal with the outer sidewalls of the source electrode 11, the first semiconductor layer 121, and the second semiconductor layer 122, and the peripheral wall of the recess formed around the drain electrode 14.

In this embodiment, as shown in fig. 2, the first gate 131 of the gate 13 is located between two semiconductor layers 12 disposed at intervals, and optionally, the first gate 131 is disposed in a cavity formed by enclosing the first gate insulating layer 151, so that the first gate 131 is insulated from the semiconductor layers 12, the source 11 and the drain 14.

As shown in fig. 2, the second gate 132 of the gate 13 is located on an outer sidewall of the semiconductor layer 12, and optionally, the second gate 132 is disposed in a groove formed by enclosing the second gate insulating layer 152, so that the second gate 132 is insulated from the semiconductor layer 12, the source 11 and the drain 14.

In one embodiment of the present application, both the first gate 13 and the second gate 13 are connected to the word line 201.

In this embodiment, as shown in fig. 2, the word line 201 extends in a first direction parallel to the substrate 100, and as shown in fig. 3, the source line 203 extends in a second direction parallel to the substrate 100, and the first direction is perpendicular to the second direction. Alternatively, the extension direction of the bit line 202 is parallel to the extension direction of the source line 203.

In this embodiment, as can be seen from fig. 3 and 4, the first gate 131 and the second gate 132 of the gate 13 are connected to the word line 201, so that the level can be applied to the first gate 131 and the second gate 132 simultaneously through the word line 201, the electric field strength of the gate 13 can be further enhanced, thereby being capable of helping to improve the on-state current of the transistor 10, further helping to improve the driving capability and the on-state speed of the transistor 10, helping to improve the read-write speed of the memory cell 200, and helping to improve the performance of the memory.

In one embodiment of the present application, the word line 201 includes a plurality of first subsections 2011 and second subsections 2012 that are alternately connected in sequence; the first subsection 2011 surrounds the first grid 13 and the second grid 13 and is connected with the first grid 13 and the second grid 13; one end of the second sub-section 2012 is connected to one first sub-section 2011, and the other end is connected to the other first sub-section 2011.

In this embodiment, as shown in fig. 2 and 3, the first subsections 2011 and the second subsections 2012 are alternately connected in sequence along the first direction, that is, the extending direction of the word line 201.

In this embodiment, as can be seen in fig. 2 and 3, the first subsection 2011 is disposed around the first gate 131 and the second gate 132, i.e. the first subsection 2011 wraps both end surfaces of the first gate 131 and both end surfaces of the second gate 132, so as to be connected to both the first gate 131 and the second gate 132.

Optionally, as shown in fig. 3, the upper surface of the first sub-segment 2011 is flush with the upper surface of the first gate 131, so that the first sub-segment 2011 can be prevented from contacting the drain 14 of the transistor 10.

In this embodiment, as shown in fig. 2, the second sub-segment 2012 is located between two adjacent transistors 10 and is used for connecting the first sub-segment 2011 surrounding the first gate 131 and the second gate 132. The upper surface of the second sub-segment 2012 is flush with the upper surface of the first sub-segment 2011, so that the contact probability of the second sub-segment 2012 and the drain 14 of the transistor 10 can be reduced, the parasitic capacitance probability between the second sub-segment 2012 and the drain 14 can be reduced, and further the performance of the memory can be guaranteed.

It should be noted that, for the sake of clarity, the structures of the first sub-segment 2011 and the second sub-segment 2012 in the word line 201 are illustrated, and the boundary between the first sub-segment 2011 and the second sub-segment 2012 and the boundary between the first sub-segment 2011 and the first gate 131 are illustrated by dashed lines in fig. 2, 3 and 4, and in the actual product, the first sub-segment 2011, the second sub-segment 2012 and the gate 13 are formed by using the same material, and the dashed lines as illustrated in fig. 2, 3 and 4 are not present.

In one embodiment of the present application, the projection of the outer contours of the source electrode 11 and the drain electrode 14 on the substrate encloses the projection of the outer contours of the first semiconductor layer 121, the second semiconductor layer 122 and the first gate electrode 131 on the substrate, so that the source electrode 11, the drain electrode 14 protrude outwards with respect to the first semiconductor layer 121, the second semiconductor layer 122 and the first gate electrode 131.

Optionally, as shown in fig. 2, in the transistor 10, an orthographic projection of an outer contour of the drain electrode 14 of the source electrode 11 on the substrate 100 encloses an orthographic projection of outer contours of the first semiconductor layer 121, the second semiconductor layer 122, and the first gate electrode 131 on the substrate 100. As shown in fig. 1, a cross-sectional pattern formed by combining the source electrode 11, the semiconductor layer 12, the first gate electrode 131, and the drain electrode 14 is i-shaped.

In one embodiment of the present application, the projection of the outer contours of the source electrode 11 and the drain electrode 14 onto the substrate overlaps with the projection of the outer contour of the second gate electrode 13 onto the substrate.

Alternatively, as shown in fig. 2, the front projection of the outer contours of the electrode 11 and the drain electrode 14 on the substrate 100 overlaps with the front projection of the outer contour of the second gate 132 on the substrate 100, so that the outer sidewalls of the source electrode 11 and the drain electrode 14 are flush with the outer sidewalls of the second gate 132.

It should be noted that, in the embodiment of the present application, both the reference to the outer and inner are with respect to the center of the memory, the reference to the center relatively close to the memory is the inner, and the reference to the center relatively far from the memory is the outer.

In one embodiment of the present application, the memory cell 200 further includes: a connection structure 40 disposed on a side of the drain 14 away from the source 11; the magnetic tunnel junction 20 is disposed on a side of the connection structure remote from the drain 14.

Alternatively, as shown in fig. 2, the transistor 10 and the connection structure 40 are stacked in a direction perpendicular to the substrate 100, and the connection structure 40 is disposed on a side of the drain 14 of the transistor 10 away from the source 11.

In the embodiment of the present application, the connection structure 40 is used to electrically connect the transistor 10 and the magnetic tunnel junction 20. Thus, the transistor 10 and the magnetic tunnel junction 20 are conveniently manufactured respectively, for example, after the source line 203, the transistor 10, the word line 201 and the connection structure 40 are sequentially formed on one side of the substrate 100 by adopting one production line, the magnetic tunnel junction 20 is formed by adopting the other production line, so that the production efficiency of the memory can be improved.

Alternatively, as shown in fig. 3, the connection structure 40 includes a silicide structure 41 and a metal structure 42. Since the drain 14 is made of a doped semiconductor material, the conductivity of the drain is significantly different from that of the metal structure 42, and by providing the silicide structure 41, the interface resistance between the metal structure 42 and the drain 14 can be reduced, so that the performance of the memory cell 200 can be ensured.

In this embodiment, as shown in fig. 2-3, the memory further includes a dielectric structure 50, and the dielectric structure 50 may be made of the same dielectric material as the gate insulating layer 15. Alternatively, as shown in FIG. 2, the connection structure 40 is disposed within an opening of the media structure 50.

Alternatively, as shown in fig. 2, a hard mask structure 30 is provided on a side of the magnetic tunnel junction 20 remote from the substrate 100, and the hard mask structure 30 may function to protect the magnetic tunnel junction 20 during formation of the magnetic tunnel junction 20. Optionally, the hard mask structure 30 comprises a metal and a dielectric material, so that the hard mask structure 30 has a certain conductivity, and the hard mask structure 30 is connected to the bit line 202, thereby electrically connecting the bit line 202 to the magnetic tunnel junction 20.

It should be noted that the hardness of the hard mask structure 30 is relative to the hardness of the photoresist, and the material of the hard mask structure 30 includes silicon oxide, silicon nitride, and the like.

In this embodiment, as shown in fig. 2, an encapsulation layer 60 is disposed on a side of the hard mask structure 30 away from the substrate 100, and the encapsulation layer 60 covers the side wall of the magnetic tunnel junction 20 to avoid the magnetic tunnel junction 20 from being corroded by external water, oxygen, and the like.

Optionally, the material of the encapsulation layer 60 includes dense materials such as silicon nitride, aluminum oxide, magnesium oxide, and the like.

Based on the same inventive concept, an embodiment of the present application provides an electronic device, including: any of the memories provided in the various embodiments above.

In this embodiment of the present application, since the electronic device adopts any of the memories provided in the foregoing embodiments, the principles and technical effects of the electronic device refer to the foregoing embodiments, and are not repeated herein.

Optionally, the electronic device comprises a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

It should be noted that the electronic device is not limited to the above-mentioned several types, and those skilled in the art may set any of the memories provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in the embodiments of the present application.

Based on the same inventive concept, the embodiment of the application provides a read-write control method of a memory, which comprises the following steps:

In the read phase, transistor 10 in the memory cell 200 to be read is controlled to be in an on state by word line 201, and a read signal is transmitted to magnetic tunnel junction 20 of memory cell 200 to be read by one of bit line 202 or one of source lines 203, such that the other of bit line 202 or one of source lines 203 senses the stored data of magnetic tunnel junction 20.

In the writing phase, the transistor 10 in the memory cell 200 to be written is controlled to be in an on state by the word line 201, and the direction of flowing through the magnetic tunnel junction 20 in the memory cell 200 to be written is controlled by the bit line 202 and the two source lines 203, so that the storage signal transmitted by the bit line 202 or the source line 203 is written into the magnetic tunnel junction 20.

The read-write control method of the memory provided by the embodiment of the application is used for any memory provided by the above embodiments.

Optionally, during a reading phase of the memory, a first level is input to the gate 13 of the transistor 10 in the memory cell 200 to be read through the word line 201, so that the transistor 10 is in a conductive state, and a change of current or voltage and a degree of change are sensed through one bit line 202 or one source line 203, so that reading of the stored data of the magnetic tunnel junction 20 is realized. In the following, it is explained how the magnetic tunnel junction 20 memory data reading is implemented by sensing the current change through the source line 203.

Specifically, when the data stored in the magnetic tunnel junction 20 is "1", the MTJ assumes a high resistance state, and when a read signal is transmitted to the magnetic tunnel junction 20 through one bit line 202, that is, a second level is applied to the magnetic tunnel junction 20 through one bit line 202, one source line 203 is kept at a reference level, and the reference level is smaller than the second level, because the MTJ assumes a high resistance state, it is difficult to measure a relatively significant current through the magnetic tunnel junction 20, that is, the source line 203, and in this case, it is determined that the read data is "1", that is, the data stored in the magnetic tunnel junction 205 of the memory cell 200 to be read can be sensed through one source line 203 is "1".

When the data stored in the magnetic tunnel junction 20 is "0", the MTJ assumes a low resistance state, and when a read signal is transmitted to the magnetic tunnel junction 20 through one bit line 202, that is, a second level is applied to the magnetic tunnel junction 20 through one bit line 202, one source line 203 is kept at a reference level, and the reference level is smaller than the second level, since the MTJ assumes a low resistance state, a relatively significant current can be measured through the magnetic tunnel junction 20, that is, the source line 203, and the read data is determined to be "0", that is, the data stored in the magnetic tunnel junction 20 of the memory cell 200 to be read can be sensed to be "0" through one source line 203.

It will be appreciated by those skilled in the art that by controlling the potential difference between the bit line 202 and the source line 203, the flow of current can be controlled to effect reading of the stored data of the magnetic tunnel junction 20 in the memory cell 200 to be read.

Optionally, during a writing phase of the memory, a first level is input to the gate 13 of the transistor 10 in the memory cell 200 to be read through the word line 201, so that the transistor 10 is in a conductive state, and a direction of flowing through the magnetic tunnel junction 20 in the memory cell 200 to be written is controlled through the bit line 202 and the two source lines 203, so that a storage signal transmitted through the bit line 202 or the source line 203 is written into the magnetic tunnel junction 20. The following describes how the magnetic tunnel junction 20 data storage is implemented, taking as an example the transfer of a storage signal to the memory cell 200 to be written via the source line 203.

Specifically, when the storage signal is "1", a third level is applied to the source 11 of the transistor 10 to be written into the memory cell 200 through the source line 203, the bit line 202 is kept at the reference level, the third level is greater than the reference level, the potential difference across the magnetic tunnel junction 20 is large enough due to the application of the third level to both source lines 203, the current flows from the source line 203 to the bit line 202, and during the process of the current flowing through the magnetic tunnel junction 20, the magnetic field direction of the free layer of the magnetic tunnel junction 20 is changed and opposite to the magnetic field direction of the fixed layer, so that the magnetic tunnel junction 20 presents a high resistance state "1", thereby realizing the storage of the data "1".

Conversely, by controlling the magnetic field direction of the free layer of the magnetic tunnel junction 20 to change and be the same as the magnetic field direction of the fixed layer, the magnetic tunnel junction 20 is made to assume a low-resistance state "0", thereby realizing the storage of data "0".

It is understood by those skilled in the art that the write current in MRAM is often more than ten times the read current, and if a single channel transistor is used, the current flowing through the transistor is larger during the write phase, and as the frequency of use increases, the loss speed of the single channel transistor is greatly increased, and the service life of the single channel transistor is reduced. Therefore, in the embodiment of the present application, by providing the dual-channel vertical transistor 10, the current passing through each sub-transistor can be reduced, so that the loss speed of the transistor 10 can be reduced, and the service life of the transistor 10 can be prolonged.

Based on the same inventive concept, the embodiment of the present application provides a method for manufacturing a memory, a flow chart of which is shown in fig. 5, the method includes the following steps S501-S503:

s501, forming a stacked structure of a plurality of source lines and a plurality of array arrangements on one side of a substrate based on a patterning process; the stacked structure comprises a source electrode, a sacrificial semiconductor structure and a drain electrode which are arranged in a stacked mode, wherein a first semiconductor layer and a second semiconductor layer are respectively arranged on two outer side walls of the sacrificial semiconductor structure, and the source electrodes of any two adjacent stacked structures in the row direction are connected with the same source line.

S502, removing the sacrificial semiconductor structure.

S503, forming word lines and grid electrodes at least partially positioned between the first semiconductor layer and the second semiconductor layer to obtain transistors arranged in an array; the gates of the transistors in the same row are connected to the same word line.

And S504, sequentially forming a connection structure and a magnetic tunnel junction on one side of the source electrode of the transistor far away from the substrate.

S505, forming a bit line on a side of the magnetic tunnel junction away from the substrate.

In order to facilitate the reader to intuitively understand the manufacturing method of the memory and the advantages of the memory manufactured by using the method provided in the embodiments of the present application, the following will be described in detail with reference to fig. 6 to 20.

In one embodiment of the present application, the forming a stacked structure of the plurality of source lines 203 and the plurality of array arrangements on one side of the substrate based on the patterning process in the step S501 includes: sequentially forming a multi-source line 203 and a plurality of stacked structure rows 112 disposed at intervals from each other on one side of a substrate based on a patterning process, the stacked structure rows 112 including a source row 1011, a sacrificial semiconductor row 1121 and a drain row 1031 disposed in a stacked manner; forming a semiconductor line 113 on both outer sidewalls of the sacrificial semiconductor line 1121 by an epitaxial process; the stack rows 112 and the semiconductor rows 113 are patterned to form an array of stacked structures 116.

In one embodiment of the present application, the step of sequentially forming the multi-source line 203 and the plurality of stacked structure rows 112 disposed at intervals on one side of the substrate based on the patterning process includes: forming a plurality of initial stacked structure rows 106 disposed at intervals from each other on one side of the substrate 100 based on a patterning process, the initial stacked structure rows 106 including source rows 1011, initial sacrificial semiconductor rows 1021, and drain rows 1031 disposed in a stacked manner; etching a portion of the substrate 100 and a portion of the source line 1011 between two adjacent stacked structure lines 106 to form a first arcuate slot 108 extending partially below the two stacked structure lines 106; forming a source line 203 in the first arc-shaped groove 108 by adopting a metal silicide process, wherein the source line 203 is conformal with the surface of the first arc-shaped groove 108; the initial sacrificial semiconductor lines 1021 are laterally etched to form sacrificial semiconductor lines 1121. Optionally, the method specifically comprises the following steps:

first, a first conductor layer 101, a sacrificial semiconductor layer 102, and a second conductor layer 103 are sequentially formed on one side of a substrate 100, a first photoresist structure 104 is formed on one side of the second conductor layer 103 away from the substrate 100, and first mask structures 105 are formed on both sidewalls of the first photoresist structure 104, as shown in fig. 6.

Optionally, the first conductor layer 101 and the second conductor layer 103 are made of doped semiconductor materials, and optionally, the first conductor layer 101 and the second conductor layer 103 are both N-type doped, and the doping degree can be determined according to specific manufacturing process or requirement; the sacrificial semiconductor layer 102 is GeSi (silicon germanium); the material of the first mask structure 105 may be silicon oxide.

Optionally, in this embodiment of the present application, the first conductor layer 101, the sacrificial semiconductor layer 102 and the second conductor layer 103 are formed by using an epitaxial growth process, so that the thickness of each film layer is convenient to be precisely controlled, particularly, the thickness of the sacrificial semiconductor layer 102 is precisely controlled, the dimensions of the semiconductor layer 12 and the gate 13 obtained by subsequent manufacturing are convenient to be precisely controlled, so that the manufacturing precision of a transistor can be ensured, the uniformity of the transistor performance of each storage unit in the memory can be further ensured, and the performance of the memory can be further ensured.

Alternatively, in the embodiments of the present application, the respective film structures may be fabricated by using deposition processes such as CVD (Chemical Vapor Deposition ), PVD (Physical Vapor Deposition, physical vapor deposition), and ALD (Atomic Layer Deposition ).

In this embodiment, the first photoresist structure 104 is removed, and then the second conductor layer 103, the sacrificial semiconductor layer 102 and a portion of the first conductor layer 101 are etched with the first mask structure 105 to form a plurality of initial stacked structure rows 106 disposed at intervals, as shown in fig. 7.

In this embodiment of the present application, the first mask structure 105 is a hard mask, and can perform a self-aligned etching function in the process of etching the second conductor layer 103, the sacrificial semiconductor layer 102, and a part of the first conductor layer 101, so as to ensure etching accuracy.

As shown in fig. 7, the initial stacked structure rows 106 extend in a second direction parallel to the substrate 100 and perpendicular to the first direction, which is the extending direction of the source lines 203, and the plurality of initial stacked structure rows 106 are spaced apart in the first direction. As shown in fig. 7, the initial stacked structure row 106 includes a source row 1011, an initial sacrificial semiconductor row 1021, and a drain row 1031, which are stacked. As shown in fig. 7, a part of the first conductor layer 101 which is not etched exists between two adjacent initial stacked structural rows 106, so that the situation of over etching in the process of forming the source line 203 is prevented.

Then, a protective layer is formed covering the top and side walls of the initial stacked structural rows 106. The protective layer can function to protect the initial stacked structural rows 106 from being etched or doped during subsequent fabrication. The protective layer is a whole layer structure and also covers the first conductor layer 101 between two adjacent initially stacked structural rows 106, which is not etched. Optionally, the protective layer is made of a material including silicon oxide.

Next, a portion of the substrate 100 and a portion of the source line 1011 between two adjacent stacked structure lines 106 are etched to form a first arc groove 108 extending partially below the two stacked structure lines 106, as shown in fig. 8.

In this embodiment, as shown in fig. 8, after the protective layer is etched, a protective structure 1071 is formed.

Then, a source line 203 is formed in the first arc groove 108 using a metal silicide process, including: filling a metal material, such as titanium, cobalt, etc., between the first arc-shaped groove 108 and the adjacent two initial stacked structural rows 106 to form a metal layer 109, as shown in fig. 9, the metal layer 109 completely fills the first arc-shaped groove 108, and the upper surface of the metal layer 109 is flush with the upper surface of the initial sacrificial semiconductor rows 1021 of the initial stacked structural rows 106; the metal layer 109 is treated by an annealing process such that the metal layer 109 reacts with a portion of the substrate 100 and a portion of the source line 1011 to form a source line 203 including metal silicide, and then the unreacted metal layer 109 is removed, as shown in fig. 10.

As shown in fig. 10, the source line 203 follows the surface of the first arc-shaped groove 108. One source line 203 is connected to each source row 1011 of two adjacent initial stacked structural rows 106.

Next, a dielectric material, such as silicon oxide, is deposited using a deposition process and treated using a CMP (Chemical Mechanical Polishing ) process, forming a first planarization layer 111, as shown in fig. 11. Alternatively, the protective structure 1071 and the first flat layer 111 are made of the same material, and thus both are represented by the first flat layer 111 in fig. 11, and the protective structure 1071 is not represented in fig. 11.

Then, portions of the first planarization layer 111 and the first mask structure 105 are removed by an etching process to form a first planarization structure 1111, and an upper surface of the first planarization structure 1111 is flush with an upper surface of the source line 1021 such that both sidewalls of the initial sacrificial semiconductor line 1021 are exposed, as shown in fig. 12.

Next, the initial sacrificial semiconductor line 1021 is laterally etched using a selective etching process to form a sacrificial semiconductor line 1121 such that both sidewalls of the sacrificial semiconductor line 1121 are retracted relative to the source line 1011 and the drain line 1031, resulting in a stacked structure line 112, as shown in fig. 13, the stacked structure line 112 including the stacked arrangement of the source line 1011, the sacrificial semiconductor line 1121, and the drain line 1031.

In one embodiment of the present application, the step of forming the semiconductor rows 113 on the two outer sidewalls of the sacrificial semiconductor rows 1121 by using an epitaxial process specifically includes the following steps:

First, a semiconductor layer is formed on the exposed surfaces of the source line 1011, the sacrificial semiconductor line 1121, and the drain line 1031 by an epitaxial process.

Since the source line 1011, the sacrificial semiconductor line 1121, and the drain line 1031 are formed based on an epitaxial process, the epitaxial process may be continued to form a semiconductor layer having an outer surface conforming to the outer surfaces of the source line 1011, the sacrificial semiconductor line 1121, and the drain line 1031.

Then, a part of the semiconductor layer is removed by an etching process to form semiconductor lines 113 on both outer sidewalls of the sacrificial semiconductor lines 1121, as shown in fig. 14.

In one embodiment of the present application, the patterning of the stacked structure rows 112 and the semiconductor rows 113 in the above steps forms the stacked structure 116 arranged in an array, specifically includes the following steps: forming a mask structure on one side of the stacked structure row away from the substrate; the extending direction of the mask structure is perpendicular to the extending direction of the stacked structure rows; and etching the stacked structure row and the semiconductor row by adopting a self-aligned etching process based on the mask structure to form a stacked structure and a semiconductor layer.

Alternatively, first, a dielectric material such as silicon oxide is deposited using a deposition process and treated using a CMO process to form a second planar layer 114, as shown in FIG. 15. Next, a mask structure is formed on a side of the second planarization layer 114 away from the substrate 100, where the mask structure includes first sub-mask structures 1151 disposed at intervals, and as shown in fig. 16, an extension direction of the first sub-mask structures 1151 is perpendicular to an extension direction of the stacked structure rows 112.

In this embodiment, fig. 5 to 15 are schematic cross-sectional views along a first direction, a second direction perpendicular to the first direction, fig. 16 is a schematic cross-sectional view along AA direction after the mask structure is prepared from the structure shown in fig. 15, and fig. 16 is usedThe first direction is shown as being the direction into the page.

Then, based on the first sub-mask structure 1151, the stacked structure row 112 and the semiconductor row 113 are etched using a self-aligned etching process to form the stacked structures 116 and the semiconductor layers 12, the stacked structures 116 are arranged in an array, and the second flat layer 114 that is not etched is removed, as shown in fig. 17.

In this embodiment, the first sub-mask structure 1151 is a hard mask, and the manufacturing material includes silicon oxide, which can perform a self-aligned etching function in the process of etching the stacked structure line 112 and the semiconductor line 113, so as to ensure etching accuracy.

As shown in fig. 17, the stacked structure 116 includes a source 11, a drain 14, a sacrificial semiconductor structure is formed after the sacrificial semiconductor line 1121 is etched, a semiconductor layer 12 is formed after the semiconductor line 113 is etched, the sacrificial semiconductor structure is not visible due to the shielding of the semiconductor layer 12, and the source 11 is connected to the bit line 202. FIG. 17 is a schematic view of a cross-sectional structure taken along the second direction, as used in FIG. 17 The first direction is shown as being the direction into the page.

In one embodiment of the present application, the removing the sacrificial semiconductor structure in step S502 specifically includes: a selective etching process is used to remove the sacrificial semiconductor structure.

In one embodiment of the present application, the step S503 of forming the word line and the gate electrode at least partially located between the first semiconductor layer and the second semiconductor layer in the semiconductor layers to obtain the transistors arranged in an array specifically includes the following steps:

first, a first gate insulating layer 151 conforming to the peripheral wall of a cavity formed by surrounding the source electrode 11, the inner sidewalls of the two semiconductor layers 12, and the drain electrode 14 and a second gate insulating layer 152 conforming to the peripheral wall of a recess formed by surrounding the source electrode 11, the outer sidewalls of the two semiconductor layers 12, and the drain electrode 14 are formed by a deposition process, so as to obtain a gate insulating layer 15, so that the gate electrode 13 is insulated from the source electrode 11, the drain electrode 14, and the semiconductor layer 12.

Then, an atomic layer deposition process is used to deposit a metal material, so that the metal material fills the cavity formed by enclosing the first gate insulating layer 151 and fills the groove formed by enclosing the second gate insulating layer 152, thereby forming an initial word line layer.

Next, the initial word line layer is patterned to form word lines 201, first gates 131 and second gates 132, as shown in fig. 18. Fig. 18 is a schematic sectional structure along the first direction, and the second direction is the direction out of the paper surface as indicated by +.in fig. 18.

Alternatively, the initial word line layer may be patterned by SOH (Spin On Hard mask, spin-on-hard-mask) process, forming a self-leveling planarization layer on one side of the initial word line layer, and then forming a photoresist structure on one side of the planarization layer, and etching the initial word line layer using the photoresist structure as a mask.

In this embodiment, the first gate 131 is disposed in a cavity formed by enclosing the first gate insulating layer 151, so that the first gate 131 is insulated from the semiconductor layer 12, the source 11 and the drain 14. The second gate 132 is disposed in a recess formed by enclosing the second gate insulating layer 152, so that the second gate 132 is insulated from the semiconductor layer 12, the source 11 and the drain 14.

In this embodiment, the outer profiles of the source electrode 11 and the drain electrode 14 of the two semiconductor layers 12 are laterally retracted, and since the source electrode 11 and the drain electrode 14 are prepared based on the epitaxial growth process, the distance between the source electrode 11 and the drain electrode 14 can be precisely controlled along the direction perpendicular to the substrate 100, the gate insulating layer 15 is formed by the ALD process, the thickness of the gate insulating layer 15 can be precisely controlled, so that the size of the cavity formed by the first gate insulating layer 151 and the size of the groove formed by the second gate insulating layer 152 can be precisely controlled, the sizes of the first gate 131 and the second gate 132 formed can be precisely controlled, particularly the lengths of the first gate 131 and the second gate 132 can be precisely controlled, the preparation precision of the gate 13 can be improved, the preparation precision of the memory unit can be ensured, the uniformity of the performance of each memory unit in the memory can be ensured, and the performance of the memory can be ensured.

In one embodiment of the present application, in the step S504, a connection structure and a magnetic tunnel junction are sequentially formed on a side of the source electrode of the transistor away from the substrate, and the method specifically includes the following steps:

first, a deposition process is used to deposit a dielectric material, such as silicon oxide, and after a planarization process and patterning, a dielectric structure 50 is formed that includes openings that expose portions of the drain 14.

Then, a metal material, such as titanium, cobalt, etc., is deposited in the opening and an annealing process is used to form silicide structure 41; the thickness of the silicide structure 41 is less than the depth of the opening.

Next, a metal material is deposited on a side of the silicide structure 41 away from the substrate 100, covering the silicide structure 41 and filling the opening, forming a metal structure 42 that is flush with the upper surface of the dielectric structure 50, resulting in a connection structure 40, as shown in fig. 19.

An initial magnetic tunnel junction layer, a hard mask layer, and a second photoresist structure are then formed in sequence on the side of dielectric structure 50 and metal structure 42 remote from substrate 100.

Next, the hard mask layer is patterned using the second photoresist structure as a mask, forming a hard mask structure 30, and the initial magnetic tunnel junction layer is patterned using the hard mask structure 30 as a mask, forming a magnetic tunnel junction 20. The hard mask structure 30 may function to protect the magnetic tunnel junction 20 during formation of the magnetic tunnel junction 20.

An encapsulation layer 60 is then deposited on the side of the hard mask structure 30 remote from the substrate 100, the encapsulation layer 60 covering the sidewalls of the magnetic tunnel junction 20, as shown in fig. 20.

In one embodiment of the present application, the forming a bit line on the side of the magnetic tunnel junction away from the substrate in the step S405 specifically includes the following steps:

first, an isolation layer 70 including an opening is formed on a side of the encapsulation layer 60 away from the substrate 100, the opening of the isolation layer 70 exposing a portion of the hard mask structure 30.

Next, a metal material is deposited within the openings of isolation layer 70 to form bit lines 202.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

in the memory provided in this embodiment of the present application, one end of one source line 203 is electrically connected to the source 11 of each transistor 10 in one column of memory cells 200, and the other end of the source line 203 is electrically connected to the source 11 of each transistor 10 in another column of memory cells 200, so that two columns of memory cells 200 can be controlled simultaneously by one source line 203, thereby reducing the number of source lines 203 in the memory, reducing the difficulty in routing the memory, and reducing the design cost and manufacturing cost of the memory.

Those of skill in the art will appreciate that the various operations, methods, steps in the flow, actions, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed in this application may be alternated, altered, rearranged, split, combined, or eliminated. Further, steps, measures, schemes in the prior art with various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

The foregoing is only a part of the embodiments of the present application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical ideas of the present application are adopted without departing from the technical ideas of the solutions of the present application, and also belong to the protection scope of the embodiments of the present application.

Claims (10)

1. A memory, comprising: a plurality of rows and columns of memory cells, a plurality of rows of word lines, a plurality of columns of bit lines, and a plurality of columns of source lines;

the memory cell includes: a transistor and a magnetic tunnel junction; the transistor includes a first channel and a second channel;

one end of the magnetic tunnel junction is electrically connected with the drain electrode of the transistor, and the other end of the magnetic tunnel junction is electrically connected with the bit line; the grid electrode of the transistor in each memory cell of the same row is electrically connected with the word line; the source electrode of each transistor in a column of the memory unit is electrically connected with two source lines at the same time, and the two source lines are respectively electrically connected with the first channel and the second channel; in any two adjacent columns of memory cells, one end of one source line is electrically connected with the source electrode of each transistor in one column of memory cells, and the other end of the source line is electrically connected with the source electrode of each transistor in the other column of memory cells.

2. The memory of claim 1 wherein the transistor is a vertical transistor, the transistor and the magnetic tunnel junction being stacked in a direction perpendicular to the substrate.

3. The memory according to claim 2, wherein the transistor includes a source electrode, a semiconductor layer, and a drain electrode which are sequentially stacked over a substrate;

the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are arranged on the same side of the source electrode at intervals and respectively contacted with the source electrode; the first semiconductor layer includes a first channel in a case of conduction, and the second semiconductor layer includes a second channel in a case of conduction;

at least a portion of the gate electrode is located in the spaced apart region of the first semiconductor layer and the second semiconductor layer.

4. The memory according to claim 3, wherein the first semiconductor layer and the second semiconductor layer are arranged at intervals in a row direction;

the cross section of the source line is arc-shaped, the top of the arc-shaped source line is provided with a notch, one end of the source line, which is close to the notch, is a first part, and the other end of the source line is a second part; the first portion is connected to the first semiconductor layer in at least some of the memory cells in one column of the memory cells, and the second portion is connected to the second semiconductor layer in at least some of the memory cells in another column of the memory cells.

5. The memory of claim 3, wherein the gate comprises a first gate and a second gate connected to each other;

the first gate is a gate located between the spaced apart regions of the first and second semiconductor layers;

the second gate is disposed on the outer sidewalls of the first semiconductor layer and the second semiconductor layer, and is insulated from the first semiconductor layer, the second semiconductor layer, the source electrode, and the drain electrode.

6. The memory of claim 5, wherein the word line comprises a plurality of first subsections and second subsections that are alternately connected in sequence;

the first subsection surrounds the first grid electrode and the second grid electrode and is connected with the first grid electrode and the second grid electrode;

one end of the second sub-section is connected with one first sub-section, and the other end of the second sub-section is connected with the other first sub-section.

7. The memory of claim 5, further comprising:

the projection of the outer contours of the source electrode and the drain electrode on the substrate and the projection of the outer contours of the first semiconductor layer, the second semiconductor layer and the first grid electrode on the substrate are surrounded, so that the source electrode and the drain electrode protrude outwards relative to the first semiconductor layer, the second semiconductor layer and the first grid electrode;

And the projection of the outer contours of the source electrode and the drain electrode on the substrate is overlapped with the projection of the outer contour of the second grid electrode on the substrate.

8. The memory of claim 1, wherein the memory unit further comprises: the connecting structure is arranged at one side of the drain electrode, which is far away from the source electrode;

the magnetic tunnel junction is arranged on one side of the connecting structure away from the drain electrode.

9. A read-write control method of a memory according to any one of claims 1 to 8, comprising:

in a reading stage, controlling a transistor in a memory cell to be read to be in a conducting state through a word line, and transmitting a reading signal to a magnetic tunnel junction of the memory cell to be read through one of a bit line or one source line so that the other of the bit line or the one source line senses stored data of the magnetic tunnel junction;

in the writing stage, a transistor in a memory cell to be written is controlled to be in a conducting state through a word line, and the direction of flowing through a magnetic tunnel junction in the memory cell to be written is controlled through a bit line and two source lines, so that a storage signal transmitted by the bit line or the source line is written into the magnetic tunnel junction.

10. A method of manufacturing a memory, comprising:

forming a stacked structure of a plurality of source lines and a plurality of array arrangements on one side of a substrate based on a patterning process; the stacked structure comprises a source electrode, a sacrificial semiconductor structure and a drain electrode which are arranged in a stacked mode, wherein a first semiconductor layer and a second semiconductor layer are respectively arranged on two outer side walls of the sacrificial semiconductor structure, and the source electrodes of any two adjacent stacked structures in the row direction are connected with the same source line;

removing the sacrificial semiconductor structure;

forming word lines and grid electrodes at least partially positioned between the first semiconductor layer and the second semiconductor layer to obtain transistors arranged in an array; the grid electrode of each transistor positioned in the same row is connected with the same word line;

sequentially forming a connection structure and a magnetic tunnel junction on one side of a source electrode of the transistor, which is far away from the substrate;

a bit line is formed on a side of the magnetic tunnel junction remote from the substrate.