CN115443534A

CN115443534A - Memory and manufacturing method thereof

Info

Publication number: CN115443534A
Application number: CN202080100140.XA
Authority: CN
Inventors: 景蔚亮; 王正波; 崔靖杰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2022-12-06
Also published as: WO2022000344A1

Abstract

The embodiment of the application provides a memory and a manufacturing method thereof, which relate to the field of storage. The memory, comprising: the stacked layer comprises a first conductive layer and a second conductive layer which are arranged in an overlapped mode, and an isolation layer arranged between the adjacent first conductive layer and the second conductive layer; the stacked layer comprises a vertical channel penetrating through the stacked layer, and a semiconductor film is formed on the inner side wall of the vertical channel; the first conductive layer comprises a conductive material, a charge trapping film layer is formed between the conductive material of the first conductive layer and the semiconductor film, a channel penetrating through the semiconductor film is formed on the semiconductor film at a position opposite to the charge trapping film layer, the second conductive layer comprises a conductive material, an electrode structure is formed at a position where the semiconductor film is in contact with the conductive material of the second conductive layer, and the electrode structure comprises a source electrode or a drain electrode.

Description

Memory and manufacturing method thereof

Technical Field

The present application relates to the field of memory, and in particular, to a memory and a method for manufacturing the same.

Background

Flash memory, flash memory for short, is a non-volatile memory. In general, flash memories have mainly two structures, a NAND (NAND) structure and a NOR (NOR) structure. Any memory cell of the NOR-structured flash memory can independently complete read-write operation, has a random access function, and can be used for data storage and executable program code storage. The NAND flash memory cannot complete independent read-write operation of the memory cells due to the serial connection characteristic of the memory cells, and needs to be erased in blocks.

With the development of three-dimensional (3D) semiconductor packaging technology, flash memories gradually come to 3D storage products in a trend of increasing memory density. Currently, more and more semiconductor products adopt vertically developed package technologies such as stacked dies, package on package (PoP) or through-silicon vias (TSV), and the vertical package has significant advantages in terms of density, weight and configurability. The mainstream process of the three-dimensional memory chip Foundry (FAB) is the gate-all-around nanowire (GAA NW) vertical channel (vertical channel) manufacturing technology, and therefore, the problem of how to produce a nonvolatile memory by using the GAA NW vertical channel manufacturing technology is to be solved.

Disclosure of Invention

The present application provides a memory device and a method of fabricating the same that can be produced by a surrounding gate nanowire vertical channel fabrication technique.

In a first aspect, a memory is provided. The structure of the memory comprises: the stacked layer comprises a first conductive layer and a second conductive layer which are arranged in an overlapped mode, and an isolation layer arranged between the adjacent first conductive layer and the second conductive layer; the stacking layer comprises a vertical channel penetrating through the stacking layer, and a semiconductor film is formed on the inner side wall of the vertical channel; the first conductive layer comprises a conductive material, a charge trapping film layer is formed between the conductive material of the first conductive layer and the semiconductor film, a channel penetrating through the semiconductor film is formed on the semiconductor film at a position opposite to the charge trapping film layer, the second conductive layer comprises a conductive material, an electrode structure is formed at a position where the semiconductor film is in contact with the conductive material of the second conductive layer, and the electrode structure comprises a source electrode or a drain electrode. Wherein the above-described structure may be formed on a substrate. In the above solution, the memory includes a vertical channel penetrating through the stacked layers, and a semiconductor thin film is formed on an inner sidewall of the vertical channel, a charge trapping film layer is disposed between the conductive material of the first conductive layer and the channel on the semiconductor thin film, and the electrode structures on both sides of the channel are respectively in contact with the conductive material of one second conductive layer to form the memory cells of the memory, so that data storage can be achieved, and thus the first conductive layer of each memory cell is disposed around the semiconductor thin film in the vertical channel as a gate, and the electrode structures are formed on both sides of the channel in the semiconductor thin film, which can be directly manufactured by a gate-around nanowire manufacturing technique. In addition, the storage units are mutually independent, and the storage units at the top and the bottom of the vertical channel are not influenced mutually; the length of the channel in the memory unit is consistent with the thickness of the first conductive layer, and the length of the channel can be determined by the process for preparing the first conductive layer, so that a short memory unit channel can be made, and the high performance of the device can be realized.

In one possible implementation, the charge trapping film layer includes any one of: oxide-nitride-oxide ONO structures, floating gate FG structures, and ferroelectric Ferro structures.

In one possible implementation, the conductive material of the first conductive layer includes a metal material. For example, tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), ruthenium (Ru), iridium (Ir), cobalt (Co), aluminum (Al), copper (Cu), etc.

In one possible implementation, the semiconductor thin film comprises polycrystalline silicon; the conductive material of the second conductive layer comprises doped polysilicon, and the electrode structure comprises doped polysilicon. The concentration of the dopant of the electrode structure is less than that of the dopant of the second conductive layer. Thus, since the second conductive layer uses polysilicon having a high concentration of the dopant, the electrode can be formed generally by diffusing the dopant in the second conductive layer into the semiconductor thin film. The type of the dopant is P type or N type. Typical dopants include: phosphorus (P), arsenic (As), boron (B), gallium (Ga), etc., and for example, as the dopant element phosphorus (P), arsenic (As), etc. having a valence of 5; the P-type doping of the polysilicon may use 3-valent dopant elements such as boron (B) and gallium (Ga). In one example, the semiconductor thin film has a thickness of 200-600A (angstroms).

In one possible implementation, the thickness of the charge trapping film layer is less than 50A. Illustratively, the charge trapping film layer includes a first oxide layer, a nitride layer, and a second oxide layer, wherein the first oxide layer, the nitride layer, and the second oxide layer are sequentially disposed between the first conductive layer and the semiconductor thin film, one side of the first oxide layer is in contact with a conductive material included in the first conductive layer, the other side of the first oxide layer is in contact with one side of the nitride layer, the other side of the nitride layer is in contact with one side of the second oxide layer, and the other side of the second oxide layer is in contact with a channel on the semiconductor thin film. The thickness of the charge trapping layer is less than 50A, and compared with the conventional charge trapping layer, the thickness of the charge trapping layer is less than 50A, so that the access speed and the erasable times of the memory cell can be improved. Wherein the first oxide layer is also called top oxide layer, and can be made of Al ₂ O ₃ 、Ta ₂ O ₅ Or SiO ₂ And the like; a nitride layer, which can be silicon nitride; the second oxide layer, also called tunneling oxide layer, may be made of Al ₂ O ₃ 、Ta ₂ O ₅ Or SiO ₂ And the like.

In one possible implementation mode, a filler is arranged in a channel groove surrounded by the semiconductor thin film; the filler is oxide. Such as silicon oxide SiO ₂ . The filler serves to ensure structural stability.

In one possible implementation, the isolation layer is an electrically insulating material. The electrically insulating material may be an oxide, such as silicon oxide SiO ₂ Wherein the isolating layer mainly functions as a first conductive layer and a second conductive layerInsulation of the layers.

In one possible implementation manner, the first conductive layer is connected with the word line, the second conductive layer on one side of the first conductive layer is connected with the bit line, and the second conductive layer on the other side of the first conductive layer is connected with the source line.

In a second aspect, an embodiment of the present application further provides a method for manufacturing a memory, including the following steps: manufacturing a stacked structure, wherein the stacked structure comprises a sacrificial layer and a second conductive layer which are arranged in an overlapped mode, and an isolation layer is arranged between the sacrificial layer and the second conductive layer; making a vertical channel on the stacked structure, wherein the vertical channel penetrates through the stacked structure; manufacturing a semiconductor film on the inner side wall of the vertical channel; manufacturing an electrode structure on the semiconductor film, wherein the electrode structure is in contact with the conductive material included in the second conductive layer; removing the sacrificial layer, and manufacturing a charge trapping film layer on the semiconductor film exposed at the position of the sacrificial layer; fabricating a first conductive layer at a location of the sacrificial layer, wherein the first conductive layer comprises a conductive material in contact with the charge trapping film layer.

The memory manufactured by the manufacturing method of the memory comprises a vertical channel penetrating through the stacked layers, a semiconductor film is formed on the inner side wall of the vertical channel, a charge capture film layer is arranged between the first conducting layer and a channel on the semiconductor film, and electrode structures on two sides of the channel are respectively connected with a conducting material contained in the second conducting layer, so that the storage unit of the memory can realize data storage; the first conductive layer of each memory cell is used as a gate and surrounds the semiconductor film in the vertical channel, and the two sides of the channel in the semiconductor film are respectively provided with an electrode structure, so that the memory cell can be directly manufactured by a surrounding gate nanowire manufacturing technology. In addition, the storage units are independent from each other, and the storage units at the top and the bottom of the vertical channel are not influenced by each other; the length of the channel in the memory cell is consistent with the thickness of the first conductive layer, and in the manufacturing process, the length of the channel is determined by the thickness of the sacrificial layer, so that a short channel of the memory cell can be made, and high performance of the device can be realized.

In one possible implementation, the semiconductor thin film comprises polysilicon; the conductive material of the second conductive layer comprises polycrystalline silicon with a dopant, and the electrode structure comprises polycrystalline silicon with a dopant; fabricating an electrode structure on the semiconductor thin film, comprising: and diffusing the dopant in the second conductive layer to the semiconductor film through a high-temperature annealing process to form the electrode structure. For example: fabricating an electrode structure on the semiconductor thin film includes fabricating a drain electrode and a source electrode of a memory cell on the semiconductor thin film. In some embodiments, the semiconductor thin film comprises polysilicon; the second conductive layer is made of polycrystalline silicon with dopant, and the electrode structure is made of polycrystalline silicon with dopant. The concentration of the dopant of the electrode structure is less than the concentration of the dopant of the second conductive layer. The type of dopant is P-type or N-type. Specifically, the dopant in the second conductive layer is diffused to the semiconductor film through a high-temperature annealing process to form the electrode structure. For example, the drain and source of the memory cell are fabricated using a high temperature annealing process (greater than 500 ℃, about 1000 ℃). At high temperature, the heavily doped polysilicon P-type or N-type ions will diffuse out of the sidewall semiconductor film to form drain and source junctions. Since the semiconductor thin film is thin like SOI (silicon-on-insulator, i.e., silicon on an insulating substrate), the junction created by the out-diffusion is not deep. The reaction speed of the external diffusion can be realized by controlling the temperature, and the consistency of the external diffusion can be effectively controlled by using a furnace tube (furnace).

In one possible implementation manner, fabricating a charge trapping film layer on the semiconductor thin film exposed at the position of the sacrificial layer includes: and depositing a charge trapping film layer on the semiconductor thin film exposed at the position of the sacrificial layer by a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) process.

In one possible implementation manner, after the semiconductor thin film is fabricated on the inner side wall of the vertical channel, the method further includes: and manufacturing a filler in the channel groove surrounded by the semiconductor film. The filler is oxide. For example, silicon oxide SiO ₂ . The filler serves to ensure structural stability.

In one possible implementation, the sacrificial layer is silicon nitride.

In a third aspect, an electronic device is provided, which includes a circuit board and a nonvolatile memory connected to the circuit board, where the nonvolatile memory is the above memory.

Drawings

Fig. 1 is a schematic structural diagram of a storage system according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a memory system according to another embodiment of the present application;

FIG. 3 is a schematic structural diagram of a memory system according to yet another embodiment of the present application;

FIG. 4 is an equivalent circuit diagram of a non-volatile memory according to still another embodiment of the present application;

FIG. 5 is a schematic structural diagram of a memory according to an embodiment of the present application;

FIG. 5a is a schematic structural diagram of a memory according to another embodiment of the present application;

FIG. 6 is a schematic diagram of a charge trapping layer of an ONO structure according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a charge trapping film layer of a floating gate FG structure according to an embodiment of the present application;

FIG. 8 is a flow chart illustrating a method for fabricating a memory according to an embodiment of the present disclosure;

FIG. 9 is a first schematic structural diagram illustrating a manufacturing process of a memory according to an embodiment of the present disclosure;

FIG. 10 is a second schematic structural diagram illustrating a manufacturing process of a memory according to an embodiment of the present application;

fig. 11 is a schematic structural diagram three illustrating a manufacturing process of a memory according to an embodiment of the present application;

fig. 12 is a fourth schematic structural diagram in a manufacturing process of a memory according to an embodiment of the present application;

fig. 13 is a fifth structural diagram in a manufacturing process of a memory according to an embodiment of the present application;

fig. 14 is a sixth schematic structural diagram in a manufacturing process of a memory according to an embodiment of the present application;

fig. 15 is a seventh schematic structural diagram in a manufacturing process of a memory according to an embodiment of the present application;

fig. 16 is a structural schematic diagram eight in a manufacturing process of a memory according to an embodiment of the present application.

Detailed Description

The making and using of the various embodiments are discussed in detail below. It should be appreciated that many of the applicable inventive concepts provided herein may be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the specification and techniques, and do not limit the scope of the application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

Circuits or other components may be described or referred to as "performing" one or more tasks. In such cases, "for" is used to connote structure by indicating that the circuit/component includes structure (e.g., circuitry) that performs one or more tasks during operation. Thus, a given circuit/component may be said to be performing that task even when the circuit/component is not currently operational (e.g., not open). Circuits/components used with the term "for" include hardware, such as circuits that perform operations, and the like.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a alone, A and B together, and B alone, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be single or multiple. In addition, in the embodiments of the present application, the words "first", "second", and the like do not limit the number and order.

It is noted that the words "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

The technical solution of the present application may be applied to various storage systems using a nonvolatile memory, for example, the technical solution of the present application may be applied to a computer, and may also be applied to a storage system including a memory or a processor and a memory, where the processor may be a Central Processing Unit (CPU), an Artificial Intelligence (AI) processor, a digital signal processor (digital signal processor), a neural network processor, and the like.

Fig. 1 is a schematic structural diagram of a memory system according to an embodiment of the present disclosure, where the memory system may include a memory device, and the memory device may be a nonvolatile memory; optionally, the storage system may further include a CPU, a buffer (cache), a controller, and the like.

In one embodiment, as shown in FIG. 1, the memory system may be an embedded memory, and the memory system includes a CPU, a buffer, and a storage device integrated together. In another embodiment, as shown in FIG. 2, the memory system may be implemented as a stand-alone memory, the memory system including a CPU, a buffer, a controller, and a memory device integrated together, the memory device being coupled to the buffer and the CPU through the controller. In yet another embodiment, as shown in fig. 3, the memory system includes a memory device, and a CPU, a buffer, a controller, and a Dynamic Random Access Memory (DRAM) integrated together, and the memory device may be coupled with the DRAM as an external memory device; wherein the DRAM is coupled to the buffer and the CPU through the controller. The CPUs in the various memories shown in fig. 1, 2, and 3 may also be replaced with CPU cores (cores).

Generally, a non-volatile memory comprises a plurality of memory cells arranged in an array, and each memory cell is independently controlled for a NOR-type memory, wherein each memory cell corresponds to a transistor switch (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)). As shown in fig. 4, an equivalent circuit diagram of a typical non-volatile memory according to an embodiment of the present invention includes memory cells arranged in an M × N array, which includes a plurality of BLs (BL 0-BL 5) and a plurality of WLs (WL 0-WL 3). Each memory cell is connected to a Bit Line (BL) and a Word Line (WL), respectively. The read-write operation of one memory cell can be controlled by controlling BL and WL. Specifically, when the memory cell is a transistor switch, the source(s) of the transistor switch is connected to the ground Vss through source lines (SL, SL0-SL3 shown in fig. 4), the drain (drain, d) is connected to BL, the gate (gate, g) is connected to WL, the WL can control the on/off of the transistor switch, and the read/write operation of one memory cell can be controlled by inputting a voltage to the drain of the transistor switch through the BL. In order to realize the memory function of the transistor switch, a charge trapping film layer is usually included between the gate g and the channel between the source s and the drain d, and the charge trapping film layer may be any one of the following: oxide-nitride-oxide (ONO) structures, floating Gate (FG) structures, and ferroelectric (Ferro) structures. Different charge trapping film structures have different read/write operation modes, taking an ONO structure as an example: an ONO structure typically includes two oxide layers and a charge trapping layer (which may be nitride) between the oxide layers. The reading process comprises the following steps: when gates g of different memory cells are enabled by word lines WL, different amounts of electric charges are stored in the charge trapping films of the different memory cells, currents of different magnitudes are formed in channels between the source s and the drain d, and the magnitude of the current is determined so that data of each memory cell can be read. The writing process is as follows: when a sufficiently large voltage (for example, 5V voltage) is applied to the gate g through the word line WL, electrons can be driven into the charge trapping film layer through the tunneling effect of the oxide layer to complete the data writing process; the erasing process is as follows: the word line WL applies a reverse voltage to return electrons to the channel by tunneling effect, thereby realizing the erase function. Generally, after the memory cell is written with data, the memory cell in a default state represents a "1" value in the binary code, and during reading, when the gate g is enabled with a specific voltage value, a current flows through the channel between the source s and the drain d. And when subjected to the erase process, the memory cell may be set to a value of "0" in the binary code. Of course, the above only describes a typical control method of the memory cell, and those skilled in the art can reasonably switch to other control methods according to the above control method, for example, after a write process, the memory cell is represented as a "0" value in the binary code, after an erase process, the memory cell is set as a "1" value in the binary code, and so on. In addition, the source s and the drain d of the memory cell described above may be interchanged. Of course, the above equivalent circuit is only a typical circuit structure, and the connection modes of the memory cells, the BL and the WL in different schemes have other forms.

An embodiment of the present application provides a structure of the memory, which is shown in fig. 5, and includes: a stack layer 12, for example, the stack layer 12 may be formed on the substrate 11, the stack layer 12 including a first conductive layer 121 and a second conductive layer 122 that are overlapped, and a separation layer 123 disposed between the adjacent first conductive layer 121 and the second conductive layer 122; the stacked layer 12 includes a vertical channel 13 penetrating the stacked layer 12, and a semiconductor thin film 14 is formed on an inner side wall of the vertical channel 13; the first conductive layer 121 includes a conductive material, and a charge trap film layer 16 is formed between the conductive material of the first conductive layer 121 and the semiconductor thin film 14. The semiconductor thin film 14 has a channel 17 formed through the semiconductor thin film 14 at a position facing the charge trap film layer 16. The second conductive layer 122 includes a conductive material, and an electrode structure 18 is formed at a position where the semiconductor film 14 is in contact with the conductive material of the second conductive layer 122. As described above, electrode structure 18 includes source 18-1 or drain 18-2.

Illustratively, the vertical channel 13 is filled with a filler 15; the filler 15 being an oxide, e.g. silicon oxide SiO ₂ . The filler 15 serves to secure the stability of the structure.

In the structure shown in fig. 5a, in combination with the equivalent circuit shown in fig. 4, of the second conductive layer 122a, the first conductive layer 121, and the second conductive layer 122b which are continuous, the first conductive layer 121 is connected to the word line WL, the second conductive layer 122a on one side of the first conductive layer 121 is connected to the bit line BL, and the second conductive layer 122b on the other side of the first conductive layer 121 is connected to the Source Line (SL).

In the above solution, the memory includes a vertical channel penetrating through the stacked layers, and a semiconductor thin film is formed on an inner sidewall of the vertical channel, a charge trapping film layer is disposed between the conductive material of the first conductive layer and the channel on the semiconductor thin film, and the electrode structures on both sides of the channel are respectively in contact with the conductive material of one second conductive layer to form the memory cells of the memory, so that data storage can be achieved. In addition, the storage units are mutually independent, and the storage units at the top and the bottom of the vertical channel are not influenced mutually; the length of the channel in the memory unit is consistent with the thickness of the first conductive layer, and the length of the channel can be determined by the process for preparing the first conductive layer, so that a short memory unit channel can be made, and the high performance of the device can be realized.

In one example, the charge trapping film layer 16 includes any one of: oxide-nitride-oxide ONO structures, floating gate FG structures and ferroelectric Ferro structures. As shown in the figureAs shown in fig. 6, taking the charge trapping layer 16 of the ONO structure as an example, the charge trapping layer 16 includes a first oxide layer 161, a nitride layer 162 and a second oxide layer 163, wherein the first oxide layer 161, the nitride layer 162 and the second oxide layer 163 are sequentially disposed between the first conductive layer 121 and the semiconductor thin film 14, one side of the first oxide layer 161 is in contact with the conductive material in the first conductive layer 121, the other side of the first oxide layer 161 is in contact with one side of the nitride layer 162, the other side of the nitride layer 162 is in contact with one side of the second oxide layer 163, and the other side of the second oxide layer 163 is in contact with the channel 17. The thickness of the charge trapping layer 16 is usually less than 50A (angstroms), and the driving voltage for the write operation or the read operation is about 5v (less than 10 v). The thickness of the charge trapping layer in the embodiment of the invention is designed to be less than 50A, compared to the conventional thickness of the charge trapping layer 16, so that the access speed and the number of times of erasing and writing of the memory cell can be improved. The first oxide layer 161 is also called top oxide layer, and Al may be used ₂ O ₃ 、Ta ₂ O ₅ Or SiO ₂ And the like; a nitride layer 162, which may be silicon nitride; the second oxide layer 163 is also called a tunnel oxide layer, and Al may be used ₂ O ₃ 、Ta ₂ O ₅ Or SiO ₂ And the like. For the charge trapping film layer 16 of the floating gate FG structure, in combination with the usual morphology of a floating gate FG structure, the FG structure usually comprises two layers of gates (control gates) opposite the channel and an insulating layer between the gates. With particular reference to fig. 7, a floating gate FG structure includes: a control gate kg (i.e., a gate in general), the first conductive layer 121 may be directly used in this application; the floating gate fg (floating gate) is not electrically connected with the outside, is wrapped in an insulating medium (such as a silicon dioxide medium layer) and is floating, and in the application, the floating gate fg can be surrounded by the insulating medium arranged on two sides. The floating gate fg can trap and store electrons, and since there is no external loop, the electrons will not be lost even after power is turned off. The amount of electrons stored in the floating gate fg structure can change the conduction of the transistor switchVoltage, i.e., threshold voltage Vth; different threshold voltages Vth may represent different states, such as a "0" or "1" value in a binary code, enabling storage of data. The ferroelectric Ferro structure is based on MOSFET, and the insulating material of the grid g is replaced by ferroelectric material with high dielectric constant. For example, a ferroelectric material is provided between the conductive material of the first conductive layer 121 and the channel 17 with the first conductive layer 121 as the gate g. The ferroelectric material may include at least one of the following materials: lead zirconium titanate (PbZrTiO) ₃ ) Strontium bismuth tantalate (SrBi) ₂ Ta ₂ O ₉ ) Hafnium oxide (HfO) ₂ ) And the like.

Illustratively, the conductive material of the first conductive layer includes a metallic material. For example, tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), ruthenium (Ru), iridium (Ir), cobalt (Co), aluminum (Al), copper (Cu), etc.

In order to realize the fabrication of the electrode structure and the channel on the semiconductor thin film, the semiconductor thin film 14 may use polysilicon; the conductive material of second conductive layer 122 comprises doped polysilicon and electrode structure 18 comprises doped polysilicon. Typically, the concentration of the dopant of the electrode structure 18 is less than the concentration of the dopant of the second conductive layer 122. Thus, since the conductive material of the second conductive layer 122 includes polysilicon having a high concentration of dopants, the electrode structure 18 can be generally formed by diffusing the dopants in the second conductive layer 122 into the semiconductor thin film 14. Wherein the type of the dopant is P type or N type. Typical dopants include: phosphorus (P), arsenic (As), boron (B), gallium (Ga), etc., and for example, as the dopant element phosphorus (P), arsenic (As), etc. having a valence of 5; p-type doping of polycrystalline silicon may use 3-valent dopant elements such as boron (B) and gallium (Ga). In one example, the semiconductor thin film has a thickness of 200-600A.

The isolation layer 123 is an electrically insulating material and may be an oxide such as silicon oxide SiO ₂ Wherein the isolation layer 123 mainly functions as an insulation of the first conductive layer 121 and the second conductive layer 123.

In addition, an embodiment of the present application provides a flow of a method for manufacturing a memory, which is shown in fig. 8 and includes the following steps:

101. a stacked structure 19 is produced.

The stacked structure 19 may be fabricated on a substrate 11, and the substrate 11 may be generally referred to as a silicon wafer (wafer), a die (die) or a silicon integrated circuit with a logic circuit function, or a semiconductor with a logic circuit function. The stacked structure 19 includes a sacrificial layer 124 and a second conductive layer 122 that are overlapped, wherein an isolation layer 123 is disposed between the sacrificial layer 124 and the second conductive layer 122. Specifically, as shown in fig. 9, a sacrificial layer/spacer layer/second conductive layer/spacer layer/sacrificial layer/spacer layer/second conductive layer/spacer layer is alternately deposited over the substrate 11. For example, the sacrificial layer 124 may be a nitride (nitride), such as GaN; the sacrificial layer 124, which may also be referred to as a nitride etch layer, is replaced with a conductive material (e.g., a metal material) to form the first conductive layer 121 in conjunction with the structure of the memory provided in fig. 5 above. The conductive material of the second conductive layer 122 includes heavily doped polysilicon, the type of dopant is P-type or N-type, and typical dopants include: phosphorus, arsenic, boron, gallium and the like, for example, 5-valent dopant elements of phosphorus, arsenic and the like can be used for N-type doping of polycrystalline silicon; the P-type doping of the polysilicon can be carried out by using 3-valent dopant elements such as boron, gallium and the like. The reason why the conductive material of the second conductive layer 122 includes heavily doped polysilicon is to provide for the out-diffusion (out-diffusion) formation of the electrode structures 18 (source and drain) on the sidewalls of the vertical channel 13 in a subsequent step. Further, the isolation layer 123 may be an electrically insulating material, typically, an oxide (silicon dioxide may be specifically used), as an insulator between the second conductive layer 122 and the first conductive layer 121. In fig. 7, the stacked structure formed by fabricating the sacrificial layer 124 with a nitride material (N), the isolation layer 123 with an oxide material (O), and the second conductive layer 122 with a heavily doped P-type polysilicon (P) is opodopo.

102. Vertical channels 13 are fabricated through the stacked structure 19 on the stacked structure 19.

In some embodiments, as shown in fig. 10, a Reactive Ion Etching (RIE) technique may be employed to etch vertical channels 13 in stacked structure 19.

103. A semiconductor film 14 is formed on the inner side wall of the vertical channel 13.

In an embodiment of the present application, a semiconductor thin film 14 is deposited on the inside sidewalls of the vertical channels 13, as shown in fig. 11. Wherein the semiconductor thin film 14 serves as a channel for each memory cell in the memory, in some embodiments, the semiconductor thin film 14 has a thickness between 200-600A. The semiconductor thin film 14 may be polysilicon.

Optionally, step 103 may be followed by forming a filler 15 in the via trench 14-1 surrounded by the semiconductor thin film 14. As shown in FIG. 12, an oxide is formed in the trench 14-1 of FIG. 11 as the filler 15, for example, the filler 15 may be silicon dioxide SiO ₂ 。

104. Electrode structure 18 is fabricated on semiconductor film 14, wherein electrode structure 18 is in contact with the conductive material comprised by second conductive layer 122.

As shown in fig. 13, step 104 includes fabricating a drain 18-2 and a source 18-1 of the memory cell on the semiconductor film 14. In some embodiments, the semiconductor thin film 14 comprises polysilicon; the conductive material of second conductive layer 122 comprises doped polysilicon and electrode structure 18 comprises doped polysilicon. The concentration of the dopant of electrode structure 18 is less than the concentration of the dopant of second conductive layer 122. The type of dopant is P-type or N-type. Specifically, the dopant in the second conductive layer 122 is diffused into the semiconductor film 14 through the high temperature annealing process to form the electrode structure 18. For example, the drain and source of the memory cell are fabricated using a high temperature annealing process (greater than 500 ℃, about 1000 ℃). At high temperature, the heavily doped polysilicon P-type or N-type ions will out-diffuse (out-diffusion) into the sidewall semiconductor film 14 to form a drain junction and a source junction. Since the semiconductor thin film 14 is thin like SOI (silicon-on-insulator, i.e., silicon on an insulating substrate), the junction created by the out-diffusion is not deep. The reaction speed of the external diffusion can be realized by controlling the temperature, and the consistency of the external diffusion can be effectively controlled by using a furnace tube (furnace).

105. The sacrificial layer 124 is removed, and the charge trapping film layer 16 is formed on the semiconductor thin film 14 exposed at the position of the sacrificial layer 124.

Referring to fig. 14, in step 105, the sacrificial layer 124 may be removed by an etching process to expose the semiconductor thin film 14. For example, when nitride is used for the sacrificial layer 124, an etchant having a higher selectivity to nitride is selected. The etchant has a weak etching property to the isolation layer 123 and the second conductive layer 122, so that all the nitride layer is etched away when the sacrificial layer 124 is replaced, and the other layers are remained. Referring to fig. 15, step 106 includes a process of preparing the charge trapping film layer 16. In some embodiments, the charge trapping film layer 16 is deposited on the semiconductor thin film 14 exposed at the location of the sacrificial layer 124 using a CVD or ALD process. The charge trapping layer 16 includes, but is not limited to, the ONO structure, FG structure, ferro structure described above.

106. A first conductive layer 121 is formed at the position of the sacrificial layer 124, wherein the first conductive layer 121 includes a conductive material in contact with the charge trapping film layer 16.

Referring to fig. 16, step 106 includes depositing a conductive material at the position of the sacrificial layer 124 by a CVD or ALD process (the metal material forms the first conductive layer 121. Depositing a metal at the position of the etched sacrificial layer 124, finally forming the stacked layer 12 of the first conductive layer 121 and the isolation layer 123 and the second conductive layer 122 as shown in fig. 5. In some embodiments, tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), ruthenium (Ru), iridium (Ir), cobalt (Co), aluminum (Al), copper (Cu), etc. are selected as the metal material of the first conductive layer 121.

In summary, the memory shown in fig. 5 is formed, wherein one stacked layer 12 in fig. 5 corresponds to a memory cell forming one memory. The channel length (channel length) of the memory cell is determined by the deposition thickness of the sacrificial layer 124. In some embodiments, reducing the thickness of the sacrificial layer 124 can increase the access speed of the memory cell; in some embodiments, increasing the thickness of the sacrificial layer 124 may reduce the memory cell leakage current. Therefore, the selection of an appropriate thickness of the sacrificial layer 124 can compromise the access speed and the magnitude of the leakage current.

The source and the drain (i.e. the bit line BL) are shared between two corresponding memory cells of each second conductive layer 122, the sacrificial layer 124 is replaced by the first conductive layer 121 to serve as the gate (connected to the word line WL) of the memory cell, and the isolation layer 123 ensures that the first conductive layer 121 and the second conductive layer 122 do not affect each other. Thus, each memory cell corresponds to one word line WL and one bit line BL, can finish independent read-write operation, and has a random access function.

The memory manufactured by the manufacturing method of the memory comprises a vertical channel penetrating through the stacked layers, a semiconductor film is formed on the inner side wall of the vertical channel, a charge capture film layer is arranged between the conductive material of the first conductive layer and the channel on the semiconductor film, and the electrode structures on two sides of the channel are respectively contacted with the conductive material of the second conductive layer, so that the storage unit of the memory can realize data storage; the first conductive layer of each memory cell is used as a gate and is arranged around the semiconductor film in the vertical channel in a surrounding mode, and the electrode structures are arranged on two sides of the channel in the semiconductor film respectively and can be directly manufactured through a surrounding gate nanowire manufacturing technology. In addition, the storage units are independent from each other, and the storage units at the top and the bottom of the vertical channel are not influenced with each other; the length of the channel in the memory cell is consistent with the thickness of the first conductive layer, and in the manufacturing process, the length of the channel is determined by the thickness of the sacrificial layer, so that a short memory cell channel can be made, and high performance of the device can be realized.

Based on this, the embodiment of the present application further provides an electronic device, which includes a circuit board and a memory connected to the circuit board, where the memory may be any one of the memories provided above. The circuit board may be a Printed Circuit Board (PCB), or the circuit board may also be a Flexible Printed Circuit (FPC), and the embodiment does not limit the circuit board. Optionally, the electronic device is different types of user devices or terminal devices, such as a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device; the electronic device may also be a network device such as a base station. Optionally, the electronic device further includes a package substrate, the package substrate is fixed on the PCB through solder balls, and the memory is fixed on the package substrate through solder balls. It should be noted that, for the related description of the memory in the electronic device, reference may be specifically made to the description of the memory in the foregoing embodiment, and details of the embodiment of the present application are not described herein again.

In another aspect of the application, there is also provided a non-transitory computer-readable storage medium for use with a computer having software for creating an integrated circuit, the computer-readable storage medium having stored thereon one or more computer-readable data structures having photomask data for manufacturing the memory provided by any of the illustrations provided above.

Finally, it should be noted that: the above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A memory, comprising:

the stacked layer comprises a first conductive layer and a second conductive layer which are arranged in an overlapped mode, and an isolation layer arranged between the adjacent first conductive layer and the second conductive layer;

the stacked layer comprises a vertical channel penetrating through the stacked layer, and a semiconductor film is formed on the inner side wall of the vertical channel;

the first conductive layer comprises a conductive material, a charge trapping film layer is formed between the conductive material of the first conductive layer and the semiconductor thin film, a channel penetrating through the semiconductor thin film is formed on the semiconductor thin film at a position opposite to the charge trapping film layer, the second conductive layer comprises a conductive material, and an electrode structure is formed at a position where the semiconductor thin film is in contact with the conductive material of the second conductive layer.
The memory of claim 1, wherein the charge trapping film layer comprises any one of: oxide-nitride-oxide ONO structures, floating gate FG structures and ferroelectric Ferro structures.
The memory of claim 1, wherein the conductive material of the first conductive layer comprises a metallic material.
The memory of claim 1, wherein the semiconductor thin film comprises polysilicon; the conductive material of the second conductive layer comprises polycrystalline silicon with a dopant, and the electrode structure comprises polycrystalline silicon with a dopant.
The memory of claim 4, wherein a concentration of the dopant of the electrode structure is less than a concentration of the dopant of the second conductive layer.
The memory according to claim 4 or 5, wherein the type of the dopant is P-type or N-type.
The memory according to claim 1, wherein the semiconductor thin film has a thickness of 200 to 600A.
The memory of claim 1, wherein the charge trapping film layer has a thickness of less than 50A.
The memory of claim 1, wherein the vertical channel is filled with a filler.
The memory of claim 9, wherein the filler is an oxide.
The memory of claim 1, wherein the isolation layer is an electrically insulating material.
The memory of any one of claims 1-11, wherein the first conductive layer is connected to a word line, the second conductive layer on one side of the first conductive layer is connected to a bit line, and the second conductive layer on the other side of the first conductive layer is connected to a source line.
A method for manufacturing a memory, comprising:

manufacturing a stacked structure, wherein the stacked structure comprises a sacrificial layer and a second conductive layer which are arranged in an overlapped mode, and an isolation layer is arranged between the sacrificial layer and the second conductive layer;

making a vertical channel on the stacked structure, wherein the vertical channel penetrates through the stacked structure;

manufacturing a semiconductor film on the inner side wall of the vertical channel;

manufacturing an electrode structure on the semiconductor film, wherein the electrode structure is in contact with the conductive material included in the second conductive layer;

removing the sacrificial layer, and manufacturing a charge trapping film layer on the semiconductor film exposed at the position of the sacrificial layer;

and manufacturing a first conductive layer at the position of the sacrificial layer, wherein the first conductive layer comprises a conductive material which is in contact with the charge trapping film layer.
The method of claim 13, wherein the semiconductor thin film comprises polysilicon; the conductive material of the second conductive layer comprises polycrystalline silicon with dopant, and the electrode structure comprises polycrystalline silicon with dopant;

fabricating an electrode structure on the semiconductor thin film, comprising:

and diffusing the dopant in the second conductive layer to the semiconductor film through a high-temperature annealing process to form the electrode structure.
The method of claim 13, wherein fabricating a charge trapping layer on the exposed semiconductor thin film at the position of the sacrificial layer comprises:

and depositing a charge trapping film layer on the semiconductor thin film exposed at the position of the sacrificial layer by a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) process.
The method of claim 13, further comprising, after forming a semiconductor film on the inner sidewall of the vertical channel:

and manufacturing a filler in the channel groove surrounded by the semiconductor film.
The method of any one of claims 13-16, wherein the sacrificial layer is silicon nitride.
An electronic device comprising a circuit board, and a non-volatile memory connected to the circuit board, the non-volatile memory being the memory of any one of claims 1-12.