CN116230575B - Semiconductor test structure and semiconductor parameter test method - Google Patents
Semiconductor test structure and semiconductor parameter test method Download PDFInfo
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- CN116230575B CN116230575B CN202310462222.4A CN202310462222A CN116230575B CN 116230575 B CN116230575 B CN 116230575B CN 202310462222 A CN202310462222 A CN 202310462222A CN 116230575 B CN116230575 B CN 116230575B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
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Abstract
The present disclosure relates to the field of semiconductor technology, and relates to a semiconductor test structure and a semiconductor parameter test method, wherein the test structure comprises an active layer, a gate structure, a plurality of lead groups and a conductive connection layer, wherein: the active layer comprises an active group, and the active group comprises a plurality of active areas which are distributed at intervals along a first direction; orthographic projection of the grid structure on the active group penetrates through the plurality of active areas; each lead group is respectively positioned on each active region and is in contact connection with the active region, and each lead group is positioned on the same side of the grid structure; the conductive connection layer is positioned on one side of the lead group far away from the active layer and comprises a plurality of first conductive connection parts which are distributed at intervals along a first direction, and the first conductive connection parts are connected between two adjacent lead groups so as to connect the active areas in series. The semiconductor test structure can improve the accuracy of the test result of the electrical parameters of the lead group.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor test structure and a semiconductor parameter test method.
Background
The semiconductor test structure is commonly used for testing various parameters of the semiconductor structure, so that data support is provided for optimization of a semiconductor manufacturing process, but the existing semiconductor test structure is not matched with an actual product, the internal structure of the actual product cannot be accurately reflected, and the accuracy of the parameters obtained by the test is low.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
In view of the above, the present disclosure provides a semiconductor test structure and a semiconductor parameter test method, which can improve the accuracy of the test result of the electrical parameters of the lead set.
According to one aspect of the present disclosure, there is provided a semiconductor test structure including a test region, in which:
an active layer including an active group including a plurality of active regions spaced apart along a first direction;
a gate structure, orthographic projection of the gate structure on the active set extending through a plurality of the active regions;
the lead groups are respectively positioned on the active areas and are in contact connection with the active areas, and the lead groups are positioned on the same side of the grid structure;
The conductive connection layer is positioned on one side of the lead group away from the active layer and comprises a plurality of first conductive connection parts which are distributed at intervals along the first direction, and the first conductive connection parts are connected between two adjacent lead groups so as to connect the active areas in series.
In one exemplary embodiment of the present disclosure, the lead group includes first and second leads spaced apart along the first direction, and a plurality of the first leads and a plurality of the second leads connected to a plurality of the active regions are alternately distributed along the first direction; in the first direction, one end of the first conductive connection part is connected with a second lead connected with the previous active region, and the other end of the first conductive connection part is connected with a first lead connected with the next active region.
In one exemplary embodiment of the present disclosure, the first and second leads are located at edge regions of the active region, respectively.
In an exemplary embodiment of the present disclosure, a partial region of the orthographic projection of the first and/or second leads on the active layer is located outside the active region.
In an exemplary embodiment of the disclosure, the test structure further includes a first redundant area, where the first redundant area is at least disposed on one side of the test area, the first redundant area and the test area are adjacently distributed, and the first redundant area is provided with:
a reference active layer including a plurality of reference active regions spaced apart along the first direction;
the reference lead groups are respectively positioned on the reference active areas and are in contact connection with the reference active areas;
and the reference conducting layer is positioned on one side of the reference lead group, which is far away from the reference active layer, and is in contact connection with the reference lead group.
In an exemplary embodiment of the present disclosure, the number of the active groups in the test area is plural, and the plural active groups are spaced apart along a second direction, the second direction intersecting the first direction; the number of the grid structures is multiple, and each active group is provided with one grid structure;
the conductive connection layer further comprises a plurality of second conductive connection parts which are distributed at intervals along the second direction, and the second conductive connection parts are connected between two adjacent active groups in the second direction so as to connect the active groups in series.
In an exemplary embodiment of the present disclosure, the test structure further includes a second redundant area, the second redundant area and the test area are adjacently distributed along the first direction, each of the gate structures extends into the second redundant area, and the second redundant area is provided with:
and the reference connection layer is electrically connected with each grid structure.
In one exemplary embodiment of the present disclosure, the width of the first conductive connection part in the second direction is equal to the width thereof in the first direction; the width of the second conductive connection part in the second direction is equal to the width of the second conductive connection part in the first direction.
In an exemplary embodiment of the present disclosure, the active set located at the top in the second direction is a starting active set, and active regions located at both ends of the starting active set are a first end active region and a second end active region, respectively; the active group at the bottommost part in the second direction is a termination active group, and active regions at two ends of the termination active group are a third end active region and a fourth end active region respectively; the lead group connected with the second end active region and the lead group connected with the third end active region are connected with the second conductive connection part; the test structure further comprises:
The first external connection part is positioned at one side of the lead group far away from the active layer and is electrically connected with the lead group connected with the first end active region;
and the second external connection part is positioned on one side of the lead group away from the active layer and is electrically connected with the lead group connected with the fourth end active region.
According to one aspect of the present disclosure, a semiconductor parameter testing method is provided, and the electrical parameters of the lead group are detected by using the semiconductor testing structure described in any one of the above.
In one exemplary embodiment of the present disclosure, the test method includes:
applying a first voltage to the first external connection and a second voltage to the second external connection;
detecting a current value flowing in the semiconductor test structure;
determining a total resistance of the semiconductor test structure according to the first voltage, the second voltage and the current value;
acquiring the resistance value of the active region and the resistance value of the conductive connecting layer;
and determining the resistance value of the lead group according to the total resistance of the semiconductor test structure, the resistance value of the active region and the resistance value of the conductive connecting layer.
In one exemplary embodiment of the present disclosure, when the first voltage is applied to the first external connection and the second voltage is applied to the second external connection, a voltage of 0V is applied to the gate structure.
In one exemplary embodiment of the present disclosure, determining a total resistance of the semiconductor test structure from the first voltage, the second voltage, and the current value includes:
calculating a voltage difference between the first voltage and the second voltage;
and determining the total resistance of the semiconductor test structure according to the ratio of the voltage difference to the current value.
According to the semiconductor test structure and the semiconductor parameter test method, the active areas can be connected in series through the lead groups and the conductive connecting layers, so that the total resistance of the active layers, the lead groups and the conductive connecting layers can be calculated integrally, and the resistance of the lead groups can be calculated accurately by subtracting the resistances of the active layers and the conductive connecting layers. In the process, the grid structure is arranged on the active group, so that the actual structural environment of the lead group can be truly simulated, the accuracy of the test result of the electrical parameters of the lead group can be improved, reliable data support can be provided for process optimization, the process optimization process can be accelerated, and the product performance can be improved. Meanwhile, as the lead wire groups are positioned on the same side of the grid structure, when two adjacent lead wire groups are connected together through the conductive connecting layer, the conductive connecting layer can be prevented from crossing the top of the grid structure, and the risk of short circuit between the conductive connecting layer and the grid structure can be reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a top view of a semiconductor test structure in an embodiment of the present disclosure.
FIG. 2 is a cross-sectional view of an embodiment of the present disclosure taken along the aa' direction in FIG. 1.
Fig. 3 is a schematic view of an active layer according to an embodiment of the disclosure.
Fig. 4 is a schematic diagram of a gate structure according to an embodiment of the disclosure.
Fig. 5 is a schematic diagram of a reference connection layer in an embodiment of the disclosure.
Fig. 6 is a schematic diagram of a lead set according to an embodiment of the disclosure.
FIG. 7 is a schematic diagram of a test area, a first redundant area, and a second redundant area according to an embodiment of the present disclosure.
Fig. 8 is a top view of a semiconductor test structure in an embodiment of the present disclosure.
Reference numerals illustrate:
1. an active layer; 11. an active group; 111. an active region; 110. a starting active set; 1101. a first end active region; 1102. a second end active region; 120. terminating the active set; 1201. a third end active region; 1202. a fourth end active region; 2. a lead group; 21. a first lead; 22. a second lead; 3. a conductive connection layer; 31. a first conductive connection; 32. a second conductive connection portion; 4. a gate structure; 5. a first external connection portion; 6. a second external connection portion; 100. a reference active layer; 101. a reference active region; 200. a reference lead set; 201. a first reference lead; 202. a second reference lead; 300. a reference conductive layer; 400. a reference connection layer; 500. a reference gate; 600. presetting a lead; x, a first direction; y, the second direction; A. a test zone; B. a first redundant area; C. and a second redundant area.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," "third," and "fourth," etc. are used merely as labels, and are not intended to limit the number of objects.
During the fabrication of semiconductor structures, it is often necessary to test the electrical parameters of various portions within the semiconductor structure by testing the structure to assess whether the process of forming the portions is viable. One or two relatively universal test structures are generally adopted to detect the electrical parameters of each part in the test process, but in actual products, the structural environments around each part (such as a lead) in the semiconductor structure are different, and the accuracy of the parameter measurement result is greatly influenced by adopting the universal test structures to detect the related parameters.
Based on this, the embodiment of the present disclosure provides a semiconductor test structure that can be used to test the resistance value of a lead. FIG. 1 illustrates a top view of a semiconductor test structure of the present disclosure, and FIG. 2 illustrates a schematic view taken along the aa' direction in FIG. 1; referring to fig. 1 and 2, the semiconductor test structure includes an active layer 1, a plurality of lead groups 2, a conductive connection layer 3 and a gate structure 4, wherein:
the active layer 1 includes an active group 11, and the active group 11 includes a plurality of active regions 111 spaced apart along a first direction;
a plurality of lead groups 2 respectively located on the active regions 111 and connected to the active regions 111 in a contact manner;
The conductive connection layer 3 is located at a side of the lead group 2 away from the active layer 1, and includes a plurality of first conductive connection portions 31 spaced apart along the first direction, and the first conductive connection portions 31 are connected between two adjacent lead groups 2 to connect the active regions 111 in series;
the orthographic projection of the gate structure 4 on the active set 11 penetrates through the plurality of active regions 111, and each of the lead sets 2 is located on the same side of the gate structure 4.
The semiconductor test structure of the present disclosure can connect each active region 111 in series with each conductive connection layer 3 through the lead set 2, so as to calculate the total resistance of the active layer 1, each lead set 2 and the conductive connection layer 3, and then can accurately calculate the resistance of the lead set 2 by subtracting the resistances of the active layer 1 and the conductive connection layer 3. In the process, the grid structure 4 is arranged on the active group 11, so that the actual structural environment of the lead group 2 can be truly simulated, the accuracy of the test result of the electrical parameters of the lead group 2 can be improved, reliable data support can be provided for process optimization, the process optimization process can be accelerated, and the product performance can be improved. Meanwhile, since the lead groups 2 are located on the same side of the gate structure 4, when two adjacent lead groups 2 are connected together through the conductive connection layer 3, the conductive connection layer 3 can be prevented from crossing the top of the gate structure 4, and the risk of short circuit between the conductive connection layer 3 and the gate structure 4 can be reduced.
The following is a detailed description of various portions and specific details of the semiconductor test structures of the present disclosure:
the active layer 1 may be formed in a substrate, which may have a flat plate structure, which may be rectangular, circular, oval, polygonal or irregular, and which may be made of a semiconductor material, for example, silicon, but is not limited to silicon or other semiconductor materials, and the shape and material of the substrate are not particularly limited.
For example, the substrate may be a silicon substrate having shallow trench isolation structures formed therein, which are capable of separating a plurality of active regions 111 on the substrate. In some embodiments of the present disclosure, a plurality of active regions 111 may constitute one active set 11, and each active region 111 in the active set 11 may be spaced apart along the first direction x. In other embodiments of the present disclosure, as shown in fig. 3, the plurality of active regions 111 may be formed into a plurality of active groups 11 (i.e., the number of active groups 11 may be plural), each active group 11 may include a plurality of active regions 111, the plurality of active regions 111 in each active group 11 may be spaced apart along a first direction x, the plurality of active groups 11 may be spaced apart along a second direction y, a spacing between the active regions 111 may be equal to a spacing between the active regions in an actual product, and a spacing between the active groups 11 may be equal to a spacing between the active groups in the actual product so as to truly simulate a distribution between the adjacent active regions 111. For example, in the first direction x, the pitch between the active regions 111 may be equal to the pitch of the active regions 111 in the peripheral region of the memory, and the pitch between the active groups 11 may be equal to the pitch of the active groups 11 in the peripheral region of the memory; alternatively, in the first direction x, the pitch between the active regions 111 may be equal to the pitch of the active regions 111 in the array region of the memory, and the pitch between the active groups 11 may be equal to the pitch of the active groups 11 in the array region of the memory.
The first direction x may be any direction parallel to the substrate, and the second direction y may intersect the first direction x, e.g., the second direction y and the first direction x may be perpendicular to each other. It should be noted that, the vertical may be an absolute vertical or a substantially vertical, and deviations may be unavoidable in the manufacturing process, and in this disclosure, the angle between the first direction x and the second direction y may be deviated to some extent due to the deviation of the angles caused by the limitation of the manufacturing process, so long as the angle deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y may be considered to be vertical. For example, the predetermined range may be 10 °, namely: an angle between the first direction x and the second direction y is considered to be perpendicular when the angle is within a range of 80 ° or more and 100 ° or less.
In some embodiments of the present disclosure, the active set 11 located at the top in the second direction y may be used as the initial active set 110, and the active regions 111 located at the two ends in the first direction x in the initial active set 110 are the first end active region 1101 and the second end active region 1102, respectively; the active set 11 located at the bottommost portion in the second direction y may be referred to as a termination active set 120, and the active regions 111 located at both ends in the first direction x in the termination active set 120 are a third end active region 1201 and a fourth end active region 1202, respectively.
As shown in fig. 4, the gate structure 4 may be located on a side of the active layer 1 away from the substrate, the gate structure 4 may be stripe-shaped and may extend along the first direction x, for example, the gate structure 4 may be located on the active layer 1, and its orthographic projection on the active set 11 may penetrate through the plurality of active regions 111. For example, the orthographic projection of the gate structure 4 on the substrate may extend through all active regions 111 within the active set 11, and the gate structure 4 may be a word line structure, for example.
As shown in fig. 5, when the number of active groups 11 is plural, the number of gate structures 4 may be plural, and the plural gate structures 4 may be distributed at intervals along the second direction y. Each active set 11 is provided with a gate structure 4, that is, a plurality of gate structures 4 may be disposed on each active set 11 in a one-to-one correspondence.
With continued reference to fig. 2 and 4, the number of the lead groups 2 may be plural, for example, the number of the lead groups 2 may be the same as the number of the active regions 111, one lead group 2 may be formed on each active region 111, and the lead groups 2 may be in contact connection with the surface of the active region 111.
In one exemplary embodiment of the present disclosure, as shown in fig. 2, the lead group 2 may include first and second leads 21 and 22 spaced apart in the first direction x, and one ends of the first and second leads 21 and 22 may each be in contact with the active region 111 and the other ends thereof may extend toward a side remote from the active region 111. In an actual product, the length of the active area 111 is generally smaller, the space capable of laying out the leads is also relatively smaller, in order to ensure that two leads can be laid out on one active area 111 and further reduce the contact resistance of the leads, the leads are generally laid out in the edge area of the active area 111, in this embodiment, in order to truly reflect the layout position of the lead group 2, the first leads 21 and the second leads 22 can be respectively connected with two ends distributed along the first direction x in the active area 111, that is, the first leads 21 and the second leads 22 can be both located in the edge area of the active area 111, and further truly simulate the layout position of the leads, which is helpful for improving the accuracy of the test result of the electrical parameters of the lead group 2 and providing reliable data support for process parameter optimization.
In some embodiments of the present disclosure, as shown in fig. 4, a plurality of first wires 21 and a plurality of second wires 22 connected to the plurality of active regions 111, respectively, may be alternately distributed along the first direction x. For example, in the first direction x, at least one side of each first lead 21 is distributed with the second leads 22, and at least one side of each second lead 22 is distributed with the first lead 21.
In some embodiments of the present disclosure, as shown in fig. 6, a partial area of the orthographic projection of the first lead 21 on the active layer 1 may be located outside the active area 111, that is, a partial area of the bottom of the first lead 21 may be in contact with the active area 111, and another partial area may be located outside the active area 111, so as to simulate a situation that the first lead 21 deviates from the outside of the active area 111 due to the smaller size of the active area 111 in a partial device, and may actually simulate a connection state between the first lead 21 and the active area 111.
In some embodiments of the present disclosure, as shown in fig. 6, a partial area of the orthographic projection of the second wire 22 on the active layer 1 may be located outside the active area 111, that is, a partial area of the bottom of the second wire 22 may be in contact with the active area 111, and another partial area may be located outside the active area 111, so as to simulate a situation that the second wire 22 deviates from the outside due to the smaller size of the active area 111 in a partial device, and may actually simulate a connection state between the second wire 22 and the active area 111.
In some embodiments of the present disclosure, a partial area of the orthographic projection of either one of the first wire 21 and the second wire 22 on the active layer 1 may be located outside the active area 111, or, a partial area of the orthographic projection of both the first wire 21 and the second wire 22 on the active layer 1 may be located outside the active area 111, so as to further simulate the situation of the active area and its conductive contact in a higher-integration chip.
The materials of the first and second leads 21 and 22 may be the same or different, and are not particularly limited herein. For example, the materials of the first and second leads 21 and 22 may be metal materials, for example, the materials of the first and second leads 21 and 22 may be copper, aluminum, tungsten, or the like.
In one exemplary embodiment of the present disclosure, as shown in fig. 4 and 7, all of the lead groups 2 disposed corresponding to the same active group 11 may be located on the same side of the gate structure 4 corresponding to the active group 11, so as to facilitate subsequent series connection of the active regions 111 within the active group 11 together through the respective lead groups 2.
It should be noted that, in the process of manufacturing the semiconductor test structure of the present disclosure, the lead set 2 may be formed after the gate structure 4 is formed, so that an environmental state in the process of forming the lead set 2 may be truly simulated, which is helpful for keeping the profile of the lead set 2 consistent with the profile of the lead in an actual product, more truly reflecting the structural profile of the lead set 2, and is helpful for improving the accuracy of the test structure.
As shown in fig. 2, 6 and 8, the conductive connection layer 3 may be located at a side of the lead groups 2 away from the active layer 1, and may be connected to each of the lead groups 2. The conductive connection layer 3 may be located in a different layer than the gate structure 4, e.g. it may be located on a side of the gate structure 4 remote from the substrate. The conductive connection layer 3 may be made of a conductive material, for example, a conductive metal, for example, copper, aluminum, tungsten, or the like.
In some embodiments of the present disclosure, referring to fig. 1 and 2, the conductive connection layer 3 may include a plurality of first conductive connection portions 31, and each of the first conductive connection portions 31 may be spaced apart along the first direction x. Each first conductive connection portion 31 may be connected between two adjacent lead groups 2, respectively, and each active region 111 may be connected in series through each first conductive connection portion 31 and each lead group 2.
For example, in the first direction x, one end of the first conductive connection portion 31 is connected to the second lead 22 connected to the previous active region 111, and the other end of the first conductive connection portion 31 is connected to the first lead 21 connected to the next active region 111, among the adjacent two active regions 111. For example, when the active set 11 includes 4 active regions 111, the number of the first conductive connection portions 31 may be 3, and the 3 first conductive connection portions 31 may be respectively connected between two adjacent active regions 111; specifically, the four active regions 111 may be defined as a first active region, a second active region, a third active region, and a fourth active region, respectively, one end of the first conductive connection portion 31 may be in contact connection with the second lead 22 connected to the first active region, and the other end of the first conductive connection portion 31 may be in contact connection with the first lead 21 connected to the second active region; one end of the second first conductive connection part 31 may be in contact with the second lead 22 connected to the second active region, and the other end of the second first conductive connection part 31 may be in contact with the first lead 21 connected to the third active region; one end of the third first conductive connection portion 31 may be in contact with the second lead 22 connected to the third active region, and the other end of the third first conductive connection portion 31 may be in contact with the first lead 21 connected to the fourth active region.
In one exemplary embodiment of the present disclosure, the width of the first conductive connection part 31 in the second direction y is equal to the width thereof in the first direction x so as to facilitate the subsequent calculation of the resistance of each first conductive connection part 31. For example, each of the first conductive connection portions 31 may have a rectangular shape in a direction parallel to the substrate, and the length and width of the rectangular shape may be equal, i.e., each of the first conductive connection portions 31 may have a square shape.
In an exemplary embodiment of the present disclosure, as shown in fig. 8, the conductive connection layer 3 may further include a second conductive connection portion 32, and in the second direction y, the second conductive connection portion 32 may be connected between two adjacent active groups 11, and the two adjacent active groups 11 may be connected in series through the second conductive connection portion 32, contributing to an increase in the number of active regions 111 connected in series.
In one exemplary embodiment of the present disclosure, the width of the second conductive connection 32 in the second direction y is equal to the width thereof in the first direction x so as to facilitate the subsequent calculation of the resistance of each second conductive connection 32. For example, each of the second conductive connection portions 32 may have a rectangular shape in a direction parallel to the substrate, and the length and width of the rectangular shape may be equal, i.e., each of the second conductive connection portions 32 may have a square shape.
When the number of the active set 11 is two, the number of the second conductive connection parts 32 may be one. For example, when the two active groups 11 each include 4 active regions 111, and the 4 active regions 111 are the first active region, the second active region, the third active region, and the fourth active region, one end of the second conductive connection portion 32 may be in contact with the second lead 22 connected to the fourth active region in one active group 11, and the other end thereof may be in contact with the second lead 22 connected to the fourth active region in the other active group 11, so that the two active groups 11 are connected in series through the second conductive connection portion 32.
With continued reference to fig. 8, when the number of the active groups 11 is greater than 2, the number of the second conductive connection portions 32 may be plural, the plurality of second conductive connection portions 32 may be distributed at intervals along the second direction y, the number of the second conductive connection portions 32 may be less than 1 than the number of the active groups 11, and each second conductive connection portion 32 may be respectively connected between two adjacent active groups 11, so as to connect the plurality of active groups 11 in series.
In some embodiments of the present disclosure, the active set 11 may include a first end and a second end that are disposed side by side along the first direction x, the first ends of the plurality of active sets 11 may be aligned, and at the same time, the second ends of the plurality of active sets 11 may be aligned with each other, the second conductive connection portion 32 may be connected between the first ends or the second ends of the adjacent two active sets 11, and the adjacent two second conductive connection portions 32 may be staggered, for example, when the number of active sets 11 is plural, each active set 11 may be sequentially named as a first active set, a second active set, a third active set, a fourth active set, … …, an n-1 active set, and at the same time, each second conductive connection portion 32 may be sequentially named as a 1 st second conductive connection portion 32, a 2 nd second conductive connection portion 32, a 3 rd second conductive connection portion 32, … …, and an n-1 st second conductive connection portion 32, wherein the 1 st second conductive connection portion 32, the 3 rd second conductive connection portion 32, and the 5 th second conductive connection portion 32 … … are all connected between the lead groups 2 at the second ends of the adjacent two active groups 11, and the 2 nd second conductive connection portion 32, the 4 th second conductive connection portion 32, and the 6 th second conductive connection portion 32 … … are all connected between the lead groups 2 at the first ends of the adjacent two active groups 11, for example, the 1 st second conductive connection portion 32 is connectable between the second lead 22 connected to the second ends of the first active groups and the second lead 22 connected to the second ends of the second active groups; the 2 nd second conductive connection part 32 may be connected between the first lead 21 connected to the first end of the second active set and the first lead 21 connected to the first end of the third active set; the 3 rd second conductive connection 32 may be connected between the second lead 22 connected to the second end of the third active set and the second lead 22 connected to the second end of the fourth active set; when n is an even number, the n-1 th second conductive connection part 32 may be connected between the second lead 22 connected to the second terminal of the n-1 th active set and the second lead 22 connected to the second terminal of the n-1 th active set; when n is an odd number, the n-1 th second conductive connection part 32 may be connected between the first lead 21 connected to the first end of the n-1 th active set and the first lead 21 connected to the first end of the n-1 th active set.
In an exemplary embodiment of the present disclosure, please continue to refer to fig. 7, the first active set may be used as the initial active set 110, the active region 111 at the end of the first end in the initial active set 110 is the first end active region 1101, and the active region 111 at the end of the second end is the second end active region 1102. The nth active set may be used as the termination active set 120, and when n is even, the active region 111 at the end of the first end of the termination active set 120 is the fourth end active region 1202, and the active region 111 at the end of the second end is the third end active region 1201. When n is an odd number, the active region 111 at the end of the first end in the termination active set 120 is a third end active region 1201, and the active region 111 at the end of the second end is a fourth end active region 1202. The lead group 2 connected to the second end active region 1102 and the lead group 2 connected to the third end active region 1201 are connected to different second conductive connection portions 32, respectively.
In an exemplary embodiment of the present disclosure, as shown in fig. 7 and 8, the test structure of the present disclosure may further include a first redundancy area B, which may be provided at least at one side of the test area a. For example, in the second direction y, the first redundant area B may be distributed adjacent to the test area a. The first redundancy area B may have a reference active layer 100, a reference lead set 200, and a reference conductive layer 300 disposed therein, wherein:
The reference active layer 100 may include a plurality of reference active regions 101 spaced apart along the first direction x, and the material, shape and size of the reference active regions 101 are the same as the material, shape and size of the active regions 111 in the test region a, respectively. The pitch between adjacent two reference active regions 101 is equal to the pitch between the active regions 111 of the test region a spaced apart in the first direction x. The spacing between the reference active region 101 and the active region 111 closest to the reference active region 101 within the test region a is equal to the spacing between the active regions 111 of the test region a spaced apart along the second direction y.
The number of the reference lead groups 200 may be plural, and the plural reference lead groups 200 may be located on each reference active area 101 (i.e., one reference lead group 200 may be disposed on each reference active area 101 in a one-to-one correspondence), and may be in contact connection with each reference active area 101. The structure of the reference lead set 200 is the same as that of the lead set 2 in the test area a, for example, the reference lead set 200 may include a first reference lead 201 and a second reference lead 202 that are spaced along the first direction x, and specific details of the first reference lead 201 and the second reference lead 202 may refer to the first lead 21 and the second lead 22 in the test area a, and thus, will not be described herein.
The reference conductive layer 300 may be located at a side of the reference lead group 200 remote from the reference active layer 100 and in contact connection with the reference lead group 200. In some embodiments of the present disclosure, the reference conductive layer 300 may include a plurality of reference connection portions spaced apart from each other, and each reference connection portion may be connected between each of the adjacent reference lead groups 200. In other embodiments of the present disclosure, the reference conductive layer 300 may have a stripe shape and may extend along the first direction x, and the orthographic projection of the reference conductive layer 300 on the reference active layer 100 may penetrate the plurality of reference active regions 101. The material of the reference conductive layer 300 may be the same as that of the conductive connection layer 3 in the test area a, for example, copper, aluminum, tungsten, or the like.
In some embodiments of the present disclosure, a reference gate 500 may be further disposed in the first redundant region B, and the reference gate 500 may be located on the reference active layer 100, and its orthographic projection on the reference active layer 100 may extend through the plurality of reference active regions 101. The specific details of the reference gate 500 are similar to the gate structure 4 and will not be repeated here.
In some embodiments of the present disclosure, the first redundancy area B may include a first sub-area and a second sub-area, and in the second direction y, the first sub-area, the test area a, and the second sub-area may be sequentially adjacently distributed, and reference active layer 100, a plurality of reference lead groups 200, reference conductive layer 300, and reference gate 500 are disposed in the first sub-area and the second sub-area. The structural environment of each lead group 2 in the test area A can be simulated through the arrangement of the first redundant area B, so that the peripheral structural environment of each lead group 2 in an actual product can be accurately restored, the interference of the peripheral structural environment is taken into consideration, and the accuracy of the test structure is improved.
In an exemplary embodiment of the present disclosure, referring to fig. 7 and 8, the semiconductor test structure of the present disclosure may further include a second redundancy region C, which may be adjacent to the test region a in the first direction x, and each gate structure 4 may extend from the test region a into the second redundancy region C. In some embodiments of the present disclosure, a reference connection layer 400 may be disposed within the second redundancy region C, and the reference connection layer 400 may be electrically connected to each gate structure 4. For example, the surface of each gate structure 4 extending to the inner portion of the second redundant area C may be provided with a preset lead 600, and the reference connection layer 400 may be disposed on a side of the preset lead 600 away from the gate structure 4 and in contact connection with an end of the preset lead 600 away from the gate structure 4.
In an exemplary embodiment of the present disclosure, the semiconductor test structure of the present disclosure may further include a first external connection portion 5 and a second external connection portion 6, and as shown in fig. 2 and 6, the first external connection portion 5 and the second external connection portion 6 may be located at a side of the lead set 2 away from the active layer 1. The width of the first external connection portion 5 in the second direction y is equal to the width thereof in the first direction x, so that the resistance of each first external connection portion 5 is calculated later. For example, each of the first external connection portions 5 may have a rectangular shape in a direction parallel to the substrate, and the length and width of the rectangular shape may be equal, i.e., each of the first external connection portions 5 may have a square shape. The material of the first external connection portion 5 may be a conductive material, for example, copper or aluminum. The structure and other details of the second external portion 6 are substantially identical to those of the first external portion 5, and the specific details of the second external portion 6 may refer to the first external portion 5, so that a detailed description thereof will be omitted herein. In some embodiments of the present disclosure, the shape, material, length, and width of the first external connection portion 5, the second external connection portion 6, the first conductive connection portion 31, and the second conductive connection portion 32 are all equal, i.e., the resistances of the first external connection portion 5, the second external connection portion 6, the first conductive connection portion 31, and the second conductive connection portion 32 are all equal, respectively.
As shown in fig. 1, 2 and 6, when the active set 11 is one, the first external connection portion 5 and the second external connection portion 6 may be electrically connected to the lead set 2 connected to the active regions 111 at both ends of the active set 11, respectively, so that a test voltage is applied to the active set 11 through the first external connection portion 5 and the second external connection portion 6 during a test. For example, the active set 11 includes a first active region, a second active region, a third active region and a fourth active region, the first external connection portion 5 may be in contact connection with a first lead 21 of the first active region, and the second external connection portion 6 may be in contact connection with a second lead 22 of the fourth active region.
In an exemplary embodiment of the present disclosure, as shown in fig. 8, when the number of active groups 11 is plural, the first external connection part 5 may be connected to the lead group 2 connected to the first end active region 1101 of the starting active group 110, for example, it may be electrically connected to the first lead 21 connected to the first end active region 1101; the second external connection 6 may be connected to the lead group 2 terminating the connection of the fourth end active region 1202 of the active group 120, for example, it may be electrically connected to the first lead 21 connected to the fourth end active region 1202. A first voltage may be applied to the first external connection 5 and a second voltage may be applied to the second external connection 6, thereby forming a current in the semiconductor test structure so as to calculate a total resistance of the semiconductor test structure through the first voltage, the second voltage, and the current.
The embodiment of the present disclosure also provides a semiconductor parameter testing method, which can detect the electrical parameter of the lead set 2 by using the semiconductor testing structure in any of the above embodiments. The electrical parameter may be contact resistance, etc.
In one exemplary embodiment of the present disclosure, the test method of the present disclosure may include step S110 to step S150, wherein:
step S110, applying a first voltage to the first external connection portion and applying a second voltage to the second external connection portion.
The first voltage may be a high-level voltage, and the second voltage may be a low-level voltage, and after the first voltage is applied to the first external connection portion 5 and the second voltage is applied to the second external connection portion 6, a voltage difference may be generated between the first external connection portion 5 and the second external connection portion 6, thereby forming a circulation loop. In some embodiments of the present disclosure, when the first voltage is applied to the first external connection portion 5 and the second voltage is applied to the second external connection portion 6, a voltage of 0V may be applied to the gate structure 4 at the same time, so that an inversion layer resistance may be prevented from being formed under the gate structure 4, thereby interfering with the test result, and helping to further improve the accuracy of the test result.
Step S120, detecting a value of a current flowing in the semiconductor test structure.
After the voltages are applied to the first external connection portion 5 and the second external connection portion 6, a voltage difference can be generated between the first external connection portion 5 and the second external connection portion 6, a current can be generated in the semiconductor test structure under the action of the voltage difference, and a current value of the current flowing in the semiconductor test structure can be detected, so that the resistance value of the lead group 2 can be calculated later. For example, the current value may be detected by a multimeter or a ammeter, but the current value may be formed by other means, and the method for detecting the current value is not particularly limited.
Step S130, determining the total resistance of the semiconductor test structure according to the first voltage, the second voltage and the current value.
For example, a voltage difference between the first voltage and the second voltage may be calculated, and according to ohm's law, a total resistance of the semiconductor test structure may be obtained according to a ratio of the voltage difference to a current value of a current flowing in the semiconductor test structure.
And step S140, obtaining the resistance value of the active region and the resistance value of the conductive connecting layer.
In some implementations of the present disclosureFor example, the resistance value of each active region 111 and the resistance values of each first conductive connection portion 31, each second conductive connection portion 32, the first external connection portion 5, and the second external connection portion 6 may be detected by other test structures. In some embodiments of the present disclosure, the resistance value of each active region 111 may be detected by a test device (i.e. R s_AA ) In this embodiment, the effective resistance of the portion of each active region 111 participating in the series connection can be calculated, thereby reducing the error of the calculation result. For example, the spacing between the first and second leads 21, 22 on the active region 111 may be detected (i.eW AA ) And the edge of the active region 111 between the first and second wirings 21 and 22 is spaced apart from the gate structure 4 by the width (i.e.L AA ). Can be based on the distance between the first lead 21 and the second lead 22W AA ) And the edge of the active region 111 between the first and second wirings 21 and 22 is spaced apart from the gate structure 4 by a widthL AA ) The effective resistance of the active region 111 is calculated.
In one exemplary embodiment of the present disclosure, the determination may be made by the design layout of the semiconductor test structure of the present disclosureW AA And/orL AA Can also be determined by slicing or other meansW AA And/orL AA Is not aligned hereW AA AndL AA the determination mode of (2) is particularly limited.
When the shapes, materials, lengths and widths of the first external connection portion 5, the second external connection portion 6, the first conductive connection portion 31 and the second conductive connection portion 32 are equal, respectively, the resistance values of the first external connection portion 5, the second external connection portion 6, the first conductive connection portion 31 and the second conductive connection portion 32 can be detected by using another test component, and at this time, the shapes, materials, lengths and widths of the first external connection portion 5, the second external connection portion 6, the first conductive connection portion 31 and the second conductive connection portion 32 are equal, respectively, so that the detected resistance values of the respective portions are equal, and the first external connection portion 5, the second external connection portion 6, the first conductive connection portion 31 and the second conductive connection portion 32 can be electrically connected The resistance values are allR s_M0 。
And step S150, determining the resistance value of the lead group according to the total resistance of the semiconductor test structure, the resistance value of the active region and the resistance value of the conductive connecting layer.
In the embodiment of the present disclosure, the number of the lead groups 2 may be defined as n, the number of the corresponding active regions 111 is also n, the total number of the first conductive connection portions 31, the second conductive connection portions 32, the first external connection portions 5, and the second external connection portions 6 is (n+1), and the resistance value of the lead groups 2 may be calculated according to the following formula (formula I):
(formula I)
Wherein, the liquid crystal display device comprises a liquid crystal display device,nfor the number of lead groups 2,R c for the resistance value of the lead set 2,V f as a voltage difference between the first voltage and the second voltage,I f as the value of the current to be measured,W AA is the spacing between the first 21 and second 22 leads on the same active region 111,L AA for the width of the edge of the active region 111 between the first and second wirings 21 and 22 from the gate structure 4,R s_AA is the resistance value of the active region 111,R s_M0 the resistance value of the first external connection portion 5, the second external connection portion 6, the first conductive connection portion 31, or the second conductive connection portion 32.
It should be noted that, when the lead group 2 includes two leads (i.e., the lead group 2 includes the first lead 21 and the second lead 22), the resistance of each lead may be R c /2。
It should be noted that although the various steps of the semiconductor parameter testing method of the present disclosure are depicted in a particular order in the figures, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (12)
1. A semiconductor test structure comprising a test region, wherein:
an active layer including an active group including a plurality of active regions spaced apart along a first direction;
A gate structure, orthographic projection of the gate structure on the active set extending through a plurality of the active regions;
the lead groups are respectively positioned on the active areas and are in contact connection with the active areas, and the lead groups are positioned on the same side of the grid structure;
the conductive connection layer is positioned on one side of the lead group away from the active layer and comprises a plurality of first conductive connection parts which are distributed at intervals along the first direction, and the first conductive connection parts are connected between two adjacent lead groups so as to connect the active areas in series;
the test structure further comprises a first redundant area, wherein the first redundant area is at least arranged on one side of the test area, the first redundant area is distributed adjacently to the test area, and the first redundant area is internally provided with:
a reference active layer including a plurality of reference active regions spaced apart along the first direction;
the reference lead groups are respectively positioned on the reference active areas and are in contact connection with the reference active areas;
and the reference conducting layer is positioned on one side of the reference lead group, which is far away from the reference active layer, and is in contact connection with the reference lead group.
2. The test structure of claim 1, wherein the set of leads includes first and second leads spaced apart along the first direction, and a plurality of the first leads and a plurality of the second leads connected to a plurality of the active regions are alternately distributed along the first direction; in the first direction, one end of the first conductive connection part is connected with a second lead connected with the previous active region, and the other end of the first conductive connection part is connected with a first lead connected with the next active region.
3. The test structure of claim 2, wherein the first and second leads are located at edge regions of the active region, respectively.
4. The test structure of claim 2, wherein a partial region of the orthographic projection of the first and/or second leads onto the active layer is located outside the active region.
5. The test structure of any one of claims 1-4, wherein the number of active groups in the test zone is a plurality, the plurality of active groups being spaced apart along a second direction, the second direction intersecting the first direction; the number of the grid structures is multiple, and each active group is provided with one grid structure;
The conductive connection layer further comprises a plurality of second conductive connection parts which are distributed at intervals along the second direction, and the second conductive connection parts are connected between two adjacent active groups in the second direction so as to connect the active groups in series.
6. The test structure of claim 5, further comprising a second redundant region, the second redundant region and the test region being adjacently disposed along the first direction, each of the gate structures extending into the second redundant region from the test region, the second redundant region having disposed therein:
and the reference connection layer is electrically connected with each grid structure.
7. The test structure of claim 6, wherein the first conductive connection has a width in the second direction that is equal to a width of the first conductive connection in the first direction; the width of the second conductive connection part in the second direction is equal to the width of the second conductive connection part in the first direction.
8. The test structure of claim 7, wherein the active set at the top in the second direction is a starting active set, and the active regions at the two ends in the starting active set are a first end active region and a second end active region, respectively; the active group at the bottommost part in the second direction is a termination active group, and active regions at two ends of the termination active group are a third end active region and a fourth end active region respectively; the lead group connected with the second end active region and the lead group connected with the third end active region are connected with the second conductive connection part; the test structure further comprises:
The first external connection part is positioned at one side of the lead group far away from the active layer and is electrically connected with the lead group connected with the first end active region;
and the second external connection part is positioned on one side of the lead group away from the active layer and is electrically connected with the lead group connected with the fourth end active region.
9. A semiconductor parameter testing method, wherein the electrical parameters of the lead set are detected using the semiconductor test structure of claim 8.
10. The test method according to claim 9, wherein the test method comprises:
applying a first voltage to the first external connection and a second voltage to the second external connection;
detecting a current value flowing in the semiconductor test structure;
determining a total resistance of the semiconductor test structure according to the first voltage, the second voltage and the current value;
acquiring the resistance value of the active region and the resistance value of the conductive connecting layer;
and determining the resistance value of the lead group according to the total resistance of the semiconductor test structure, the resistance value of the active region and the resistance value of the conductive connecting layer.
11. The method of testing of claim 10, wherein a voltage of 0V is applied to the gate structure when the first voltage is applied to the first external connection and a second voltage is applied to the second external connection.
12. The method of testing of claim 10, wherein determining the total resistance of the semiconductor test structure from the first voltage, the second voltage, and the current value comprises:
calculating a voltage difference between the first voltage and the second voltage;
and determining the total resistance of the semiconductor test structure according to the ratio of the voltage difference to the current value.
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