CN113192931A - Residual polycrystalline silicon monitoring structure, structure layout, method and semiconductor device - Google Patents
Residual polycrystalline silicon monitoring structure, structure layout, method and semiconductor device Download PDFInfo
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- CN113192931A CN113192931A CN202110466484.9A CN202110466484A CN113192931A CN 113192931 A CN113192931 A CN 113192931A CN 202110466484 A CN202110466484 A CN 202110466484A CN 113192931 A CN113192931 A CN 113192931A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 213
- 238000012544 monitoring process Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 152
- 239000002184 metal Substances 0.000 claims abstract description 114
- 238000002955 isolation Methods 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 description 3
- 238000012935 Averaging Methods 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
The invention provides a residual polycrystalline silicon monitoring structure, a structure layout, a method and a semiconductor device. This can greatly shorten the distance between the edge of the metal strip and the remaining polysilicon. When voltage is applied to the strip-shaped metal strip and the polysilicon strip, the side wall between the metal strip and the polysilicon strip is more easily broken down, and the current between the metal strip and the polysilicon strip is more easily detected. The detection rate of the residual polysilicon in the side wall on the side edge of the polysilicon strip is improved, and the monitoring effect of the residual polysilicon monitoring structure is further improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a residual polycrystalline silicon monitoring structure, a residual polycrystalline silicon monitoring layout, a residual polycrystalline silicon monitoring method and a semiconductor device.
Background
With the improvement of living standard of people, electronic products are more and more widely applied, and various semiconductor products are generally used in the electronic products. With the development of technology and the increase of demand, the performance requirements of semiconductor products are higher and higher.
For example, in the case of a flash memory having memory cells, the performance of the flash memory is greatly reduced due to a failure of the flash memory, and one reason for an early failure of the flash memory is that a height difference exists between a shallow trench isolation structure and an active region on a substrate, which causes polysilicon residue when a word line is formed by etching, and further causes a short circuit between the word line and the active region when the word line is applied with a high voltage, so that the flash memory fails. Therefore, monitoring of the residual polysilicon is an important monitoring item in the flash memory manufacturing process. The existing residual polysilicon monitoring structure usually has poor monitoring effect when monitoring residual polysilicon.
Disclosure of Invention
The invention aims to provide a residual polycrystalline silicon monitoring structure, a structure layout, a method and a semiconductor device, and aims to solve the problem that the existing residual polycrystalline silicon monitoring structure is poor in monitoring effect when residual polycrystalline silicon is monitored.
In order to solve the above technical problem, the present invention provides a structure for monitoring residual polysilicon, comprising: a substrate with an active region and a shallow trench isolation structure, a polysilicon strip, a strip-shaped metal strip, a side wall and a dielectric layer formed on the substrate,
wherein the active regions comprise at least one first active region and at least one second active region, the first active region and the second active region are vertically crossed with each other, and the shallow trench isolation structures are alternately arranged with the first active region and the second active region;
the strip-shaped metal strip is positioned on the second active region and spans the first active region, the polycrystalline silicon strips and the strip-shaped metal strip are arranged in parallel at intervals and span the first active region and the shallow trench isolation structures alternately arranged with the first active region, the side walls are formed on the side edges of the polycrystalline silicon strips and positioned between the polycrystalline silicon strips and the strip-shaped metal strip, and the dielectric layer is formed on the substrate and at least positioned between the active region and the polycrystalline silicon strips; and the number of the first and second groups,
the metal strip and the polycrystalline silicon strip are used for being applied with voltage, and whether residual polycrystalline silicon exists in the side wall on the side edge of the polycrystalline silicon strip after the polycrystalline silicon strip is formed by etching is judged according to the current between the metal strip and the polycrystalline silicon strip.
Optionally, each of the strip-shaped metal strips spans all of the first active regions.
Optionally, at least two polysilicon strips are arranged in parallel with the second active region at intervals, one strip-shaped metal strip is arranged between two adjacent polysilicon strips, and the strip-shaped metal strip is arranged in the middle of two adjacent polysilicon strips; or two strip-shaped metal strips are arranged between two adjacent polycrystalline silicon strips, and the distance between the two adjacent polycrystalline silicon strips is trisected by the two strip-shaped metal strips.
Optionally, the width of the strip-shaped metal strip is 0.15 um-0.2 um, and the strip-shaped metal strip and the distance between the polycrystalline silicon strips is 0.05 um-0.1 um.
In order to solve the problems, the invention also provides a residual polysilicon monitoring structure layout, wherein the residual polysilicon monitoring structure layout is used for preparing the residual polysilicon monitoring structure as described in any one of the above items, and the residual polysilicon monitoring structure layout comprises a superposed active region layout, a shallow trench isolation structure layout, a polysilicon layout, a metal strip layout, a side wall layout and a dielectric layer layout; wherein the content of the first and second substances,
the active area layout comprises at least one first active area graph and at least one second active area graph, and the first active area graph and the second active area graph are mutually and vertically crossed;
the shallow trench isolation structure layout comprises a shallow trench isolation structure graph, and the shallow trench isolation graph, the first active region graph and the second active region graph are alternately arranged;
the strip metal strip layout comprises a strip metal strip graph, and the strip metal strip graph is positioned on the second active region graph and stretches across the first active region graph;
the polycrystalline silicon strip layout comprises polycrystalline silicon strip patterns, the polycrystalline silicon strip patterns and the strip metal strip patterns are arranged in parallel at intervals, and cross the first active region patterns and the shallow trench isolation structure patterns alternately arranged with the first active region patterns;
the side wall layout comprises side wall graphs, and the side wall graphs are positioned on the side edges of the polycrystalline silicon strip graphs and between the polycrystalline silicon strip graphs and the strip metal strip graphs; and the number of the first and second groups,
the dielectric layer layout comprises a dielectric layer graph, and the dielectric layer graph is at least positioned between the active region graph and the polycrystalline silicon strip graph.
Optionally, each of the bar-shaped metal bar patterns spans all of the first active region patterns.
Optionally, at least two polysilicon stripe patterns are provided, at least two polysilicon stripe patterns are respectively arranged in parallel with the second active region pattern at intervals, one strip metal stripe pattern is arranged between two adjacent polysilicon stripe patterns, and the strip metal stripe pattern is arranged in the middle of two adjacent polysilicon stripe patterns; alternatively, the first and second electrodes may be,
two strip-shaped metal strip patterns are arranged between two adjacent polysilicon strip patterns, and the distance between the two adjacent polysilicon strip patterns is trisected by the two strip-shaped metal strip patterns.
Optionally, the width of the bar-shaped metal strip pattern is 0.15 um-0.2 um, and the distance between the bar-shaped metal strip pattern and the polysilicon strip pattern is 0.05 um-0.1 um.
In order to solve the above problems, the present invention further provides a method for monitoring residual polysilicon, comprising:
providing any one of the residual polysilicon monitoring structures;
applying voltage to adjacent strip-shaped metal strips and adjacent polysilicon strips, measuring the current between the strip-shaped metal strips and the polysilicon strips to which the voltage is applied, and judging whether residual polysilicon exists in the side wall on the side edge of the polysilicon strips to which the voltage is applied according to the current.
Optionally, 0V voltage is applied to the strip-shaped metal strip, and 10V to 12V voltage is applied to the polysilicon strip.
Optionally, if the current between the adjacent strip-shaped metal strip and the polysilicon strip to which the voltage is applied is 0-100A, determining that the residual polysilicon exists in the side wall of the polysilicon strip to which the voltage is applied; and the number of the first and second groups,
and if the current between the adjacent strip-shaped metal strips and the polysilicon strips to which the voltage is applied is 1-100 muA, judging that no residual polysilicon is left in the side wall on the side edge of the polysilicon strip to which the voltage is applied.
In order to solve the above problem, the present invention further provides a semiconductor device, including the residual polysilicon monitoring structure as described in any one of the above, wherein the residual polysilicon monitoring structure is formed in a scribe line region of the substrate.
According to the residual polysilicon monitoring structure provided by the invention, the metal strip positioned on the second active region is arranged into a strip shape, and the strip metal strip crosses the first active region. This can greatly shorten the distance between the edge of the metal strip and the remaining polysilicon. When voltage is applied to the strip-shaped metal strip and the polysilicon strip, the side wall between the metal strip and the polysilicon strip is more easily broken down, and the current between the metal strip and the polysilicon strip is more easily detected. The detection rate of the residual polysilicon in the side wall on the side edge of the polysilicon strip is improved, and the monitoring effect of the residual polysilicon monitoring structure is further improved.
Drawings
Fig. 1 is a schematic top view of a structure of a residual polysilicon monitoring structure according to an embodiment of the invention.
Fig. 2 is a cross-sectional view taken along the direction AB in fig. 1.
Fig. 3 is a schematic top view of a portion of a structure of a residual polysilicon monitor structure according to an embodiment of the invention.
Fig. 4 is a schematic top view of a layout of a residual polysilicon monitoring structure according to an embodiment of the present invention.
Wherein the reference numbers are as follows:
1-an active region;
11-a first active region; 12-a second active region;
2-shallow trench isolation structure;
3-a polysilicon strip;
4-strip metal strips 4;
5-side wall;
6-a dielectric layer;
7-residual polysilicon;
a-an active area layout;
10-active area pattern;
101-a first active area pattern; 102-a second active area pattern;
b-shallow trench isolation structure layout; 20-shallow trench isolation structure pattern;
c-polysilicon strip layout; 30-polysilicon stripe pattern;
d, a strip metal strip layout; 40-metal bar pattern;
e-side wall layout; 50-side wall graph;
f, dielectric layer layout; 60-dielectric layer pattern.
Detailed Description
The remaining polysilicon monitoring structure, the structure layout, the method and the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
Fig. 1 is a schematic top view of a structure of a residual polysilicon monitoring structure according to an embodiment of the invention. Fig. 2 is a cross-sectional view taken along the direction AB in fig. 1. Fig. 3 is a schematic top view of a portion of a structure of a residual polysilicon monitor structure according to an embodiment of the invention. As shown in fig. 1 to fig. 3, the present embodiment provides a structure for monitoring residual polysilicon, including: the structure comprises a substrate 100 with an active region 1 and a shallow trench isolation structure 2, a polycrystalline silicon strip 3, a strip-shaped metal strip 4, a side wall 5 and a dielectric layer 6, wherein the polycrystalline silicon strip 3, the strip-shaped metal strip 4, the side wall 5 and the dielectric layer 6 are formed on the substrate 100;
wherein the active region 1 comprises at least one first active region 11 and at least one second active region 12, the first active region 11 and the second active region 12 vertically crossing each other; the shallow trench isolation structures 2 are alternately arranged with the first active regions 11 and the second active regions 12.
The strip-shaped metal strip 4 is located on the second active region 12 and crosses the first active region 11. The polysilicon strips 3 and the strip-shaped metal strips 4 are arranged in parallel at intervals and also cross the first active region 11 and the shallow trench isolation structures 2 alternately arranged with the first active region 11. The side walls 5 are formed on the side edges of the polycrystalline silicon strips 3 and located between the polycrystalline silicon strips 3 and the strip-shaped metal strips 4, and the dielectric layers are formed on the substrate 100 and at least located between the active region 1 and the polycrystalline silicon strips 3, so that the active region 1 and the polycrystalline silicon strips 3 are insulated from each other. And, in this embodiment, the strip-shaped metal strips 4 and the active region 1 are mutually conducted.
When the detection structure is detected, voltage can be applied to the metal strip 4 and the polycrystalline silicon strip 3 to obtain the current between the metal strip 4 and the polycrystalline silicon strip 3, and whether residual polycrystalline silicon 7 exists in the side wall 5 on the side edge of the polycrystalline silicon strip 3 after the polycrystalline silicon strip 3 is formed by etching is judged according to the current.
Due to the height difference in the area where the first active region 11 intersects the shallow trench isolation structure 2, there is usually residual polysilicon 7 at the intersection of the first active region 11 and the shallow trench isolation structure 2 when etching to form the polysilicon strip 3 across the first active region 11 and the shallow trench isolation structure 2. In the present embodiment, the metal strips 4 on the second active regions 2 (which cross the first active regions 11 perpendicularly to each other) are arranged in a strip shape, and the metal strips 4 cross the first active regions 11. The distance between the edge of the metal strip 4 and the residual polysilicon 7 can be greatly shortened. Therefore, when voltage is applied to the strip-shaped metal strips 4 and the polycrystalline silicon strips 3, the side walls 5 between the metal strips 4 and the polycrystalline silicon strips 3 are more easily broken down, and the current between the metal strips 4 and the polycrystalline silicon strips 3 is more easily detected. The detection rate of the residual polysilicon 7 in the side wall 5 on the side edge of the polysilicon strip 3 is improved, and the monitoring effect of the residual polysilicon monitoring structure is further improved.
With continued reference to fig. 1 to fig. 3, there are at least two first active regions 11, at least two first active regions 11 are spaced apart and arranged in parallel, and the rectangular metal strip 4 spans all the first active regions 11. In this way, the residual polysilicon 7 on all the first active regions 11 can be monitored, so as to further improve the monitoring effect of the residual polysilicon monitoring structure. In this embodiment, the number of the second active regions 12 is also at least two, and two adjacent second active regions 12 are arranged in parallel, wherein the shallow trench isolation structure 2 isolates the adjacent first active regions 11 and the adjacent second active regions 12.
In this embodiment, the ions implanted in the active region 1 may be P-type ions or N-type ions. The shallow trench isolation structure 2, the sidewall 5 and the dielectric layer 6 may be made of at least one material selected from silicon oxide, silicon nitride and silicon oxynitride.
Further, with reference to fig. 1, in this embodiment, at least two polysilicon strips 3 are provided, at least two polysilicon strips 3 are respectively disposed in parallel with the second active region 12 at intervals, one strip-shaped metal strip 4 is disposed between two adjacent polysilicon strips 3, and the strip-shaped metal strip 4 is disposed in the middle of two adjacent polysilicon strips 3. Therefore, detection abnormality caused by unequal distances in the monitoring process is avoided.
In addition, optionally, two strip-shaped metal strips 4 are arranged between two adjacent polysilicon strips 3, and the distance between the two adjacent polysilicon strips 3 is trisected by the two strip-shaped metal strips 4. Thus, two sets of monitoring data can be obtained, and an accurate monitoring structure can be obtained by mutually correcting the two sets of data, for example, averaging and the like.
Further, the width of metal strip 4 is 0.15um ~ 0.2um, and rectangle metal strip 4 with distance between the polycrystalline silicon strip 3 is 0.05um ~ 0.1 um.
Based on the detection structure as described above, the present embodiment also provides a semiconductor device including the monitoring structure of residual polysilicon as described above, which is disposed in the scribe lane region of the substrate 100.
Furthermore, the structure, the size and the like of each part of the monitoring structure in the dicing lane area can be the same as the structure, the size and the like of the device in the device area of the semiconductor device, so that the polysilicon residue condition of the device area can be accurately reflected by using the monitoring structure. For example, the polysilicon strips 3 in the monitoring structure may correspond to the word line structure of the flash memory in the device region, and the active region 1 in the monitoring structure is the same as the active region structure of the flash memory. And floating gates, side wall structures, bit lines and the like of the flash memory can be formed in the middle positions between the adjacent polysilicon strips in the device region.
With continued reference to fig. 1 to 3, the present embodiment further discloses a method for monitoring residual polysilicon, which includes the following first step and second step.
In step one, the residual polysilicon monitoring structure as described above is provided.
In the second step, a voltage is applied to the adjacent strip-shaped metal strips 4 and the adjacent polysilicon strips 3, the magnitude of the current between the strip-shaped metal strips 4 and the polysilicon strips 3 to which the voltage is applied is measured, and whether residual polysilicon 7 exists in the side walls 5 of the polysilicon strips 3 to which the voltage is applied is judged according to the magnitude of the current.
In the present embodiment, a voltage of 0V is applied to the strip-shaped metal strip 4, and a voltage of 10V to 12V is applied to the polysilicon strip. And if the current between the adjacent strip-shaped metal strip 4 and the polysilicon strip 3 to which the voltage is applied is 0-100A, judging that the residual polysilicon 7 exists in the side wall 5 of the polysilicon strip 3 to which the voltage is applied.
And if the current between the adjacent strip-shaped metal strip 4 and the polysilicon strip 3 to which the voltage is applied is 1 muA-100 muA, judging that the side wall 5 on the side of the polysilicon strip 3 to which the voltage is applied has no residual polysilicon 7.
Fig. 4 is a schematic top view of a layout of a residual polysilicon monitoring structure according to an embodiment of the present invention. As shown in fig. 4, this embodiment further discloses a residual polysilicon test structure layout, wherein the residual polysilicon monitor structure layout is used for preparing the residual polysilicon monitor structure as described above, and the residual polysilicon monitor structure layout is superimposed with an active region layout a, a shallow trench isolation structure layout B, a polysilicon layout C, a strip-shaped metal strip layout D, a side wall layout E, and a dielectric layer layout F.
In this embodiment, the active region layout a includes at least one first active region pattern 101 and at least one second active region pattern 102, where the first active region pattern 101 and the second active region pattern 102 are perpendicular to each other.
The shallow trench isolation structure layout B includes a shallow trench isolation structure pattern 20, and the shallow trench isolation pattern 20, the first active region pattern 101, and the second active region pattern 102 are alternately arranged.
The strip-shaped metal strip layout D comprises a strip-shaped metal strip pattern 40, and the strip-shaped metal strip pattern 40 is located on the second active region pattern 102 and spans the first active region pattern 101.
The polysilicon strip layout C comprises a polysilicon strip graph 30, wherein the polysilicon strip graph 30 and the strip metal strip graph 40 are arranged in parallel at intervals, and cross the first active region graph 101 and the shallow trench isolation structure graphs 20 alternately arranged with the first active region graph 101.
The side wall layout E comprises a side wall graph 50, and the side wall graph 50 is positioned on the side edge of the polycrystalline silicon strip graph 30 and positioned between the polycrystalline silicon strip graph 30 and the strip-shaped metal strip graph 40; and the number of the first and second groups,
the dielectric layer layout F comprises a dielectric layer pattern 60, and the dielectric layer pattern 60 is at least positioned between the active region pattern 10 and the polysilicon stripe pattern 30.
Further, as shown in fig. 4, each of the bar-shaped metal bar patterns 40 spans all of the first active region patterns 101.
And, the number of the polysilicon stripe patterns 30 is at least two, at least two of the polysilicon stripe patterns 30 are respectively arranged in parallel with the second active region pattern 102 at intervals, one of the strip-shaped metal stripe patterns 40 is arranged between two adjacent polysilicon stripe patterns 30, and the strip-shaped metal stripe pattern 40 is arranged in the middle of two adjacent polysilicon stripe patterns 30.
Or, two strip-shaped metal strip patterns 40 are arranged between two adjacent polysilicon strip patterns 30, and the distance between the two adjacent polysilicon strip patterns 30 is trisected by the two strip-shaped metal strip patterns 40.
Continuing to refer to fig. 4, in this embodiment, the width of the bar-shaped metal bar pattern 20 is 0.15um to 0.2um, and the distance between the bar-shaped metal bar pattern 40 and the polysilicon bar pattern 30 is 0.05um to 0.1 um.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (12)
1. A residual polysilicon monitoring structure, comprising: a substrate with an active region and a shallow trench isolation structure, a polysilicon strip, a strip-shaped metal strip, a side wall and a dielectric layer formed on the substrate,
wherein the active regions comprise at least one first active region and at least one second active region, the first active region and the second active region are vertically crossed with each other, and the shallow trench isolation structures are alternately arranged with the first active region and the second active region;
the strip-shaped metal strip is positioned on the second active region and spans the first active region, the polycrystalline silicon strips and the strip-shaped metal strip are arranged in parallel at intervals and span the first active region and the shallow trench isolation structures alternately arranged with the first active region, the side walls are formed on the side edges of the polycrystalline silicon strips and positioned between the polycrystalline silicon strips and the strip-shaped metal strip, and the dielectric layer is formed on the substrate and at least positioned between the active region and the polycrystalline silicon strips; and the number of the first and second groups,
the metal strip and the polycrystalline silicon strip are used for being applied with voltage, and whether residual polycrystalline silicon exists in the side wall on the side edge of the polycrystalline silicon strip after the polycrystalline silicon strip is formed by etching is judged according to the current between the metal strip and the polycrystalline silicon strip.
2. The residual polysilicon monitor structure of claim 1, wherein each of said strip-shaped metal strips spans all of said first active regions.
3. The residual polysilicon monitoring structure of claim 1, wherein there are at least two polysilicon strips, at least two polysilicon strips are disposed in parallel with the second active region, one metal strip is disposed between two adjacent polysilicon strips, and the metal strip is disposed in the middle of two adjacent polysilicon strips; or two strip-shaped metal strips are arranged between two adjacent polycrystalline silicon strips, and the distance between the two adjacent polycrystalline silicon strips is trisected by the two strip-shaped metal strips.
4. The residual polysilicon monitoring structure of claim 1, wherein the width of the strip-shaped metal strip is 0.15um to 0.2um, and the distance between the strip-shaped metal strip and the polysilicon strip is 0.05um to 0.1 um.
5. A residual polysilicon monitoring structure layout is characterized in that the residual polysilicon monitoring structure layout is used for preparing a residual polysilicon monitoring structure according to any one of claims 1 to 4, and comprises an active region layout, a shallow trench isolation structure layout, a polysilicon layout, a metal strip layout, a side wall layout and a dielectric layer layout which are overlapped; wherein the content of the first and second substances,
the active area layout comprises at least one first active area graph and at least one second active area graph, and the first active area graph and the second active area graph are mutually and vertically crossed;
the shallow trench isolation structure layout comprises a shallow trench isolation structure graph, and the shallow trench isolation graph, the first active region graph and the second active region graph are alternately arranged;
the strip metal strip layout comprises a strip metal strip graph, and the strip metal strip graph is positioned on the second active region graph and stretches across the first active region graph;
the polycrystalline silicon strip layout comprises polycrystalline silicon strip patterns, the polycrystalline silicon strip patterns and the strip metal strip patterns are arranged in parallel at intervals, and cross the first active region patterns and the shallow trench isolation structure patterns alternately arranged with the first active region patterns;
the side wall layout comprises side wall graphs, and the side wall graphs are positioned on the side edges of the polycrystalline silicon strip graphs and between the polycrystalline silicon strip graphs and the strip metal strip graphs; and the number of the first and second groups,
the dielectric layer layout comprises a dielectric layer graph, and the dielectric layer graph is at least positioned between the active region graph and the polycrystalline silicon strip graph.
6. The residual polysilicon monitor structure layout of claim 5, wherein each of said bar-shaped metal strip patterns spans all of said first active region patterns.
7. The residual polysilicon monitor structure layout as set forth in claim 5, wherein there are at least two polysilicon stripe patterns, at least two of the polysilicon stripe patterns are respectively arranged in parallel with the second active region pattern at an interval, one of the stripe metal stripe patterns is arranged between two adjacent polysilicon stripe patterns, and the stripe metal stripe pattern is arranged right in the middle of two adjacent polysilicon stripe patterns; alternatively, the first and second electrodes may be,
two strip-shaped metal strip patterns are arranged between two adjacent polysilicon strip patterns, and the distance between the two adjacent polysilicon strip patterns is trisected by the two strip-shaped metal strip patterns.
8. The residual polysilicon monitoring structure layout of claim 5, wherein the width of the bar-shaped metal bar pattern is 0.15um to 0.2um, and the distance between the bar-shaped metal bar pattern and the polysilicon bar pattern is 0.05um to 0.1 um.
9. A method for monitoring residual polysilicon, comprising:
providing a residual polysilicon monitoring structure according to any one of claims 1 to 4;
applying voltage to adjacent strip-shaped metal strips and adjacent polysilicon strips, measuring the current between the strip-shaped metal strips and the polysilicon strips to which the voltage is applied, and judging whether residual polysilicon exists in the side wall on the side edge of the polysilicon strips to which the voltage is applied according to the current.
10. The method for monitoring residual polysilicon as set forth in claim 9, wherein a voltage of 0V is applied to the strip-shaped metal strip and a voltage of 10V to 12V is applied to the polysilicon strip.
11. The method for monitoring residual polysilicon according to claim 9, wherein if the current between the adjacent strip-shaped metal strip and the polysilicon strip to which the voltage is applied is 0 to 100A, it is determined that the residual polysilicon exists in the sidewall of the side edge of the polysilicon strip to which the voltage is applied; and the number of the first and second groups,
and if the current between the adjacent strip-shaped metal strips and the polysilicon strips to which the voltage is applied is 1-100 muA, judging that no residual polysilicon is left in the side wall on the side edge of the polysilicon strip to which the voltage is applied.
12. A semiconductor device comprising the residual polysilicon monitor structure according to any one of claims 1 to 4, wherein the residual polysilicon monitor structure is formed in a scribe line region of the substrate.
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