CN113192931B - Residual polysilicon monitoring structure, structure layout, method and semiconductor device - Google Patents
Residual polysilicon monitoring structure, structure layout, method and semiconductor device Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 204
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 187
- 238000012544 monitoring process Methods 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 111
- 238000002955 isolation Methods 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 7
- 238000001514 detection method Methods 0.000 abstract description 6
- 230000015654 memory Effects 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Abstract
The invention provides a residual polysilicon monitoring structure, a structure layout, a method and a semiconductor device. This can greatly shorten the distance between the edges of the metal strips and the residual polysilicon. When voltage is applied to the strip-shaped metal strip and the polysilicon strip, the side wall between the metal strip and the polysilicon is more easily broken down, and the current between the metal strip and the polysilicon is more easily detected. The detection rate of the residual polysilicon in the side wall at the side edge of the polysilicon strip is improved, and the monitoring effect of the residual polysilicon monitoring structure is further improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a residual polysilicon monitoring structure, layout, method, and semiconductor device.
Background
With the improvement of living standard of people, electronic products are increasingly widely used, and various semiconductor products are generally used in the electronic products. With the development of technology and the increase of demands of people, the performance requirements of semiconductor products are also increasing.
For example, for a flash memory with memory cells, the performance of the flash memory is greatly reduced due to the failure of the flash memory, and one reason for the early failure of the flash memory is that the flash memory is failed due to the height difference between the shallow trench isolation structure and the active area on the substrate, which has the effect of causing the polysilicon to remain when the word line is formed by etching, and further causing the word line and the active area to be shorted when the word line is at a high voltage. Therefore, monitoring of residual polysilicon is an important monitoring item in the manufacturing process of flash memories. The existing residual polysilicon monitoring structure generally has poor monitoring effect when monitoring residual polysilicon.
Disclosure of Invention
The invention aims to provide a residual polysilicon monitoring structure, a structure layout, a method and a semiconductor device, which are used for solving the problem that the monitoring effect is poor when the existing residual polysilicon monitoring structure is used for monitoring residual polysilicon.
In order to solve the above technical problems, the present invention provides a residual polysilicon monitoring structure, comprising: the substrate with the active region and the shallow trench isolation structure, the polysilicon strip, the strip-shaped metal strip, the side wall and the dielectric layer which are formed on the substrate,
the shallow trench isolation structure is alternately arranged with the first active region and the second active region;
the strip-shaped metal strips are positioned on the second active area and transversely span the first active area, the polysilicon strips are arranged in parallel with the strip-shaped metal strips at intervals and transversely span the first active area and the shallow trench isolation structures alternately arranged with the first active area, the side walls are formed on the side edges of the polysilicon strips and positioned between the polysilicon strips and the strip-shaped metal strips, and the dielectric layer is formed on the substrate and at least positioned between the active area and the polysilicon strips; the method comprises the steps of,
the metal strip and the polysilicon strip are used for being applied with voltage so as to judge whether residual polysilicon exists in the side wall positioned on the side edge of the polysilicon strip after the polysilicon strip is formed by etching according to the current between the metal strip and the polysilicon strip.
Optionally, each of the strip-shaped metal strips spans all of the first active regions.
Optionally, at least two polysilicon strips are arranged in parallel with the second active space, one strip-shaped metal strip is arranged between two adjacent polysilicon strips, and the strip-shaped metal strip is arranged in the middle of the two adjacent polysilicon strips; or two strip-shaped metal strips are arranged between two adjacent polysilicon strips, and the distance between the two adjacent polysilicon strips is halved by the two strip-shaped metal strips.
Optionally, the width of the strip-shaped metal strip is 0.15 um-0.2 um, and the distance between the strip-shaped metal strip and the polysilicon strip is 0.05 um-0.1 um.
In order to solve the problems, the invention also provides a residual polysilicon monitoring structure layout, which is used for preparing the residual polysilicon monitoring structure according to any one of the above, and comprises an active area layout, a shallow trench isolation structure layout, a polysilicon strip layout, a strip metal strip layout, a side wall layout and a dielectric layer layout which are overlapped; wherein,
the active area layout comprises at least one first active area graph and at least one second active area graph, and the first active area graph and the second active area graph are mutually perpendicular and crossed;
the shallow trench isolation structure layout comprises shallow trench isolation structure patterns, and the shallow trench isolation structure patterns, the first active region patterns and the second active region patterns are alternately arranged;
the strip metal strip layout comprises strip metal strip patterns which are positioned on the second active region patterns and cross the first active region patterns;
the polycrystalline silicon strip layout comprises polycrystalline silicon strip patterns, wherein the polycrystalline silicon strip patterns are arranged in parallel with the strip metal strip patterns at intervals and cross the first active region patterns and the shallow trench isolation structure patterns alternately arranged with the first active region patterns;
the side wall layout comprises side wall patterns, wherein the side wall patterns are positioned on the side edges of the polycrystalline silicon strip patterns and are positioned between the polycrystalline silicon strip patterns and the strip-shaped metal strip patterns; the method comprises the steps of,
the dielectric layer layout comprises dielectric layer patterns, and the dielectric layer patterns are at least positioned between the active region patterns and the polysilicon strip patterns.
Optionally, each of the bar metal stripe patterns spans all of the first active region patterns.
Optionally, at least two polysilicon stripe patterns are arranged in parallel with the second active region patterns, one stripe metal stripe pattern is arranged between two adjacent polysilicon stripe patterns, and the stripe metal stripe pattern is arranged in the middle of the two adjacent polysilicon stripe patterns; or,
two strip-shaped metal strip patterns are arranged between two adjacent polysilicon strip patterns, and the two strip-shaped metal strip patterns trisect the distance between the two adjacent polysilicon strip patterns.
Optionally, the width of the strip-shaped metal strip pattern is 0.15 um-0.2 um, and the distance between the strip-shaped metal strip pattern and the polysilicon strip pattern is 0.05 um-0.1 um.
In order to solve the above problems, the present invention further provides a method for monitoring residual polysilicon, including:
providing a residual polysilicon monitoring structure as set forth in any one of the preceding claims;
applying voltage to the adjacent strip-shaped metal strips and polysilicon strips, measuring the current between the strip-shaped metal strips and the polysilicon strips, and judging whether residual polysilicon exists in the side walls of the sides of the polysilicon strips to which the voltage is applied according to the current.
Optionally, 0V voltage is applied to the strip-shaped metal strip, and 10V-12V voltage is applied to the polysilicon strip.
Optionally, if the current between the adjacent strip-shaped metal strips and the polysilicon strips to which the voltage is applied is 0-100A, judging that the residual polysilicon exists in the side wall of the side edge of the polysilicon strips to which the voltage is applied; the method comprises the steps of,
and if the current between the adjacent strip-shaped metal strips and the polysilicon strips subjected to the voltage is 1 mu A-100 mu A, judging that no residual polysilicon exists in the side wall of the side edge of the polysilicon strips subjected to the voltage.
In order to solve the above problems, the present invention further provides a semiconductor device, which is characterized by comprising the residual polysilicon monitoring structure as set forth in any one of the above, wherein the residual polysilicon monitoring structure is formed in a scribe line region of the substrate.
According to the residual polysilicon monitoring structure provided by the invention, the metal strips on the second active area are arranged in a strip shape, and the strip-shaped metal strips cross the first active area. This can greatly shorten the distance between the edges of the metal strips and the residual polysilicon. When voltage is applied to the strip-shaped metal strip and the polysilicon strip, the side wall between the metal strip and the polysilicon is more easily broken down, and the current between the metal strip and the polysilicon is more easily detected. The detection rate of the residual polysilicon in the side wall at the side edge of the polysilicon strip is improved, and the monitoring effect of the residual polysilicon monitoring structure is further improved.
Drawings
Fig. 1 is a schematic top view of a residual polysilicon monitor structure according to an embodiment of the invention.
Fig. 2 is a cross-sectional view taken along direction AB in fig. 1.
Fig. 3 is a schematic top view of a residual polysilicon monitor structure according to an embodiment of the invention.
Fig. 4 is a schematic top view of a residual polysilicon monitor structure layout according to an embodiment of the present invention.
Wherein, the reference numerals are as follows:
1-an active region;
11-a first active region; 12-a second active region;
2-shallow trench isolation structures;
3-polysilicon strips;
4-strip-shaped metal strips 4;
5-side walls;
6-a dielectric layer;
7-residual polysilicon;
a-an active area layout;
10-active region pattern;
101-a first active region pattern; 102-a second active area pattern;
b-shallow trench isolation structure layout; 20-shallow trench isolation structure patterns;
c-polycrystalline silicon strip layout; 30-polysilicon stripe pattern;
d-strip metal strip layout; 40-metal bar patterns;
e-side wall layout; 50-side wall patterns;
f-dielectric layer layout; 60-dielectric layer pattern.
Detailed Description
The residual polysilicon monitoring structure, the structure layout, the method and the semiconductor device provided by the invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
Fig. 1 is a schematic top view of a residual polysilicon monitor structure according to an embodiment of the invention. Fig. 2 is a cross-sectional view taken along direction AB in fig. 1. Fig. 3 is a schematic top view of a residual polysilicon monitor structure according to an embodiment of the invention. As shown in fig. 1 to 3, the residual polysilicon monitoring structure provided in this embodiment includes: the semiconductor device comprises a substrate 100 with an active region 1 and a shallow trench isolation structure 2, a polysilicon strip 3, a strip-shaped metal strip 4, a side wall 5 and a dielectric layer 6, wherein the polysilicon strip 3, the strip-shaped metal strip 4, the side wall 5 and the dielectric layer 6 are formed on the substrate 100;
wherein the active region 1 comprises at least one first active region 11 and at least one second active region 12, the first active region 11 and the second active region 12 perpendicularly intersecting each other; the shallow trench isolation structures 2 are alternately arranged with the first active regions 11 and the second active regions 12.
The strip-shaped metal strip 4 is located on the second active region 12 and spans the first active region 11. The polysilicon strips 3 are arranged in parallel with the strip-shaped metal strips 4 at intervals and also cross the first active regions 11 and the shallow trench isolation structures 2 alternately arranged with the first active regions 11. The side wall 5 is formed on the side edge of the polysilicon strip 3 and is located between the polysilicon strip 3 and the strip-shaped metal strip 4, and the dielectric layer is formed on the substrate 100 and is located at least between the active region 1 and the polysilicon strip 3, so as to insulate the active region 1 and the polysilicon strip 3 from each other. And, in this embodiment, the strip-shaped metal strip 4 and the active region 1 are mutually conducted.
When the detection structure is detected, voltage can be applied to the metal strip 4 and the polysilicon strip 3 to obtain the current between the metal strip 4 and the polysilicon strip 3, and whether residual polysilicon 7 exists in the side wall 5 positioned at the side edge of the polysilicon strip 3 after the polysilicon strip 3 is formed by etching is judged according to the current.
Since there is a difference in height in the area where the first active region 11 intersects the shallow trench isolation structure 2, when the polysilicon strip 3 is etched to cross the first active region 11 and the shallow trench isolation structure 2, there is typically residual polysilicon 7 at the intersection of the first active region 11 and the shallow trench isolation structure 2. In the present embodiment, the metal strips 4 on the second active regions 12 (crossing the first active regions 11 perpendicularly) are arranged in a stripe shape, and the metal strips 4 are made to cross the first active regions 11. The distance between the edges of the metal strips 4 and the residual polysilicon 7 can be greatly shortened. Thus, when a voltage is applied to the strip-shaped metal strip 4 and the polysilicon strip 3, the side wall 5 between the metal strip 4 and the polysilicon strip 3 is more easily broken down, and the current between the metal strip 4 and the polysilicon strip 3 is more easily detected. So as to improve the detection rate of the residual polysilicon 7 in the side wall 5 positioned at the side edge of the polysilicon strip 3, and further improve the monitoring effect of the residual polysilicon monitoring structure.
With continued reference to fig. 1 to 3, at least two first active regions 11 are provided, at least two first active regions 11 are disposed in parallel at intervals, and the rectangular metal strip 4 spans all the first active regions 11. In this way, the residual polysilicon 7 located on all the first active regions 11 can be monitored, so as to further improve the monitoring effect of the residual polysilicon monitoring structure. In this embodiment, at least two second active regions 12 are also provided, and two adjacent second active regions 12 are disposed parallel to each other, where the shallow trench isolation structure 2 isolates adjacent first active regions 11 and isolates adjacent second active regions 12.
In this embodiment, the ions implanted in the active region 1 may be P-type ions or N-type ions. The materials of the shallow trench isolation structure 2, the side wall 5 and the dielectric layer 6 may be at least one selected from silicon oxide, silicon nitride or silicon oxynitride.
Further, with continued reference to fig. 1, in this embodiment, at least two polysilicon strips 3 are provided, at least two polysilicon strips 3 are respectively disposed in parallel with the second active area 12 at intervals, one strip-shaped metal strip 4 is disposed between two adjacent polysilicon strips 3, and the strip-shaped metal strip 4 is disposed in the middle of two adjacent polysilicon strips 3. Therefore, detection errors caused by the problem of unequal distances during monitoring are avoided.
Furthermore, optionally, two strip-shaped metal strips 4 are arranged between two adjacent polysilicon strips 3, and the two strip-shaped metal strips 4 trisect the distance between the two adjacent polysilicon strips 3. Thus, two sets of monitoring data can be obtained, and the two sets of data can be mutually corrected to obtain accurate monitoring structures, such as averaging and the like.
Further, the width of the metal strip 4 is 0.15um to 0.2um, and the distance between the rectangular metal strip 4 and the polysilicon strip 3 is 0.05um to 0.1um.
Based on the detection structure as described above, the present embodiment also provides a semiconductor device, which includes the monitoring structure of residual polysilicon as described above, where the monitoring structure of residual polysilicon is disposed in the scribe line region of the substrate 100.
Furthermore, the structure, the size and the like of each part of the monitoring structure in the dicing channel region can be the same as the device structure, the size and the like in the device region of the semiconductor device, so that the polycrystalline silicon residue condition of the device region can be accurately reflected by using the monitoring structure. For example, the poly-silicon stripe 3 in the monitor structure may correspond to a word line structure of a flash memory in the device region, and the active region 1 in the monitor structure is the same as the active region structure of the flash memory. And floating gates, sidewall structures, bit lines and the like of the flash memory can be formed at intermediate positions between adjacent polysilicon strips in the device region.
With continued reference to fig. 1 to 3, the embodiment also discloses a method for monitoring residual polysilicon, which includes the following steps.
In a first step, a residual polysilicon monitor structure as described above is provided.
In the second step, a voltage is applied to the adjacent strip-shaped metal strips 4 and the polysilicon strips 3, the magnitude of the current between the strip-shaped metal strips 4 and the polysilicon strips 3 to which the voltage is applied is measured, and whether residual polysilicon 7 exists in the side wall 5 at the side edge of the polysilicon strips 3 to which the voltage is applied is judged according to the magnitude of the current.
In this embodiment, a voltage of 0V is applied to the strip-shaped metal strip 4, and a voltage of 10V to 12V is applied to the polysilicon strip. And judging that the residual polysilicon 7 exists in the side wall 5 at the side edge of the polysilicon strip 3 to which the voltage is applied when the current between the adjacent strip-shaped metal strip 4 and the polysilicon strip 3 to which the voltage is applied is 0-100A.
And if the current between the adjacent strip-shaped metal strips 4 and the polysilicon strips 3 to which the voltage is applied is 1 mu A-100 mu A, judging that the side wall 5 at the side edge of the polysilicon strips 3 to which the voltage is applied has no residual polysilicon 7.
Fig. 4 is a schematic top view of a residual polysilicon monitor structure layout according to an embodiment of the present invention. As shown in fig. 4, the embodiment further discloses a residual polysilicon test structure layout, where the residual polysilicon monitor structure layout is used for preparing the residual polysilicon monitor structure described above, and the active area layout a, the shallow trench isolation structure layout B, the polysilicon strip layout C, the strip metal strip layout D, the side wall layout E and the dielectric layer layout F are stacked by the residual polysilicon monitor structure layout.
In this embodiment, the active area layout a includes at least one first active area pattern 101 and at least one second active area pattern 102, where the first active area pattern 101 and the second active area pattern 102 intersect perpendicularly.
The shallow trench isolation structure layout B includes shallow trench isolation structure patterns 20, and the shallow trench isolation structure patterns 20, the first active region patterns 101 and the second active region patterns 102 are alternately arranged.
The strip metal strip layout D includes a strip metal strip pattern 40, and the strip metal strip pattern 40 is located on the second active region pattern 102 and spans the first active region pattern 101.
The polysilicon stripe layout C includes polysilicon stripe patterns 30, where the polysilicon stripe patterns 30 are arranged in parallel with the stripe metal stripe patterns 40 at intervals, and cross over the first active region patterns 101 and the shallow trench isolation structure patterns 20 alternately arranged with the first active region patterns 101.
The side wall layout E comprises side wall patterns 50, wherein the side wall patterns 50 are positioned on the side edges of the polysilicon strip patterns 30 and between the polysilicon strip patterns 30 and the strip metal strip patterns 40; the method comprises the steps of,
the dielectric layer layout F includes a dielectric layer pattern 60, and the dielectric layer pattern 60 is at least located between the active region pattern 10 and the polysilicon stripe pattern 30.
Further, with continued reference to fig. 4, each of the bar metal stripe patterns 40 spans all of the first active region patterns 101.
And at least two polysilicon stripe patterns 30, at least two polysilicon stripe patterns 30 are respectively arranged in parallel with the second active region pattern 102 at intervals, one stripe metal stripe pattern 40 is arranged between two adjacent polysilicon stripe patterns 30, and the stripe metal stripe pattern 40 is arranged in the middle of two adjacent polysilicon stripe patterns 30.
Alternatively, two bar-shaped metal bar patterns 40 are disposed between two adjacent polysilicon bar patterns 30, and the distance between two adjacent polysilicon bar patterns 30 is trisected by two bar-shaped metal bar patterns 40.
With continued reference to fig. 4, in this embodiment, the width of the stripe metal stripe pattern 20 is 0.15um to 0.2um, and the distance between the stripe metal stripe pattern 40 and the polysilicon stripe pattern 30 is 0.05um to 0.1um.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (12)
1. A residual polysilicon monitoring structure, comprising: the substrate with the active region and the shallow trench isolation structure, the polysilicon strip, the strip-shaped metal strip, the side wall and the dielectric layer which are formed on the substrate,
the shallow trench isolation structure is alternately arranged with the first active region and the second active region;
the strip-shaped metal strips are positioned on the second active area and transversely span the first active area, the polysilicon strips are arranged in parallel with the strip-shaped metal strips at intervals and transversely span the first active area and the shallow trench isolation structures alternately arranged with the first active area, the side walls are formed on the side edges of the polysilicon strips and positioned between the polysilicon strips and the strip-shaped metal strips, and the dielectric layer is formed on the substrate and at least positioned between the active area and the polysilicon strips; the method comprises the steps of,
the metal strip and the polysilicon strip are used for being applied with voltage so as to judge whether residual polysilicon exists in the side wall positioned on the side edge of the polysilicon strip after the polysilicon strip is formed by etching according to the current between the metal strip and the polysilicon strip.
2. The residual polysilicon monitoring structure of claim 1, wherein each of the strip-shaped metal strips spans all of the first active regions.
3. The residual polysilicon monitoring structure of claim 1, wherein at least two polysilicon strips are arranged in parallel with the second active space, one strip-shaped metal strip is arranged between two adjacent polysilicon strips, and the strip-shaped metal strip is arranged in the middle of the two adjacent polysilicon strips; or two strip-shaped metal strips are arranged between two adjacent polysilicon strips, and the distance between the two adjacent polysilicon strips is halved by the two strip-shaped metal strips.
4. The residual polysilicon monitoring structure of claim 1, wherein the strip-shaped metal strip has a width of 0.15um to 0.2um, and a distance between the strip-shaped metal strip and the polysilicon strip is 0.05um to 0.1um.
5. A residual polycrystalline silicon monitoring structure layout, which is characterized in that the residual polycrystalline silicon monitoring structure layout is used for preparing the residual polycrystalline silicon monitoring structure according to any one of claims 1-4, and comprises an active area layout, a shallow trench isolation structure layout, a polycrystalline silicon strip layout, a strip metal strip layout, a side wall layout and a dielectric layer layout which are overlapped; wherein,
the active area layout comprises at least one first active area graph and at least one second active area graph, and the first active area graph and the second active area graph are mutually perpendicular and crossed;
the shallow trench isolation structure layout comprises shallow trench isolation structure patterns, and the shallow trench isolation structure patterns, the first active region patterns and the second active region patterns are alternately arranged;
the strip metal strip layout comprises strip metal strip patterns which are positioned on the second active region patterns and cross the first active region patterns;
the polycrystalline silicon strip layout comprises polycrystalline silicon strip patterns, wherein the polycrystalline silicon strip patterns are arranged in parallel with the strip metal strip patterns at intervals and cross the first active region patterns and the shallow trench isolation structure patterns alternately arranged with the first active region patterns;
the side wall layout comprises side wall patterns, wherein the side wall patterns are positioned on the side edges of the polycrystalline silicon strip patterns and are positioned between the polycrystalline silicon strip patterns and the strip-shaped metal strip patterns; the method comprises the steps of,
the dielectric layer layout comprises dielectric layer patterns, and the dielectric layer patterns are at least positioned between the active region patterns and the polysilicon strip patterns.
6. The residual polysilicon monitoring structure layout of claim 5 wherein each of said bar metal stripe patterns spans all of said first active area patterns.
7. The residual polysilicon monitoring structure layout according to claim 5, wherein at least two polysilicon stripe patterns are arranged in parallel with the second active region patterns respectively, one stripe metal stripe pattern is arranged between two adjacent polysilicon stripe patterns, and the stripe metal stripe pattern is arranged in the middle of the two adjacent polysilicon stripe patterns; or,
two strip-shaped metal strip patterns are arranged between two adjacent polysilicon strip patterns, and the two strip-shaped metal strip patterns trisect the distance between the two adjacent polysilicon strip patterns.
8. The residual polysilicon monitoring structure layout of claim 5, wherein the width of the bar-shaped metal bar pattern is 0.15um to 0.2um, and the distance between the bar-shaped metal bar pattern and the polysilicon bar pattern is 0.05um to 0.1um.
9. A method for monitoring residual polysilicon, comprising:
providing a residual polysilicon monitoring structure as set forth in any one of claims 1-4;
applying voltage to the adjacent strip-shaped metal strips and polysilicon strips, measuring the current between the strip-shaped metal strips and the polysilicon strips, and judging whether residual polysilicon exists in the side walls of the sides of the polysilicon strips to which the voltage is applied according to the current.
10. The method of claim 9, wherein 0V is applied to the strip and 10V to 12V is applied to the strip.
11. The method for monitoring residual polysilicon according to claim 9, wherein if the current between the adjacent strip-shaped metal strip and the polysilicon strip to which the voltage is applied is 0-100A, determining that the residual polysilicon exists in the sidewall of the side edge of the polysilicon strip to which the voltage is applied; the method comprises the steps of,
and if the current between the adjacent strip-shaped metal strips and the polysilicon strips subjected to the voltage is 1 mu A-100 mu A, judging that the side walls at the sides of the polysilicon strips subjected to the voltage are free of the residual polysilicon.
12. A semiconductor device comprising a residual polysilicon monitor structure as set forth in any one of claims 1-4 formed in a scribe line region of the substrate.
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