CN116230498A - Process for manufacturing high-density BMD shallow DZ layer 12-inch silicon wafer - Google Patents

Process for manufacturing high-density BMD shallow DZ layer 12-inch silicon wafer Download PDF

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CN116230498A
CN116230498A CN202310094524.0A CN202310094524A CN116230498A CN 116230498 A CN116230498 A CN 116230498A CN 202310094524 A CN202310094524 A CN 202310094524A CN 116230498 A CN116230498 A CN 116230498A
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bmd
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王虎
孙林杉
李鹏飞
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Zhonghuan Advanced Semiconductor Materials Co Ltd
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    • H—ELECTRICITY
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    • H01L21/02002—Preparing wafers
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    • H01L21/02008—Multistep processes
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    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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    • C30B33/02—Heat treatment
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    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/08—Etching
    • C30B33/10—Etching in solutions or melts
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract

The invention discloses a process for manufacturing a high-density BMD shallow DZ layer 12-inch silicon wafer, which comprises the following steps: s1, firstly, raw materials such as a 12-inch straight pull silicon rod, ar, ammonia, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water which need to be prepared are proportioned according to certain components, and the proportioned raw materials such as the 12-inch straight pull silicon rod, ar, ammonia, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water are contained for standby through corresponding vessels; s2, performing wire cutting processing on the 12-inch straight-pull silicon rod. After the processing technology is adopted, the appearance, the natural oxide layer, the BMD and the DZ are similar to those of a 12-inch argon annealed sheet, but the COP FREE layer depth and Bulk Fe are far better than those of the 12-inch argon annealed sheet, and the phenomenon of slightly higher particles is influenced by the polishing in the current period.

Description

Process for manufacturing high-density BMD shallow DZ layer 12-inch silicon wafer
Technical Field
The invention relates to the technical field of semiconductor silicon wafers, in particular to a process for manufacturing a high-density BMD shallow DZ layer 12-inch silicon wafer.
Background
The growth of semiconductors to today, silicon materials take a significant role, and the growth of third generation semiconductor materials GaN, which are being vigorously developed today, also uses basically silicon-based substrates. The semiconductor single crystal is pulled into two main types of Czochralski and zone-melting, and the Czochralski single crystal has higher oxygen content in the body than the zone-melting single crystal because a quartz crucible is used, and the mechanical property of the silicon wafer is better than that of the zone-melting single crystal, so that the application field is far wider than that of the zone-melting single crystal. The device demand for defect-free and internal gettering of Czochralski silicon wafers has driven the continued development of Czochralski single crystal and silicon wafer processing techniques.
Defects in Czochralski wafers can be categorized into 4 general categories: (1) point defect: vacancy, interstitial, substitutional; (2) line defects: dislocations, etc.; (3) surface defects: stacking faults, grain boundaries, etc.; (4) body defects: d defects (crystal originated particles, COP for short), in vivo micro defects (BMD), etc. Among them, line defects and surface defects are harmful and unfavorable for Czochralski silicon wafer applications, and have been solved in the middle of the 20 th century in the development of single crystal technology.
The development of single crystal technology is plagued in the middle and later stages of the 20 th century, and the hydrogen annealing technology is developed by TOSHIBA Ceramics Co.LTD, so that the problem of the COP of the surface layer of the silicon wafer is solved, and the device manufacturing process requirement is met. Because the hydrogen danger is higher, the hydrogen annealing technology is gradually developed into argon annealing, and a DZ (clean zone) layer and a BMD layer are formed in the silicon wafer while the silicon wafer surface COP is solved by the argon annealing process, so that the requirement of devices on internal gettering is met, a crystal expert gradually optimizes a single crystal process and an annealing process in the later 20 th century, and the COP FREE depth and the BMD density of the silicon wafer are controlled to meet the requirements of different device manufacturing processes.
In the early period of the century, universities and enterprises such as universities of Zhejiang and universities of developed semiconductor materials, inc. have made comprehensive systematic researches on the COP, DZ depth and BMD density of argon annealed sheets. However, the argon annealed silicon wafer has two obvious disadvantages, namely that the COP FREE depth (the COP above 26nm is evaluated) of the silicon wafer is generally 5-10 mu m, and the COP is obviously increased along with the increase of the distance from the surface to the thickness center of the silicon wafer; but the annealing time in the furnace tube is long in the processing process of the argon annealing silicon wafer, and the Fe element content in the processed silicon wafer is higher. With the continuous reduction of the line width of the device end, the performance is continuously improved, and the requirements on the COP of the silicon chip and the content of Fe element in the body are higher and higher.
Therefore, research and development of a process for annealing silicon wafers by BMD, DZ and high-oxygen argon has important practical significance compared with the process for annealing silicon wafers by high-oxygen argon by using silicon wafers with COP and in-vivo Fe elements. MDZ silicon chip products developed by adopting the rapid thermal processing technology by MEMC have higher BMD density and deeper DZ, and low-density BMD silicon chips are also developed by adopting the rapid thermal processing technology by MEMC. In general, the deep DZ silicon wafer is annealed by introducing a small amount of oxygen in an argon atmosphere, and the Korean Sumsung silicon wafer is manufactured by introducing a small amount of ammonia in an argon atmosphere, wherein the silicon wafer is distributed from the surface of the silicon wafer to the thickness center of the silicon wafer in three layers, the surface layer of the silicon wafer is a shallow DZ layer, then a high-density BMD layer is arranged, and the BMD density near the thickness center of the silicon wafer is very low. Therefore, the rapid heat treatment technology can regulate and control the BMD and DZ of the silicon wafer, the rapid heat treatment process time is short, the influence on the content of Fe element in the silicon wafer is small, and in conclusion, how to develop the COP FREE depth, BMD and DZ of the matched argon annealed silicon wafer by using the rapid heat treatment technology and solve other problems in the processing process is the main problem solved by the invention.
Disclosure of Invention
The invention aims to provide a process for manufacturing a high-density BMD shallow DZ layer 12-inch silicon wafer, which solves the problems in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions: a process for fabricating a high density BMD shallow DZ layer 12 inch silicon wafer, the process comprising the steps of:
s1, firstly, raw materials such as 12-inch straight pull silicon rods, ar, ammonia water, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water which need to be prepared are proportioned according to certain components, and the proportioned raw materials such as the 12-inch straight pull silicon rods, ar, ammonia water, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water are contained for standby through corresponding vessels.
S2, performing wire cutting processing on the 12-inch straight-pull silicon rod, chamfering after the wire cutting processing is finished, grinding after the chamfering processing is finished, thinning after the grinding, RTP after the thinning, DSP and CMP processing after the RTP.
S3, performing rapid heat treatment and argon annealing treatment through a rapid heat treatment furnace and an argon annealing furnace, controlling the nitrogen content and the oxygen content of the silicon wafer, pulling crystal by adopting a COP FREE technology, regulating and controlling the annealing temperature, the annealing time, the temperature rise and fall rate and the annealing atmosphere of the rapid heat treatment process, optimizing the processing flow, solving the problems of abnormal surface appearance, abnormal particles, higher natural oxide layer and the like of the silicon wafer, and matching corresponding cleaning process before annealing to effectively ensure that the content of Fe element in the silicon wafer is the lowest.
S4, finally, inspecting the surface defects of the silicon wafer through a visual inspection instrument, testing the natural oxide layer on the surface of the silicon wafer through a film thickness tester, testing the content of Fe element in the silicon wafer through a bulk iron tester, testing the BMD and DZ of the silicon wafer through a BMD tester, and testing the surface particles of the silicon wafer through a particle tester, so as to obtain whether the quality requirement of the 12-inch straight-pulling silicon rod is qualified.
Preferably, the annealing temperature is 1280-1300 ℃, the annealing time is 10-30s, the heating rate is 50-80 ℃/s, the cooling rate is 80-10 ℃/s, and the annealing atmosphere is pure argon.
Preferably, the BMD density is 1-10E9atoms/cm3, the DZ layer is 10-30 μm, the monocrystal adopts nitrogen-doped COP FREE technology, the nitrogen content is controlled to be 1-10E13atoms/cm3, and the oxygen content is controlled to be 5.5-7.5atoms/cm3.
Preferably, the 12-inch Czochralski silicon rod must be cleaned with HF acid (HF: H2O=1:150-300), SC1 fluid (NH4.H2O: H2O2: DIW= (0.5-1.0): 3:30), and SC2 fluid (HCL: H2O2: DIW= (1-1.5): 3:30) prior to rapid thermal processing into the chamber.
Compared with the prior art, the invention has the beneficial effects that: compared with the processing flow of an argon annealed wafer, the high-temperature time is shorter, the content of Fe element in the silicon wafer is obviously reduced, the crystal pulling of the invention adopts the COP FREE technology, and compared with the COP FREE layer (no COP exists at 26nm or above) of the argon annealed wafer, the whole thickness range of the silicon wafer does not exist at 26nm or above, the invention optimizes the cleaning process after thinning, and effectively ensures that the content of Fe element in the silicon wafer is not influenced in the RTP process.
The monocrystal provided by the invention adopts a nitrogen doping technology, controls the oxygen content, optimizes the rapid heat treatment process parameters, matches BMD with DZ to obtain the high-oxygen argon annealed sheet, has shorter high-temperature process time in the processing process and smaller influence on the Fe element content in the silicon sheet, performs rapid heat treatment after thinning, and solves the problems of abnormal surface appearance, abnormal particles, higher natural oxide layer and the like in the DSP-RTP-CMP process by increasing the surface removal amount in the subsequent DSP process.
Drawings
FIG. 1 is a table of RTP process data of the present invention;
FIG. 2 is a table of the pre-RTP cleaning process recipe of the present invention;
FIG. 3 is a table of argon anneal process data parameters of the present invention;
FIG. 4 is a table of experimental results data of the present invention;
FIG. 5 is a schematic view of a silicon wafer surface according to the present invention;
FIG. 6 is a comparative view of a silicon wafer process of the present invention;
FIG. 7 is a graph showing the particle distribution of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiment one:
referring to fig. 1-7, the manufacturing process of the present embodiment includes the steps of:
s1, firstly, raw materials such as 12-inch straight pull silicon rods, ar, ammonia water, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water which need to be prepared are proportioned according to certain components, and the proportioned raw materials such as the 12-inch straight pull silicon rods, ar, ammonia water, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water are contained for standby through corresponding vessels.
S2, performing wire cutting processing on the 12-inch straight-pull silicon rod, chamfering after the wire cutting processing is finished, grinding after the chamfering processing is finished, thinning after the grinding, RTP after the thinning, DSP and CMP processing after the RTP.
S3, performing rapid heat treatment and argon annealing treatment through a rapid heat treatment furnace and an argon annealing furnace, controlling the nitrogen content and the oxygen content of the silicon wafer, pulling crystal by adopting a COP FREE technology, regulating and controlling the annealing temperature, the annealing time, the temperature rise and fall rate and the annealing atmosphere of the rapid heat treatment process, optimizing the processing flow, solving the problems of abnormal surface appearance, abnormal particles, higher natural oxide layer and the like of the silicon wafer, and matching corresponding cleaning process before annealing to effectively ensure that the content of Fe element in the silicon wafer is the lowest.
S4, finally, inspecting the surface defects of the silicon wafer through a visual inspection instrument, testing the natural oxide layer on the surface of the silicon wafer through a film thickness tester, testing the content of Fe element in the silicon wafer through a bulk iron tester, testing the BMD and DZ of the silicon wafer through a BMD tester, and testing the surface particles of the silicon wafer through a particle tester, so as to obtain whether the quality requirement of the 12-inch straight-pulling silicon rod is qualified.
In the embodiment, the annealing temperature is 1280-1300 ℃, the annealing time is 10-30s, the heating rate is 50-80 ℃/s, the cooling rate is 80-10 ℃/s, and the annealing atmosphere is pure argon.
In this example, the BMD density is 1-10E9atoms/cm3, the DZ layer is 10-30 μm, the monocrystal adopts nitrogen-doped COP FREE technology, the nitrogen content is controlled to be 1-10E13atoms/cm3, and the oxygen content is controlled to be 5.5-7.5atoms/cm3.
In this example, a 12 inch Czochralski silicon rod must be cleaned with HF acid (HF: H2O=1:150-300), SC1 fluid (NH4.H2O: H2O2: DIW= (0.5-1.0): 3:30), and SC2 fluid (HCL: H2O2: DIW= (1-1.5): 3:30) prior to rapid thermal processing into the chamber.
Embodiment two:
the distinguishing features from the first embodiment are that:
the manufacturing process of the present embodiment includes the steps of:
s1, firstly, raw materials such as 12-inch straight pull silicon rods, ar, ammonia water, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water which need to be prepared are proportioned according to certain components, and the proportioned raw materials such as the 12-inch straight pull silicon rods, ar, ammonia water, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water are contained for standby through corresponding vessels.
S2, performing wire cutting processing on the 12-inch straight-pull silicon rod, chamfering after the wire cutting processing is finished, grinding after the chamfering processing is finished, thinning after the grinding, RTP after the thinning, DSP and CMP processing after the RTP.
S3, performing rapid heat treatment and argon annealing treatment through a rapid heat treatment furnace and an argon annealing furnace, controlling the nitrogen content and the oxygen content of the silicon wafer, pulling crystal by adopting a COP FREE technology, regulating and controlling the annealing temperature, the annealing time, the temperature rise and fall rate and the annealing atmosphere of the rapid heat treatment process, optimizing the processing flow, solving the problems of abnormal surface appearance, abnormal particles, higher natural oxide layer and the like of the silicon wafer, and matching corresponding cleaning process before annealing to effectively ensure that the content of Fe element in the silicon wafer is the lowest.
S4, finally, inspecting the surface defects of the silicon wafer through a visual inspection instrument, testing the natural oxide layer on the surface of the silicon wafer through a film thickness tester, testing the content of Fe element in the silicon wafer through a bulk iron tester, testing the BMD and DZ of the silicon wafer through a BMD tester, and testing the surface particles of the silicon wafer through a particle tester, so as to obtain whether the quality requirement of the 12-inch straight-pulling silicon rod is qualified.
In the embodiment, the annealing temperature is 1000-1200 ℃, the annealing time is 5-10s, the heating rate is 30-50 ℃/s, the cooling rate is 80-10 ℃/s, and the annealing atmosphere is pure argon.
In this example, the BMD density is 1-10E9atoms/cm3, the DZ layer is 10-30 μm, the monocrystal adopts nitrogen-doped COP FREE technology, the nitrogen content is controlled to be 1-10E13atoms/cm3, and the oxygen content is controlled to be 5.5-7.5atoms/cm3.
In this example, a 12 inch Czochralski silicon rod must be cleaned with HF acid (HF: H2O=1:150-300), SC1 fluid (NH4.H2O: H2O2: DIW= (0.5-1.0): 3:30), and SC2 fluid (HCL: H2O2: DIW= (1-1.5): 3:30) prior to rapid thermal processing into the chamber.
Embodiment III:
the distinguishing features from the first and second embodiments are that:
the manufacturing process of the present embodiment includes the steps of:
s1, firstly, raw materials such as 12-inch straight pull silicon rods, ar, ammonia water, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water which need to be prepared are proportioned according to certain components, and the proportioned raw materials such as the 12-inch straight pull silicon rods, ar, ammonia water, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water are contained for standby through corresponding vessels.
S2, performing wire cutting processing on the 12-inch straight-pull silicon rod, chamfering after the wire cutting processing is finished, grinding after the chamfering processing is finished, thinning after the grinding, RTP after the thinning, DSP and CMP processing after the RTP.
S3, finally, inspecting the surface defects of the silicon wafer through a visual inspection instrument, testing the natural oxide layer on the surface of the silicon wafer through a film thickness tester, testing the content of Fe element in the silicon wafer through a bulk iron tester, testing the BMD and DZ of the silicon wafer through a BMD tester, and testing the surface particles of the silicon wafer through a particle tester, so as to obtain whether the quality requirement of the 12-inch straight-pulling silicon rod is qualified.
As can be seen from the above experimental results, compared with the processes of the second and third embodiments, the appearance, the natural oxide layer, the BMD and the DZ are similar to those of the 12-inch argon annealed sheet after the processing process of the invention is adopted, but the COP FREE layer depth and Bulk Fe are far better than those of the 12-inch argon annealed sheet, and the phenomenon of slightly higher particles is influenced by the polishing in the present period.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (4)

1. A process for manufacturing a high density BMD shallow DZ layer 12 inch silicon wafer, characterized by: the manufacturing process comprises the following steps:
s1, firstly, raw materials such as a 12-inch straight pull silicon rod, ar, ammonia, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water which need to be prepared are proportioned according to certain components, and the proportioned raw materials such as the 12-inch straight pull silicon rod, ar, ammonia, hydrochloric acid, hydrogen peroxide, hydrofluoric acid and deionized water are contained for standby through corresponding vessels;
s2, performing wire cutting processing on the 12-inch straight-pull silicon rod, chamfering after the wire cutting processing is finished, grinding after the chamfering processing is finished, thinning after the grinding processing, RTP after the thinning, DSP after the RTP processing and CMP processing;
s3, performing rapid heat treatment and argon annealing treatment through a rapid heat treatment furnace and an argon annealing furnace, controlling the nitrogen content and the oxygen content of the silicon wafer, pulling crystal, adopting a COP FREE technology, regulating and controlling the annealing temperature, the annealing time, the temperature rise and fall rate and the annealing atmosphere of the rapid heat treatment process, optimizing the processing flow to solve the problems of abnormal surface appearance, abnormal particles, higher natural oxide layer and the like of the silicon wafer, and matching corresponding cleaning process before annealing to effectively ensure that the content of Fe element in the silicon wafer is the lowest;
s4, finally, inspecting the surface defects of the silicon wafer through a visual inspection instrument, testing the natural oxide layer on the surface of the silicon wafer through a film thickness tester, testing the content of Fe element in the silicon wafer through a bulk iron tester, testing the BMD and DZ of the silicon wafer through a BMD tester, and testing the surface particles of the silicon wafer through a particle tester, so as to obtain whether the quality requirement of the 12-inch straight-pulling silicon rod is qualified.
2. The process for manufacturing a high-density BMD shallow DZ layer 12 inch silicon wafer according to claim 1, wherein: the annealing temperature is 1280-1300 ℃, the annealing time is 10-30s, the heating rate is 50-80 ℃/s, the cooling rate is 80-10 ℃/s, and the annealing atmosphere is pure argon.
3. The process for manufacturing a high-density BMD shallow DZ layer 12 inch silicon wafer according to claim 1, wherein: the BMD density is 1-10E9atoms/cm3, the DZ layer is 10-30 mu m, the monocrystal adopts nitrogen-doped COP FREE technology, the nitrogen content is controlled to be 1-10E13atoms/cm3, and the oxygen content is controlled to be 5.5-7.5atoms/cm3.
4. The process for manufacturing a high-density BMD shallow DZ layer 12 inch silicon wafer according to claim 1, wherein: the 12-inch Czochralski silicon rod must be cleaned with HF acid (HF: H2O=1:150-300), SC1 fluid (NH4.H2O: H2O2: DIW= (0.5-1.0): 3:30), and SC2 fluid (HCL: H2O2: DIW= (1-1.5): 3:30) before being subjected to rapid thermal treatment.
CN202310094524.0A 2023-02-06 2023-02-06 Process for manufacturing high-density BMD shallow DZ layer 12-inch silicon wafer Pending CN116230498A (en)

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Publication number Priority date Publication date Assignee Title
KR20030033187A (en) * 2001-10-18 2003-05-01 주식회사 실트론 Method of fabricating an epitexial wafer for semiconductor
US20090061140A1 (en) * 2005-03-28 2009-03-05 Sumco Techxiv Kabushiki Kaisha Silicon Single Crystal Producing Method, Annealed Wafer, and Method of Producing Annealed Wafer
CN113130295A (en) * 2021-03-08 2021-07-16 中环领先半导体材料有限公司 Cleaning process for solving particle agglomeration after silicon wafer cleaning
CN114737251A (en) * 2022-04-08 2022-07-12 中环领先半导体材料有限公司 Method for obtaining optimal pulling speed of silicon single crystal to prepare high BMD density 12-inch epitaxial wafer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030033187A (en) * 2001-10-18 2003-05-01 주식회사 실트론 Method of fabricating an epitexial wafer for semiconductor
US20090061140A1 (en) * 2005-03-28 2009-03-05 Sumco Techxiv Kabushiki Kaisha Silicon Single Crystal Producing Method, Annealed Wafer, and Method of Producing Annealed Wafer
CN113130295A (en) * 2021-03-08 2021-07-16 中环领先半导体材料有限公司 Cleaning process for solving particle agglomeration after silicon wafer cleaning
CN114737251A (en) * 2022-04-08 2022-07-12 中环领先半导体材料有限公司 Method for obtaining optimal pulling speed of silicon single crystal to prepare high BMD density 12-inch epitaxial wafer

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