CN116209253B - Memory unit, dynamic memory, reading method thereof and electronic equipment - Google Patents

Memory unit, dynamic memory, reading method thereof and electronic equipment Download PDF

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Publication number
CN116209253B
CN116209253B CN202211167720.8A CN202211167720A CN116209253B CN 116209253 B CN116209253 B CN 116209253B CN 202211167720 A CN202211167720 A CN 202211167720A CN 116209253 B CN116209253 B CN 116209253B
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memory
transistor
read
electrically connected
word line
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CN116209253A (en
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朱正勇
康卜文
李辉辉
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The embodiment of the application provides a storage unit, a dynamic memory and electronic equipment. The memory cell includes a memory transistor, a write transistor, and a read transistor; the memory transistor includes a main gate electrically connected to the main word line, a first pole electrically connected to the bit line, a second pole electrically connected to the read node, and a back gate electrically connected to the memory node; the write transistor includes a gate electrically connected to the write word line, a first pole electrically connected to the read node, and a second pole electrically connected to the storage node; the read transistor includes a gate electrically connected to the read word line, a first pole electrically connected to the reference signal terminal, and a second pole electrically connected to the read node. The circuit design of the memory cell provided by the embodiment can avoid crosstalk with the adjacent memory cell, so that the reliability of data reading is improved.

Description

Memory unit, dynamic memory, reading method thereof and electronic equipment
Technical Field
The present application relates to the field of storage technologies, and in particular, to a storage unit, a dynamic memory, a reading method thereof, and an electronic device.
Background
The dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory, and has the advantages of simpler structure, lower manufacturing cost and higher capacity density compared with the static memory.
DRAM memory typically includes a plurality of memory cells, which may take a variety of configurations, wherein 2T0C is one of the common memory cell configurations, but during reading, crosstalk occurs between memory cells of adjacent 2T0C configurations, which risks causing read errors.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides a memory unit, a dynamic memory, a reading method thereof and electronic equipment, and can effectively solve the problem of misreading caused by crosstalk between adjacent memory units.
In a first aspect, embodiments of the present application provide a memory cell, including:
a memory transistor comprising: a main gate electrically connected to the main word line, a first pole electrically connected to the bit line, a second pole electrically connected to the read node, and a back gate electrically connected to the storage node;
a write transistor, comprising: a gate electrically connected to a write word line, a first pole electrically connected to the read node, and a second pole electrically connected to the storage node;
a read transistor including a gate electrically connected to the read word line, a first pole electrically connected to the reference signal terminal, and a second pole electrically connected to the read node.
Optionally, the master word line is multiplexed as the write word line.
Optionally, the reference signal is grounded or electrically connected to a negative voltage terminal of the power supply.
Optionally, the off current of the write transistor is less than the off current of the storage transistor, and the off current of the write transistor is less than the off current of the read transistor.
In a second aspect, embodiments of the present application provide a dynamic memory, where the dynamic memory includes a plurality of memory cells as described above.
Optionally, the plurality of memory cells are arranged in an array of m rows and n columns, and the dynamic memory further includes:
m main word lines extending along a first direction, wherein main gates of the memory transistors in the memory cells in the same row are electrically connected with the same main word line;
m write word lines extending along the first direction, wherein the gates of the write transistors in the memory cells in the same row are electrically connected with the same write word line;
m read word lines extending along the first direction, wherein the gates of the read transistors in the memory cells in the same row are electrically connected with the same read word line; and
n bit lines extending along a second direction, wherein a first pole of the memory transistor in each memory cell in the same column is electrically connected with the same bit line, and the second direction is perpendicular to the first direction.
Optionally, the plurality of memory cells are arranged in an array of m rows and n columns, and the dynamic memory further includes:
m main word lines extending in a first direction, main gates of the memory transistors in the memory cells in the same row being electrically connected to the same main word line, and gates of the write transistors in the memory cells in the same row being electrically connected to the same main word line;
m read word lines extending along the first direction, wherein the gates of the read transistors in the memory cells in the same row are electrically connected with the same read word line; and
n bit lines extending along a second direction, wherein a first pole of the memory transistor in each memory cell in the same column is electrically connected with the same bit line, and the second direction is perpendicular to the first direction.
Optionally, the dynamic memory further includes a read-write circuit configured to provide a write signal and a read signal to the memory cell, and each of the bit lines is electrically connected to the read-write circuit.
In a third aspect, embodiments of the present application provide an electronic device that includes the dynamic memory described above.
In a fourth aspect, an embodiment of the present application provides a method for reading and writing a dynamic memory, including:
in a writing state, applying a first level to a main gate of a memory transistor in a memory cell to be written through a main word line to enable the memory transistor to be turned on, applying a second level to a gate of a writing transistor in the memory cell to be written through a writing word line to enable the writing transistor to be turned on, and inputting a third level to a reading transistor in the memory cell to be written through a reading word line to enable the reading transistor to be turned off, so that a memory signal input by a corresponding bit line is written into the memory cell to be written as memory data;
in a reading state, a fourth level is input to the gate electrode of a reading transistor of a memory cell to be read through a reading word line, so that the reading transistor is conducted, the reference level input by a reference signal end is transmitted to a reading node, a fifth level is input to the gate electrode of a writing transistor of the memory cell to be read through a writing word line, so that the writing transistor is not conducted, a sixth level is written to the main gate electrode of the memory transistor to be read through a main word line, the state of the memory transistor in the memory cell to be read with stored data of '1' is conducted, the electric signal of the reading node is acquired by a bit line, and the electric signal of the reading node cannot be acquired by the bit line due to the fact that the memory transistor in the memory cell to be read with stored data of '0' is not conducted. .
The beneficial technical effects that technical scheme that this application embodiment provided brought include:
1) According to the memory unit, the dynamic memory and the electronic equipment, which are provided by the embodiment of the application, the memory capacitor does not need to be manufactured, so that the space occupied by the memory unit can be effectively controlled, and the integration density of the dynamic memory is improved; the writing transistor adopts a metal oxide transistor, and the storage transistor and the reading transistor are both silicon-based transistors, so that the leakage current of the writing transistor is smaller, the data of a storage node can be effectively maintained, the refresh frequency of the dynamic memory is reduced, the metal oxide transistor only needs to be manufactured on the silicon substrate, the area of the silicon substrate is not increased, and the cost control is facilitated;
2) According to the memory cell, the dynamic memory and the electronic device, when the main word line is multiplexed into the writing word line, wiring in the dynamic memory can be reduced, and the density of the dynamic memory is improved.
3) According to the read-write method of the dynamic memory, based on the circuit design and the wiring design of the memory cells, in the reading process, specific voltages are required to be input to the gates of the memory transistors in the memory cells in the corresponding rows through the corresponding read word lines, so that the memory transistors in the memory cells in the corresponding rows are conducted, the memory transistors in the memory cells in the adjacent rows are not conducted when the specific voltages are not input to the read word lines of the adjacent rows, and therefore the crosstalk problem between the adjacent memory cells is not caused in the reading process, and the error reading phenomenon is avoided.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a circuit diagram of a memory cell of the prior art;
FIG. 2 is a circuit diagram of a dynamic memory according to the prior art;
fig. 3 is a circuit diagram of a memory cell according to an embodiment of the present application;
FIG. 4 is a circuit diagram of another memory cell according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a dynamic memory according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of another dynamic memory according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a frame structure of an electronic device according to an embodiment of the present application;
FIG. 8 is a flowchart illustrating a method for reading a dynamic memory according to an embodiment of the present disclosure;
fig. 9 is a graph showing transfer characteristics of memory transistors in a dynamic memory when different data are written.
Reference numerals:
10-a memory cell; a CT-memory transistor; WT-write transistor; an RT-read transistor; n1-a read node; n2-storage nodes;
WL-main word line; W_WL-write word line; R_WL-read word line; BL-bit lines; vref—reference terminal;
20-read-write circuit.
Detailed Description
Embodiments of the present application are described below with reference to the drawings in the present application. It should be understood that the embodiments described below with reference to the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and the technical solutions of the embodiments of the present application are not limited.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, information, data, steps, operations, elements, components, and/or groups thereof, etc. that may be implemented as desired in the art. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein refers to at least one of the items defined by the term, e.g., "a and/or B" may be implemented as "a", or as "B", or as "a and B".
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The DRAM is a semiconductor memory, and has the advantages of simpler structure, lower manufacturing cost and higher capacity density compared with the static memory. DRAM memory typically includes a plurality of memory cells, which may take a variety of configurations, with 2T0C being one of the common memory cell configurations.
As shown in fig. 1, the memory cell of 2T0C includes a write transistor and a read transistor, the gate of the write transistor is electrically connected to the write word line, the first pole of the write transistor is electrically connected to the write bit line, and the second pole of the write transistor is electrically connected to the storage node; the gate of the read transistor is electrically connected to the storage node, the first pole of the read transistor is electrically connected to the read bit line, and the second pole of the read transistor is electrically connected to the read word line.
Specifically, as shown in fig. 2, the dynamic memory includes a plurality of memory cells, a plurality of write word lines extending in a first direction, a plurality of read word lines extending in a first direction, a plurality of write bit lines extending in a second direction, and a plurality of read bit lines extending in the second direction, wherein the first direction is perpendicular to the second direction. The write word lines and the read word lines are alternately arranged in the first direction, and the write bit lines and the read bit lines are alternately arranged in the second direction.
As shown in fig. 2, it is assumed that the memory state of the memory cells of the first row and the first column is "1", the memory state of the memory cells of the first row and the second column is "0", the memory state of the memory cells of the second row and the first column is "1", and the memory state of the memory cells of the second row and the second column is "1". Based on the above assumption, when the first row memory cells are read in the normal read state, the read bit line r_bl2 should not have an electrical signal and the memory state of the first row and second column memory cells is judged to be "0" based on the absence of the electrical signal of the read bit line r_bl2.
However, because crosstalk may occur between adjacent memory cells, a misreading phenomenon occurs, and based on the assumption, data in each memory cell in the first row is read, which specifically includes the following steps:
the read word line r_wl1 inputs a specific voltage, and the potential of the storage node in the first row and first column storage units turns on the read transistor RT in the first row and first column storage units, thereby causing the read bit line r_bl1 to sense an electrical signal;
the potential that the read bit line r_bl1 has as a result of sensing an electrical signal may turn on the read transistor in the memory cell of the first column of the second row, thereby causing an electrical signal to be present on the read word line r_wl2;
the potential on the read word line r_wl2 due to the presence of the electrical signal may turn on the read transistor in the second row and second column memory cells, thereby causing the electrical signal on the read bit line r_bl2.
The presence of the electrical signal on the read bit line r_bl2 determines that the memory state of the first row and second column memory cells is "1", which is different from the actual memory state of the first row and second column memory cells, that is, a misread occurs.
The application provides a storage unit, a dynamic memory and electronic equipment, and aims to solve the technical problems in the prior art.
The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments. It should be noted that the following embodiments may be referred to, or combined with each other, and the description will not be repeated for the same terms, similar features, similar implementation steps, and the like in different embodiments.
The embodiment of the present application provides a memory cell, and fig. 3 shows a circuit configuration diagram of a memory cell 10 in the embodiment of the present application. As shown in fig. 3, the memory cell 10 provided in this embodiment includes a memory transistor CT, a write transistor WT, and a read transistor RT.
The memory transistor CT includes a main gate electrically connected to the main word line WL, a first pole electrically connected to the bit line BL, a second pole electrically connected to the read node N1, and a back gate electrically connected to the memory node N2; the write transistor WT includes a gate electrically connected to the write word line w_wl, a first pole electrically connected to the read node N1, and a second pole electrically connected to the storage node N2; the read transistor RT includes a gate electrically connected to the read word line r_wl, a first pole electrically connected to the reference signal terminal, and a second pole electrically connected to the read node N1.
Specifically, as shown in fig. 3, in the memory cell 10 provided in this embodiment, the reference signal is grounded. In this application, "ground" refers to "logical ground" in the dynamic memory. Alternatively, the reference signal terminal may be electrically connected to the negative voltage terminal of the power supply. I.e. with a ground level or a voltage negative voltage VSS as a reference signal.
Specifically, as shown in fig. 3, in the memory cell 10 provided in the present embodiment, the off current of the writing transistor WT is smaller than the off current of the memory transistor CT, and the off current of the writing transistor WT is smaller than the off current of the reading transistor RT. Specifically, the writing transistor WT is a metal oxide transistor, and the storage transistor CT and the reading transistor RT are silicon-based transistors. Because the metal oxide transistor has smaller turn-off current, the leakage of the charge of the storage node N2 can be effectively slowed down, so that the electric potential of the storage node N2 can be maintained for a longer time, and the refresh frequency of the dynamic memory can be reduced.
In this embodiment, the material of the metal oxide used for the memory transistor CT may be indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A) Thereby ensuring the working performance of the dynamic memory. The metal oxide material may be ITO, IWO, znO x 、InO x 、In 2 O 3 、InWO、SnO 2 、TiO x 、InSnO x 、Zn x O y N z 、Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a 、Hf x In y Zn z O a 、Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a 、Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a And the materials such as InGaSiO and the like can ensure that the leakage current of the transistor can meet the requirements, and can be specifically adjusted according to actual conditions.
Fig. 4 shows a circuit configuration diagram of a memory cell 10 in an embodiment of the present application. As shown in fig. 4, in the memory cell 10, the main word line WL is multiplexed as the write word line w_wl, and at this time, the wiring in the dynamic memory can be reduced, and the density of the dynamic memory can be improved.
The memory cell 10 provided in this embodiment does not need to manufacture a storage capacitor, so that the space occupied by the memory cell 10 can be effectively controlled, thereby improving the integration density of the dynamic memory; the writing transistor WT adopts a metal oxide transistor, and the storage transistor CT and the reading transistor RT are silicon-based transistors, so that the leakage current of the writing transistor WT is smaller, the data of the storage node N2 can be effectively kept, the refreshing frequency of the dynamic memory is reduced, the metal oxide transistor only needs to be manufactured on silicon, the area of the silicon is not increased, and the cost control is facilitated.
Based on the same inventive concept, the embodiments of the present application further provide a dynamic memory, where the dynamic memory includes the memory unit in any one of the foregoing embodiments, and has the beneficial effects of the memory unit in the foregoing embodiments, which are not described herein again.
Fig. 5 shows a schematic circuit diagram of a dynamic memory in an embodiment of the application. As shown in fig. 5, in the dynamic memory provided in this embodiment, a plurality of memory cells 10 are arranged in an array of m rows and n columns, and the dynamic memory further includes:
m main word lines WL extending in the first direction X, the main gates of the memory transistors CT in each memory cell 10 in the same row being electrically connected to the same main word line WL;
m write word lines w_wl extending in the first direction X, and the gates of the write transistors WT in each memory cell 10 in the same row are electrically connected to the same write word line w_wl;
m read word lines r_wl extending in the first direction X, and the gates of the read transistors RT in each memory cell 10 in the same row are electrically connected to the same read word line r_wl; and
n bit lines BL extending in a second direction Y, which is perpendicular to the first direction X, are electrically connected to the same bit line BL at a first pole of a memory transistor CT in each memory cell 10 in the same column.
In the dynamic memory provided in this embodiment, during writing, for example, data is written into the memory cells 10 in the first row, the first level V1 needs to be provided to the first row main word line WL1 to turn on the memory transistor CT in each memory cell 10 in the first row, the second level V2 is provided to the first row write word line w_wl1 to turn on the write transistor WT in each memory cell 10 in the first row, and the third level V3 is provided to the first row read word line r_wl1 to turn off the read transistor RT in each memory cell 10 in the first row, at this time, the data signal transmitted through each column bit line BL1 to BLn is written into the memory node N2 in each memory cell 10 in the first row as the stored data, wherein the potential of the memory node N2 is different when the stored data is "0" and the stored data is "1". Similarly, when writing data into the memory cells 10 of the corresponding row, the data writing can be realized by providing the corresponding level in the above manner.
In the dynamic memory provided in this embodiment, in the reading process, for example, the data stored in each memory cell 10 in the first row is read, the fourth level V4 needs to be input to the read word line r_wl1 of the first row to turn on the read transistor RT in each memory cell 10 in the first row, so that the reference level is written into the read node N1; inputting a fifth level V5 to the write word line w_wl1 of the first row to make the write transistor WT non-conductive, thereby ensuring that the potential of the storage node N2 is maintained; inputting a sixth level V6 to the main word line WL1 of the first row, and if the stored data in the memory cell 10 is "0", the memory transistor CT is turned off, so that the bit line BL cannot acquire an electrical signal; if the stored data in the memory cell 10 is "1", the memory transistor CT is turned on, thereby allowing the bit line BL to acquire an electrical signal. Whether the storage state of the corresponding memory cell 10 is "1" or "0" can be judged based on whether the bit line BL can acquire an electric signal, thereby completing data reading.
Fig. 6 shows a circuit schematic of another dynamic memory in an embodiment of the application. As shown in fig. 6, in the dynamic memory provided in this embodiment, a plurality of memory cells 10 are arranged in an array of m rows and n columns, and the dynamic memory further includes:
m main word lines WL extending in the first direction X, the main gates of the memory transistors CT in each memory cell 10 in the same row being electrically connected to the same main word line WL, and the gates of the write transistors WT in each memory cell 10 in the same row being electrically connected to the same main word line WL;
m read word lines r_wl extending in the first direction X, and the gates of the read transistors RT in each memory cell 10 in the same row are electrically connected to the same read word line r_wl; and
n bit lines BL extending in a second direction Y, which is perpendicular to the first direction X, are electrically connected to the same bit line BL at a first pole of a memory transistor CT in each memory cell 10 in the same column.
In the dynamic memory provided in this embodiment, in the writing process, for example, when writing data into the memory cells 10 in the first row, it is necessary to provide the first level V1 to the first row main word line WL1 so that the memory transistor CT and the writing transistor WT in each memory cell 10 in the first row are turned on, and provide the third level V3 to the first row read word line r_wl1 so that the reading transistor RT in each memory cell 10 in the first row is turned off, at this time, the data signal transmitted through each column bit line BL1 to BLn is written into the memory node N2 in each memory cell 10 in the first row as the memory data, wherein the potential of the memory node N2 when the memory data is "0" and the potential when the memory data is "1" are different. Similarly, when writing data into the memory cells 10 of the corresponding row, the data writing can be realized by providing the corresponding level in the above manner.
In the dynamic memory provided in this embodiment, in the reading process, for example, the data stored in each memory cell 10 in the first row is read, the fourth level V4 needs to be input to the read word line r_wl1 of the first row to turn on the read transistor RT in each memory cell 10 in the first row, so that the reference level is written into the read node N1; inputting a sixth level V6 to the main word line WL1 of the first row to make the writing transistor WT non-conductive, thereby ensuring that the potential of the storage node N2 is maintained; meanwhile, the sixth level V6 is also transmitted to the main gate of the storage transistor CT in each storage unit 10 in the first row, and if the storage data in the storage unit 10 is "0", the storage transistor CT is not turned on, so that the bit line BL cannot acquire the electrical signal; if the stored data in the memory cell 10 is "1", the memory transistor CT is turned on, thereby allowing the bit line BL to acquire an electrical signal. Whether the storage state of the corresponding memory cell 10 is "1" or "0" can be judged based on whether the bit line BL can acquire an electric signal, thereby completing data reading.
By designing the threshold voltages Vth of the memory transistor CT and the writing transistor WT, it is possible to realize the sixth level V6 such that the writing transistor WT is not turned on, and the memory transistor CT is turned on when the memory state is "1".
As shown in fig. 5 and 6, the dynamic memory provided in this embodiment further includes a read-write circuit 20, the read-write circuit 20 is configured to provide a write signal and a read signal to the memory cell 10, and each bit line BL is electrically connected to the read-write circuit 20.
Specifically, the write signal includes the first level V1, the second level V2, the third level V3, and the like in the above-described embodiment, and the read signal includes the fourth level V4, the fifth level V5, the sixth level V6, and the like in the above-described embodiment.
In the dynamic memory provided in this embodiment, based on the circuit design of the memory cells 10, the data writing and data reading/writing to each memory cell 10 can be realized by using only one read/write circuit 20, without separately providing a read circuit and a write circuit, and the design burden of the peripheral circuit of the dynamic memory can be reduced.
In the dynamic memory provided in this embodiment, based on the circuit design and the wiring design of the memory cells, in the reading process, a specific voltage needs to be input to the gate of the read transistor in the memory cell in the corresponding row through the corresponding read word line, so that the read transistor in each memory cell in the corresponding row is turned on, and the crosstalk problem between adjacent memory cells does not occur in the reading process, thereby avoiding the occurrence of the misreading phenomenon.
Based on the same inventive concept, the embodiment of the application also provides electronic equipment. Fig. 7 is a schematic diagram of a frame structure of an electronic device in an embodiment of the present application. Referring to fig. 7, the electronic device provided in this embodiment includes the dynamic memory in any of the above embodiments, and has the beneficial effects of the dynamic memory in the above embodiments, which are not described herein again.
Specifically, the electronic device provided in the embodiment may be a computer, a notebook computer, a tablet computer, a smart phone, and the like.
Based on the same inventive concept, the embodiment of the present application further provides a method for reading and writing a dynamic memory, where the method for reading and writing provided in the embodiment is used for reading and writing the dynamic memory in any one of the above embodiments. Fig. 8 is a flowchart illustrating a method for reading a dynamic memory according to an embodiment of the application. Referring to fig. 5, 6 and 8, the read-write method provided in the present embodiment includes:
s1: in the writing state, a first level V1 is applied to the main gate of the memory transistor CT in the memory cell 10 to be written through the main word line WL to turn on the memory transistor CT, a second level V2 is applied to the gate of the writing transistor WT in the memory cell 10 to be written through the writing word line w_wl to turn on the writing transistor WT, and a third level V3 is input to the reading transistor RT in the memory cell 10 to be written through the reading word line r_wl to turn off the reading transistor RT, so that a memory signal input by the corresponding bit line BL is written to the memory cell 10 to be written as memory data.
Specifically, referring to the dynamic memory shown in fig. 5, in the writing state, for example, when writing data into the i-th row memory cells 10, it is necessary to provide the i-th row main word line WLi with the first level V1 to turn on the memory transistor CT in the i-th row memory cells 10, the i-th row writing word line w_wli with the second level V2 to turn on the writing transistor WT in the i-th row memory cells 10, and the i-th row reading word line r_wli with the third level V3 to turn off the reading transistor RT in the i-th row memory cells 10, and at this time, the data signal transmitted through the column bit lines BL1 to BLn is written into the storage node N2 in the i-th row memory cells 10 as the stored data, wherein the storage node N2 has a different potential when the stored data is "0" and the stored data is "1". I is an integer of 1 or more and m or less.
Specifically, referring to the dynamic memory shown in fig. 6, in the writing state, for example, when writing data into the i-th row of memory cells 10, it is necessary to provide the i-th row main word line WLi with the first level V1 so that the memory transistor CT and the writing transistor WT in each of the i-th row of memory cells 10 are turned on, and provide the i-th row read word line r_wli with the third level V3 so that the reading transistor RT in each of the i-th row of memory cells 10 is turned off, the data signal transmitted through each of the column bit lines BL1 to BLn is written into the memory node N2 in each of the i-th row of memory cells 10 as the stored data, wherein the memory node N2 has different potentials when the stored data is "0" and the stored data is "1". Similarly, when writing data into the memory cells 10 of the corresponding row, the data writing can be realized by providing the corresponding level in the above manner. I is an integer of 1 or more and m or less.
In the dynamic memory shown in fig. 6, since the main word line WL is multiplexed as the write word line w_wl, the first level V1, which can be regarded as the input main word line WL at this time, is equal to the second level V2 of the input write word line w_wl (multiplexed by the main word line WL).
S2: in the read state, the fourth level V4 is input to the gate of the read transistor RT of the memory cell 10 to be read through the read word line r_wl to turn on the read transistor RT so that the reference level input at the reference signal terminal is transmitted to the read node N1, the fifth level V5 is input to the gate of the write transistor WT of the memory cell 10 to be read through the write word line w_wl to turn off the write transistor WT, and the sixth level V6 is written to the main gate of the memory transistor CT to be read through the main word line WL so that the memory transistor CT in the memory cell 10 to be read with the memory data of "1" is turned on to enable the bit line BL to acquire the electrical signal of the read node N1, and the memory transistor CT in the memory cell 10 to be read with the memory data of "0" is turned off to disable the bit line BL to acquire the electrical signal of the read node N1.
Specifically, referring to the transfer characteristic diagram of the memory transistor CT in the dynamic memory when writing different data shown in fig. 9, for the memory transistor CT, due to the effect of the back gate effect, when the memory data in the memory cell 10 is "0", the potential of the memory node N2 (i.e. the back gate of the memory transistor CT) makes the memory transistor CT be in the first state, when the memory data in the memory cell 10 is "1", the potential of the memory node N2 (i.e. the back gate of the memory transistor CT) makes the memory transistor CT be in the second state, and the characteristic curves of the memory transistor CT in the first state and the second state are different.
As shown in fig. 9, when the gate-source voltage difference of the memory transistor is V GS When' the memory transistor CT in the first state (i.e. "0" state) is not conductive, while the memory transistor CT in the second state (i.e. "1" state) is conductive. In the read state, the main gate potential of the memory transistor CT is the sixth level V6, and the source potential of the memory transistor CT is the potential of the read node N1, i.e., the reference level Vref. I.e. V6-vref=v GS In this case, it is possible to satisfy that the memory transistor CT is turned on and the bit line BL cannot acquire an electric signal when the memory state of the memory cell 10 is "0" in the read process, but the memory transistor CT is turned on and the bit line BL can acquire an electric signal when the memory state of the memory cell 10 is "1".
Specifically, referring to the dynamic memory shown in fig. 5, in the reading process, for example, the data stored in each memory cell 10 in the ith row is read, the fourth level V4 needs to be input to the read word line r_wli of the ith row to turn on the read transistor RT in each memory cell 10 in the ith row, so that the reference level is written into the read node N1; inputting a fifth level V5 to the write word line w_wli of the i-th row to make the write transistor WT non-conductive, thereby ensuring that the potential of the storage node N2 is maintained; inputting a sixth level V6 to the main word line WLi of the ith row, and if the stored data in the memory cell 10 is 0, the memory transistor CT is not conducted so that the bit line BL cannot acquire an electric signal; if the stored data in the memory cell 10 is "1", the memory transistor CT is turned on to enable the bit line BL to acquire an electrical signal. Whether the storage state of the corresponding memory cell 10 is "1" or "0" can be judged based on whether the bit line BL can acquire an electric signal, thereby completing data reading.
Specifically, referring to the dynamic memory shown in fig. 6, in the reading process, for example, reading the data stored in each memory cell 10 in the ith row, the fourth level V4 needs to be input to the read word line r_wli of the ith row to turn on the read transistor RT in each memory cell 10 in the first row, so that the reference level is written into the read node N1; inputting a sixth level V6 to the main word line WLi of the i-th row to make the writing transistor WT non-conductive, thereby ensuring that the potential of the storage node N2 is maintained; meanwhile, the sixth level V6 is also transmitted to the main gate of the storage transistor CT in each memory cell 10 in the ith row, if the stored data in the memory cell 10 is "0", the storage transistor CT is not turned on so that the bit line BL cannot acquire the electrical signal; if the stored data in the memory cell 10 is "1", the memory transistor CT is turned on to enable the bit line BL to acquire an electrical signal. Whether the storage state of the corresponding memory cell 10 is "1" or "0" can be judged based on whether the bit line BL can acquire an electric signal, thereby completing data reading.
In the dynamic memory shown in fig. 6, the threshold voltages Vth of the memory transistor CT and the write transistor WT are designed so that the write transistor WT is not turned on at the sixth level V6, and the memory transistor CT is turned on by shifting the main gate due to the back gate effect when the potential of the memory node N2 is set to "1" in the memory state.
In the dynamic memory shown in fig. 6, since the main word line WL is multiplexed as the write word line w_wl, the sixth level V6, which can be regarded as the input main word line WL at this time, is equal to the fifth level V5 of the input write word line w_wl (multiplexed by the main word line WL).
According to the method for reading the dynamic memory, based on the circuit design of the memory cell 10, the bit line BL can not acquire the electric signal when the memory state is 0, and can acquire the electric signal when the memory state is 1, so that the data signals read by the bit line BL in the two states of 1 or 0 have huge difference, the noise resistance of the dynamic memory is enhanced, and the influence of signal crosstalk can be effectively solved.
By applying the embodiment of the application, at least the following beneficial effects can be realized:
1) According to the memory unit, the dynamic memory and the electronic equipment, which are provided by the embodiment of the application, the memory capacitor does not need to be manufactured, so that the space occupied by the memory unit can be effectively controlled, and the integration density of the dynamic memory is improved; the writing transistor adopts a metal oxide transistor, and the storage transistor and the reading transistor are both silicon-based transistors, so that the leakage current of the writing transistor is smaller, the data of a storage node can be effectively maintained, the refresh frequency of the dynamic memory is reduced, the metal oxide transistor only needs to be manufactured on the silicon substrate, the area of the silicon substrate is not increased, and the cost control is facilitated;
2) According to the memory cell, the dynamic memory and the electronic device, when the main word line is multiplexed into the writing word line, wiring in the dynamic memory can be reduced, and the density of the dynamic memory is improved.
3) According to the read-write method of the dynamic memory, based on the circuit design and the wiring design of the memory cells, in the reading process, specific voltages are required to be input to the gates of the memory transistors in the memory cells in the corresponding rows through the corresponding read word lines, so that the memory transistors in the memory cells in the corresponding rows are conducted, the memory transistors in the memory cells in the adjacent rows are not conducted when the specific voltages are not input to the read word lines of the adjacent rows, and therefore the crosstalk problem between the adjacent memory cells is not caused in the reading process, and the error reading phenomenon is avoided.
Those of skill in the art will appreciate that the various operations, methods, steps in the flow, actions, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed in this application may be alternated, altered, rearranged, split, combined, or eliminated. Further, steps, measures, schemes in the prior art with various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are based on the exemplary directions or positional relationships shown in the drawings, are for convenience of description or simplifying the description of the embodiments of the present application, and do not indicate or imply that the apparatus or components referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the order in which the steps are performed is not limited to the order indicated by the arrows. In some implementations of embodiments of the present application, the steps in each flow may be performed in other orders as desired, unless explicitly stated herein. Moreover, some or all of the steps in the flowcharts may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of the sub-steps or stages may be executed at the same time, or may be executed at different times, where the execution sequence of the sub-steps or stages may be flexibly configured according to the requirements, which is not limited by the embodiment of the present application.
The foregoing is only a part of the embodiments of the present application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical ideas of the present application are adopted without departing from the technical ideas of the solutions of the present application, and also belong to the protection scope of the embodiments of the present application.

Claims (10)

1. A memory cell, comprising:
a memory transistor comprising: a main gate electrically connected to the main word line, a first pole electrically connected to the bit line, a second pole electrically connected to the read node, and a back gate electrically connected to the storage node;
a write transistor, comprising: a gate electrically connected to a write word line, a first pole electrically connected to the read node, and a second pole electrically connected to the storage node;
a read transistor including a gate electrically connected to the read word line, a first pole electrically connected to the reference signal terminal, and a second pole electrically connected to the read node.
2. The memory cell of claim 1, wherein the master word line is multiplexed as the write word line.
3. The memory cell of claim 1, wherein the reference signal is grounded or electrically connected to a negative voltage terminal of a power supply.
4. The memory cell of claim 1, wherein an off current of the write transistor is less than an off current of the memory transistor and an off current of the write transistor is less than an off current of the read transistor.
5. A dynamic memory comprising a plurality of memory cells according to any one of claims 1-4.
6. The dynamic memory of claim 5, wherein a plurality of said memory cells are arranged in an array of m rows and n columns, said dynamic memory further comprising:
m main word lines extending along a first direction, wherein main gates of the memory transistors in the memory cells in the same row are electrically connected with the same main word line;
m write word lines extending along the first direction, wherein the gates of the write transistors in the memory cells in the same row are electrically connected with the same write word line;
m read word lines extending along the first direction, wherein the gates of the read transistors in the memory cells in the same row are electrically connected with the same read word line; and
n bit lines extending along a second direction, wherein a first pole of the memory transistor in each memory cell in the same column is electrically connected with the same bit line, and the second direction is perpendicular to the first direction.
7. The dynamic memory of claim 5, wherein a plurality of said memory cells are arranged in an array of m rows and n columns, said dynamic memory further comprising:
m main word lines extending in a first direction, main gates of the memory transistors in the memory cells in the same row being electrically connected to the same main word line, and gates of the write transistors in the memory cells in the same row being electrically connected to the same main word line;
m read word lines extending along the first direction, wherein the gates of the read transistors in the memory cells in the same row are electrically connected with the same read word line; and
n bit lines extending along a second direction, wherein a first pole of the memory transistor in each memory cell in the same column is electrically connected with the same bit line, and the second direction is perpendicular to the first direction.
8. The dynamic memory as recited in claim 6 or 7, further comprising:
and a read-write circuit configured to supply a write signal and a read signal to the memory cell, and each of the bit lines is electrically connected to the read-write circuit.
9. An electronic device comprising the dynamic memory of any one of claims 5-8.
10. A method of reading from and writing to a dynamic memory as recited in any of claims 5-8, comprising:
in a writing state, applying a first level to a main gate of a memory transistor in a memory cell to be written through a main word line to enable the memory transistor to be turned on, applying a second level to a gate of a writing transistor in the memory cell to be written through a writing word line to enable the writing transistor to be turned on, and inputting a third level to a reading transistor in the memory cell to be written through a reading word line to enable the reading transistor to be turned off, so that a memory signal input by a corresponding bit line is written into the memory cell to be written as memory data;
in a reading state, a fourth level is input to the gate electrode of a reading transistor of a memory cell to be read through a reading word line, so that the reading transistor is conducted, the reference level input by a reference signal end is transmitted to a reading node, a fifth level is input to the gate electrode of a writing transistor of the memory cell to be read through a writing word line, so that the writing transistor is not conducted, a sixth level is written to the main gate electrode of the memory transistor to be read through a main word line, so that the memory transistor in the memory cell to be read with stored data of '1' is conducted, the electric signal of the reading node is acquired by a bit line, and the memory transistor in the memory cell to be read with stored data of '0' is not conducted, so that the electric signal of the reading node cannot be acquired by the bit line.
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