CN110956993A - Resistance change type memory cell based on resistance voltage division reading - Google Patents
Resistance change type memory cell based on resistance voltage division reading Download PDFInfo
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- CN110956993A CN110956993A CN201911280085.2A CN201911280085A CN110956993A CN 110956993 A CN110956993 A CN 110956993A CN 201911280085 A CN201911280085 A CN 201911280085A CN 110956993 A CN110956993 A CN 110956993A
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- access memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0038—Power supply circuits
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Abstract
The invention discloses a resistive random access memory cell based on resistance voltage division reading, which comprises: a first transistor; one end of the resistance change unit is connected with the drain electrode of the first transistor in series, and a connection point is used as a voltage division point; and a second transistor having a gate connected to the voltage dividing point; the first transistor and the resistance change unit realize resistance voltage division. According to the resistive random access memory unit based on resistance voltage division reading, the resistance voltage division of one transistor and the resistive random access unit is utilized, and the grid electrode of the other transistor is utilized to amplify the voltage change signal of the voltage division point so as to increase the reading window caused by high and low resistance states, so that the misreading caused by the fluctuation of device and process parameters is reduced.
Description
Technical Field
The invention relates to the technical field of circuit structures and storage, in particular to a resistance change type storage unit based on resistance voltage division reading.
Background
In a conventional Resistive Random Access Memory (RRAM), a one-transistor one-resistance cell (1T 1R) structure is generally adopted. When reading operation is carried out, word-lines (WL) of a selected unit are opened, data are read by reading current between a Source Line (SL) and a Bit Line (BL), and a reading window is determined by current change caused by high and low resistance states of the resistive random access memory unit. However, due to the limited resistance value variation range of the device, the resistive random access memory faces the problem of small reading window, and the tolerance of the small reading window to the parameter fluctuation of the device is very limited, which easily causes misreading.
Disclosure of Invention
In view of the above, the present invention provides a resistive random access memory cell based on resistance voltage division reading, so as to at least partially solve the above technical problems.
The invention provides a resistive random access memory cell based on resistance voltage division reading, which comprises:
a first transistor;
one end of the resistance change unit is connected with the drain electrode of the first transistor in series, and a connection point is used as a voltage division point; and
a second transistor having a gate connected to the voltage dividing point;
the first transistor and the resistance change unit realize resistance voltage division.
Wherein, in some embodiments:
a source of the first transistor is connected to a source line, and a gate of the first transistor is connected to a first word line;
the other end of the resistance change unit is connected to a first bit line;
the source of the second transistor is grounded, and the drain of the second transistor is connected to a second bit line;
further, the source line is grounded, the first word line is connected to a voltage, and the first bit line and the second bit line are respectively connected to a reading voltage.
In some embodiments, the resistive type memory cell further comprises:
and an Nth transistor connected in series with the (N-1) th transistor, wherein N is an integer greater than 2.
In some embodiments, the source of the Nth transistor is connected to the drain of the N-1 th transistor, the drain of the Nth transistor is connected to the second bit line, and the gate of the Nth transistor is connected to the second word line;
further, the second word line is connected to a voltage.
The resistive random access memory cell based on resistance voltage division reading provided by the invention has the following beneficial effects:
(1) according to the resistance-variable memory, the resistance voltage division of one transistor and the resistance-variable unit is utilized, the voltage change signal of a voltage division point is amplified by utilizing the grid electrode of the other transistor to increase the reading window caused by a high-low resistance state, the reading window of the resistance-variable memory can be effectively increased through a resistance voltage division reading mode, and the misreading caused by the fluctuation of devices and process parameters can be reduced;
(2) by adding the independent reading bit line, the invention avoids the direct reading interference on the resistance change unit, can allow the voltage of the reading wire to change greatly, and reduces the false writing effect caused by the reading interference while increasing the reading window.
Drawings
FIG. 1 is a diagram of the bias states of a conventional 1T1R memory cell and its read operation;
FIG. 2 is a cell current distribution corresponding to a high resistance state and a low resistance state of the memory cell of FIG. 1;
FIG. 3 is a diagram of the first embodiment 2T1R memory cell (vertical RBL) and its bias state during a read operation;
FIG. 4 is a cell current distribution for the high resistance state of the memory cell of FIG. 3 corresponding to the low resistance state;
FIG. 5 is a schematic diagram of a memory array constructed with the 2T1R memory cells of FIG. 3 according to a second embodiment of the present invention;
FIG. 6 is a structural diagram of a memory cell (RBL in horizontal direction) 1R according to a third embodiment of the present invention;
fig. 7 is a structural diagram of a storage unit of a fourth embodiment 3T1R of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
In a conventional resistive random access memory (Resistive Random Access Memory (RRAM), a memory cell composed of a transistor and a resistance change cell (1T 1R) is widely used. The cell structure is shown in fig. 1, wherein 1T (M1) is a gate tube of the cell, and 1r (rram) is a resistance change memory cell. In a read operation, a voltage (V) is applied to a word-line (WL) of a selected cellWL) Grounding (GND) a Source Line (SL), and applying a read voltage (V) to a Bit Line (BL)READ). By reading the memory cell current (CellCurrent, I)CELL) The read window is determined by the current change caused by the High Resistance State (HRS) and the Low Resistance State (LRS) of the resistance change memory cell. As shown in fig. 2, HRS corresponds to a lower cell current; LRS corresponds to a higher cell current. Due to the characteristics of the RRAM device, the current caused by the high and low resistance states is about 7 times.
The invention discloses a resistive random access memory cell based on resistance voltage division reading, aiming at solving the problems of small reading window and the like of a 1T1R resistive random access memory, and the first embodiment of the invention discloses a structure of the resistive random access memory cell based on a two-transistor one-resistor 2T1R, wherein the reading window caused by high and low resistance states is increased by dividing the voltage of the resistors of a gate tube (M1) and a Resistive Random Access Memory (RRAM) and amplifying the voltage change signal of a voltage division point by using the grid of another transistor (M2). The structure is shown in fig. 3, and specifically includes:
a first transistor (M1) having a source connected to a Source Line (SL) and a gate connected to a first Word Line (WL);
a resistance change unit (RRAM) having one end connected in series with the drain of the first transistor, a connection point serving as a voltage division point, and the other end connected to a first Bit Line (BL); and
a second transistor (M2), wherein the gate is connected to the voltage division point, the source of the second transistor is grounded, and the drain is connected to a second bit line (RBL);
wherein the first transistor (M1) and the Resistive Random Access Memory (RRAM) implement resistance voltage division.
Further, whereinIs connected to Ground (GND), and the first Word Line (WL) is connected to a voltage (V)WL) The first Bit Line (BL) and the second bit line (RBL) are respectively connected to a read voltage (V)BL、VREAD)。
In this embodiment, during a read operation, a voltage (V) is applied to the word-line (WL) of the selected cellWL) Grounding (GND) a Source Line (SL), and applying a read voltage (V) to a Bit Line (BL)BL) M1 was subjected to voltage division with the RRAM. Applying a read voltage (V) on a read bit-line (RBL)READ) And the other end of M2 is grounded. The current flowing through M2 is defined as the memory cell current (I)CELL). When RRAM is in high resistance state, the voltage of voltage division point is lower, ICELLSmall; when the RRAM is in a low resistance state, the voltage of the voltage division point is higher, ICELLIs large; as shown in fig. 4, HRS corresponds to a lower cell current; LRS corresponds to a higher cell current. Due to the amplification effect of the voltage division type reading, in the case of the adopted RRAM device, the current change caused by the high and low resistance states in the resistive random access memory cell of the 2T1R provided by the embodiment is about 79 times, and compared with the structure of the 1T1R cell, the current change caused by the high and low resistance states is enlarged by about 10 times.
Based on the resistive random access memory cell 2T1R, a second embodiment of the present invention provides a memory array based on the resistive random access memory cell, and the memory cells shown in fig. 3 are arranged in an array, as shown in fig. 5, the memory cells are connected in the lateral direction of the memory array by Word Lines (WL), and are connected in the column direction of the memory array by Source Lines (SL), first Bit Lines (BL), and second bit lines (RBL), so as to finally achieve the purpose of reading and writing data.
The third embodiment of the present invention is shown in fig. 6, which is a 2T1R resistive random access memory cell structure similar to the horizontal direction RBL of fig. 3 (fig. 3 is a 2T1R resistive random access memory cell structure of the vertical direction RBL). It should be noted that the cell structures shown in fig. 6 and fig. 3 are different only in the layout manner of the RBLs, and specifically, the RBLs in fig. 3 are perpendicular to the Word Line (WL), while the RBLs in fig. 6 are parallel to the Word Line (WL), and there is no difference in the arrangement and connection manner of the other elements, and the 2T1R resistive random access memory cell in the horizontal direction RBL shown in fig. 6 can effectively increase the read window of the resistive random access memory and reduce the misreading problem caused by the fluctuation of the device and process parameters by the resistance voltage division reading manner.
In other embodiments, based on the foregoing embodiments, the resistive random access memory cell read by dividing the resistance provided by the present invention may further include:
and an Nth transistor connected in series with the (N-1) th transistor, wherein N is an integer greater than 2.
Further, the source of the Nth transistor is connected to the drain of the N-1 th transistor, the drain of the Nth transistor is connected to the second bit line, the gate of the Nth transistor is connected to a second word line, and the second word line is connected to a voltage.
In view of this, a fourth embodiment of the present invention provides a structure of the resistive random access memory cell based on a three-transistor one-resistive random access cell (3T1R), as shown in fig. 7, in the structure of the resistive random access memory cell of 2T1R (fig. 3 or fig. 6), further comprising:
a third transistor having a source connected to the drain of the second transistor, a drain connected to the second bit line (RBL), a gate connected to a second word line (RWL), and the second word line (RWL) connected to a voltage.
In this embodiment, during a read operation, a voltage (V) is applied to the Word Line (WL) of the selected cellWL) And supplying a voltage (V) to the word line (RWL)RWL) Grounding (GND) the Source Line (SL) and applying a read voltage (V) to the Bit Line (BL)BL) M1 is then divided by the RRAM. Applying a read voltage (V) to a Read Bit Line (RBL)READ) And the other end of M2 is grounded. The current through M2 and M3 is defined as the memory cell current (I)CELL). Due to the amplification effect of voltage division type reading, under the condition of the adopted RRAM device, the current change caused by high and low resistance states in the resistive random access memory cell of the 3T1R provided by the embodiment is basically consistent with the effect of 2T1R, and compared with a 1T1R cell structure, the current change caused by high and low resistance states is also enlarged by about one order of magnitude.
The resistive random access memory cell based on resistance voltage division reading and some embodiments thereof provided by the invention are described so far. The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A resistive random access memory cell based on resistive voltage division reading, comprising:
a first transistor;
one end of the resistance change unit is connected with the drain electrode of the first transistor in series, and a connection point is used as a voltage division point; and
a second transistor having a gate connected to the voltage division point;
the first transistor and the resistive switching unit realize resistance voltage division.
2. The resistive random access memory cell according to claim 1, wherein the other end of the resistive random access memory cell is connected to a first bit line.
3. The resistive random access memory cell of claim 2, wherein the drain of the second transistor is coupled to a second bit line.
4. A resistive random access memory cell according to claim 1, 2 or 3 wherein the source of the second transistor is connected to ground.
5. The resistive random access memory cell of claim 4, wherein the source of the first transistor is connected to a source line and the gate of the first transistor is connected to a first word line.
6. The resistive random access memory cell of claim 5, wherein the source line is coupled to ground, the first word line is coupled to a voltage, and the first bit line and the second bit line are each coupled to a read voltage.
7. The resistive memory cell of claim 6, further comprising:
an Nth transistor connected in series with the Nth-1 transistor, wherein N is an integer greater than 2.
8. The resistive random access memory cell of claim 7, wherein the source of the Nth transistor is connected to the drain of the N-1 th transistor, and the drain of the Nth transistor is connected to the second bit line.
9. The resistive random access memory cell of claim 8, wherein the gate of the nth transistor is connected to a second word line.
10. The resistive random access memory cell of claim 9, wherein the second word line is connected to a voltage.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021083356A1 (en) * | 2019-11-01 | 2021-05-06 | 华为技术有限公司 | Storage and computation unit and chip |
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Application publication date: 20200403 |