CN106158000A - Spin transfer torque magnetic memory cell and memorizer - Google Patents
Spin transfer torque magnetic memory cell and memorizer Download PDFInfo
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- CN106158000A CN106158000A CN201510160721.3A CN201510160721A CN106158000A CN 106158000 A CN106158000 A CN 106158000A CN 201510160721 A CN201510160721 A CN 201510160721A CN 106158000 A CN106158000 A CN 106158000A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- Mram Or Spin Memory Techniques (AREA)
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Abstract
The embodiment of the present invention provides a kind of spin transfer torque magnetic memory cell and memorizer, and this memory cell includes: the first source electrode line, the second source electrode line, bit line, wordline, and the first transistor, transistor seconds and MTJ MTJ；The grid of the first transistor is connected with wordline, and the source electrode of the first transistor and the first source electrode line connect；The drain electrode of the first transistor is connected with one end of MTJ, and the other end of MTJ is connected with bit line；The source electrode of transistor seconds and the second source electrode line connect, and the grid of transistor seconds, drain electrode are connected with the drain electrode of the first transistor respectively.By the difference according to MTJ work resistance state, control the first transistor and the change of transistor seconds ON-OFF state, so that during different write resistance state, the first transistor is different with transistor seconds ON-OFF state, realize the difference to MTJ reset current to control, avoid the waste of electricity, improve the dependability of MTJ.
Description
Technical field
The invention belongs to memory technology field, be specifically related to a kind of spin transfer torque magnetic memory list
Unit and memorizer.
Background technology
Along with integrated circuit technique is to the development in low-power consumption direction and the information age place to mass data storage
The requirement of reason improves day by day, and storage system is towards high density, Large Copacity, high reliability and low-power consumption direction
Development.
Traditional volatile storage such as SRAM (Static Random Access
Memory, is called for short SRAM) or dynamic RAM (Dynamic Random Access
Memory, is called for short DRAM) being required for offer energy, i.e. data when data keep cannot be in power down feelings
Keep under condition, therefore there is higher quiescent dissipation.And nonvolatile memory such as phase transition storage (phase
Change memory, is called for short PCM) resistance-variable storing device (resistive random access memory, letter
Claim RRAM) and magnetic RAM (Magnetic Random Access Memory, abbreviation
Etc. MRAM) novel medium memorizer is due to its storage characteristics: data need not energy, therefore when keeping
Not having quiescent dissipation, this external multilevel storage, massive store and read-write lifting aspect also have to be sent out further
The space of exhibition, entirety has the trend replacing traditional volatile memorizer.Wherein, secondary MRAM, i.e.
Spin transfer torque magnetic memory (Spin Transfer Torque-Magnetic Random Access
Memory, is called for short STT-MRAM) have non-volatile, operating rate is fast, erasable number of times is unrestricted,
Easily increase the advantages such as capacity, obtain broad development and application.
The read-write capability of STT-MRAM is controlled by the memory element of STT-MRAM.At present, typical case
STT-MRAM memory element be by one storage information magnetic tunnel-junction (Magnetic Tunnel
Junction, MTJ) couple with a transistor M and to be constituted, i.e. there is 1T1MTJ structure, such as Fig. 1 institute
Showing, wherein, MTJ junction composition is as shown in Figure 2.This structural top and free layer that bottom is magnetic material and
Fixed layer, centre is the thinnest barrier layer, and the magnetic material free layer direction of magnetization can change, fixed layer
The direction of magnetization is the most immutable, and electric current passes through different directions (by fixed layer to free layer or by free layer
To barrier layer) when flowing through MTJ, the free layer direction of magnetization changes therewith, can with the fixed layer direction of magnetization in
Parastate or antiparallel state, under parastate, MTJ externally presents low resistance state, under antiparallel state
Then present high-impedance state, " 0 " and one state can be stored, therefore by by the direction of MTJ just controlling electric current
Data storage can be realized.
Tradition STT-RAM memory element employing 1T1MTJ structure, but depositing due to STT-RAM itself
Storage characteristic, when writing " 0 " and " 1 ", required reset current is inconsistent.Under standard connects, write
During the i.e. low resistance state of parallel state, the reset current of needs is relatively big, needs during the write i.e. high-impedance state of anti-parallel state
Reset current is less.In the case of not changing peripheral write circuit, at present, 1T1MTJ structure is used
The STT-RAM memory element electric current that MTJ passes through when writing " 0 " with " 1 " is the same, i.e. meets write
Size of current required during low resistance state.Therefore, in the case of needs small area analysis writes, it is actually written into electric current
Excess, the certain infringement also having mtj structure while waste electricity, reduces the reliability of device.
Summary of the invention
For the problem of above-mentioned existence, the embodiment of the present invention provides a kind of spin transfer torque magnetic memory
Unit and memorizer, in order to overcome the damage to memory device of the constant excessive reset current, to improve storage
The reliability of device.
First aspect, embodiments provides a kind of spin transfer torque magnetic memory cell, including:
First source electrode line, the second source electrode line, bit line, wordline, and the first transistor, transistor seconds
With MTJ MTJ；
The grid of described the first transistor is connected with described wordline, the source electrode of described the first transistor and first
Source electrode line connects；The drain electrode of described the first transistor is connected with one end of described MTJ, described MTJ's
The other end is connected with described bit line；
The source electrode of described transistor seconds is connected with described second source electrode line, the grid of described transistor seconds,
The drain electrode of described transistor seconds drain electrode with described the first transistor respectively is connected.
In the first possible implementation of first aspect, described memory cell also includes dividing potential drop electricity
Resistance, described divider resistance is connected between the grid of described transistor seconds and drain electrode.
In the implementation that the second of first aspect is possible, described memory cell is in write low-resistance
During the duty of state, described first source electrode line and the first feeder ear connect, described second source electrode line and the
Two feeder ears connect, and described wordline is connected with the 3rd feeder ear, described bit line；Wherein, described
The output level of one feeder ear, described second feeder ear and described 3rd feeder ear is high level；
Described the first transistor and described transistor seconds are in conducting state, and described the first transistor
Turn on prior to described transistor seconds.
In conjunction with the implementation that the second of first aspect is possible, in the third possible reality of first aspect
In existing mode, when described memory cell is in the duty of write high-impedance state, described first source electrode line
Ground connection, described second source electrode line is unsettled, and described wordline is connected with described 3rd feeder ear, described bit line with
4th feeder ear connects；Wherein, the output level of described 4th feeder ear is high level；
Described the first transistor is in the conduction state, and described transistor seconds is in cut-off state.
In conjunction with the implementation that the second of first aspect is possible, in the 4th kind of possible reality of first aspect
In existing mode, when described memory cell is in the duty of reading, described first source electrode line and the 5th
Feeder ear connects, and described second source electrode line and the 6th feeder ear connect, described wordline and described 3rd power supply
End connects, described bit line；Wherein, the output electricity of described 5th feeder ear and described 6th feeder ear
Average out to high level；
Described the first transistor and described transistor seconds are in conducting state, and described transistor seconds
Work in linear amplification region.
In conjunction with the 4th kind of possible implementation of first aspect, in the 5th kind of possible reality of first aspect
In existing mode, the resistance that described the first transistor is corresponding is the first resistance, and described transistor seconds is corresponding
Resistance is the second resistance, and described second resistance is more than described first resistance.
In conjunction with the 4th kind of possible implementation of first aspect, in the 6th kind of possible reality of first aspect
In existing mode, resistance corresponding for described MTJ includes low resistance state resistance and high-resistance resistors, described low resistance state
Resistance is described MTJ resistance when working in described low resistance state, and described high-resistance resistors is described MTJ
Work in resistance during described high-impedance state；
The dividing potential drop to described 5th feeder ear output level according to described high-resistance resistors and described first resistance
Determine the grid level of described transistor seconds；
The output level of described 6th feeder ear deducts difference between described grid level for more than 0 and close
In the positive number of 0.
In conjunction with the 4th kind of possible implementation of first aspect, in the 7th kind of possible reality of first aspect
In existing mode, the linear gradient of the VA characteristic curve of described transistor seconds is more than 1.
Second aspect, embodiments provides a kind of spin transfer torque magnetic memory, including: extremely
A few spin transfer torque magnetic memory cell as above；
Reading circuit, described reading circuit includes at least one amplifier, at least one amplifier described
Quantity equal with the quantity of described spin transfer torque magnetic memory cell, and each amplifier one a pair
Answer a described spin transfer torque magnetic memory cell；
The positive input terminal of described each amplifier and the institute in corresponding spin transfer torque magnetic memory cell
State the second source electrode line to connect.
The spin transfer torque magnetic memory cell of embodiment of the present invention offer and memorizer, this storage list
Unit includes two i.e. the first transistors of transistor, transistor seconds and a MTJ
MTJ, the source electrode of the two transistor is respectively connecting to the first source electrode line and the second source electrode line, and second
The grid of transistor and drain electrode are both connected on the connecting line between the drain electrode of the first transistor and MTJ,
Realize in ablation process, the difference of reset current being controlled.In the structure of this memory cell, the
One transistor is master control tubulation, and transistor seconds is that subordinate control pipe is controlled by the first transistor, only
When the first transistor is opened, transistor seconds is only possible to open, by according to MTJ work resistance state
Difference, controls the first transistor and the change of transistor seconds ON-OFF state, so that different
During write resistance state, the first transistor is different with transistor seconds ON-OFF state, it is achieved to MTJ
The difference of reset current controls, it is to avoid the waste of electricity, improves the dependability of MTJ.
Accompanying drawing explanation
Fig. 1 is the structural representation of the STT-MRAM of existing ITIMTJ structure；
Fig. 2 is the structural representation of ITIMTJ；
Fig. 3 is the structural representation of spin transfer torque magnetic memory cell embodiment one of the present invention；
Fig. 4 is that duty during spin transfer torque magnetic memory cell of the present invention write low resistance state is shown
It is intended to；
Fig. 5 is that duty during spin transfer torque magnetic memory cell of the present invention write high-impedance state is shown
It is intended to；
Fig. 6 is working state schematic representation during spin transfer torque magnetic memory cell of the present invention reading；
Fig. 7 is the VA characteristic curve figure of transistor seconds；
Fig. 8 is the structural representation of spin transfer torque magnetic memory cell embodiment two of the present invention；
Fig. 9 is the structural representation of spin transfer torque magnetic memory embodiment one of the present invention.
Detailed description of the invention
Fig. 3 is the structural representation of spin transfer torque magnetic memory cell embodiment one of the present invention, such as figure
Shown in 3, this memory element includes:
First source electrode line SL1, the second source electrode line SL2, bit line BL, wordline WL, and first crystal
Pipe M1, transistor seconds M2 and MTJ MTJ；
The grid of described the first transistor M1 is connected with described wordline WL, described the first transistor M1
Source electrode and the first source electrode line SL1 connect；The drain electrode of described the first transistor M1 and the one of described MTJ
End connects, and the other end of described MTJ is connected with described bit line BL；
The source electrode of described transistor seconds M2 is connected with described second source electrode line SL2, described second crystal
The grid of pipe M2, described transistor seconds M2 drain electrode respectively with the drain electrode of described the first transistor M1
Connect.
In the present embodiment, the structure of the STT-MRAM memory element of employing is the structure of 2T1MTJ, increases
If transistor seconds M2 and the second source electrode line SL2, and grid and the drain electrode of M2 are connected to
In connection between M1 and MTJ.Above-mentioned transistor can be MOS transistor.
Wherein, in the present embodiment and following example, will carry out as a example by the mode that MTJ standard connects
The elaboration of this memory element operation principle, during for Opposite direction connection, is similar to therewith, repeats no more.
The mode connected corresponding to MTJ standard, the drain electrode of M1 is MTJ's with one end of the connection of MTJ
Fixed layer end, the free layer end that one end is MTJ that MTJ and bit line BL is connected.
Based on said structure, this STT-MRAM memory element real work when, by above-mentioned
First source electrode line SL1, the second source electrode line SL2, bit line BL, the control of output level of wordline WL,
Control M1 and M2 and be in different on or off states according to the difference of duty, thus
Control reality eventually the difference of MTJ reset current is controlled.
The work of STT-MRAM memory element when the different write state of concrete introduction and the state of reading
Made Cheng Qian, first the several parameters related in the present embodiment were introduced.
In the present embodiment, it is assumed that resistance corresponding for M1 is the first resistance R1, resistance corresponding for M2 is
One resistance R2, the i.e. first and second transistors can have certain resistance value.And assume the electricity of MTJ
Resistance is RX, and wherein, RX includes two kinds of resistances of RH and RL, and RH is in high-impedance state corresponding to MTJ
External resistance during the most anti-flat form, when RL is in the most flat form of low resistance state corresponding to MTJ to extrernal resistance
Value.
Introduce the work process of STT-MRAM memory element below in conjunction with specific embodiments.
Fig. 4 is that duty during spin transfer torque magnetic memory cell of the present invention write low resistance state is shown
It is intended to, as shown in Figure 4, when this STT-MRAM cell is in the duty of write low resistance state,
Described first source electrode line SL1 and the first feeder ear connect VDDw1, described second source electrode line SL2 and the
Two feeder ear VDDw2 connect, and described wordline WL and the 3rd feeder ear VDD connect, described bit line BL
Ground connection VSS.Wherein, described first feeder ear VDDw1, described second feeder ear VDDw2 and institute
The output level stating the 3rd feeder ear VDD is high level.
And, the setting of above-mentioned level makes the first transistor M1 and transistor seconds M2 be in leading
Logical state, and the first transistor M1 is prior to transistor seconds M2 conducting.
Specifically, when writing the i.e. parallel state of low resistance state, reset current from left to right flows through MTJ,
The reset current that MTJ needs is bigger.
During write low resistance state, wordline WL meets high level signal VDD, makes the first transistor M1 open.
First source electrode line SL1 and the second source electrode line SL2 meets write high level signal VDDw1 and VDDw2, its
In, VDDw1 and VDDw2 can be equal or different, bit line BL ground connection VSS.Now, first is brilliant
The series via of body pipe M1 with MTJ fully opens, and the i.e. first source electrode line SL1 is formed logical with bit line BL
Road.VDDw1 through the dividing potential drop of the low resistance state resistance RL of resistance R1 and MTJ of the first transistor M1,
Grid at transistor seconds M2 forms voltage VG2.Set the VG2 threshold more than transistor seconds M2
Threshold voltage VT2, makes M2 open, and now the second source electrode line SL2 and bit line BL forms path.Thus,
The first transistor M1 is integrally formed, two paths of transistor seconds M2 provide reset current for MTJ
State, makes MTJ obtain bigger reset current.
Wherein, in order to ensure that the grid voltage VG2 of above-mentioned transistor seconds M2 is more than transistor seconds
The threshold V T 2 of M2, makes M2 open, can be defeated by reasonably arranging external each feeder ear
The level height entered, or by reasonably arrange the first transistor M1, transistor seconds M2 and
MTJ, makes their resistance value have reasonable disposition relation, is equivalent to the device selecting to meet above-mentioned condition
Part；Or make relatively low etc. the mode of threshold V T 2 that suitable transistor seconds M2 turns it on
Realize.
Fig. 5 is duty signal during spin transfer torque magnetic memory cell of the present invention write high-impedance state
Figure, as it is shown in figure 5, when STT-MRAM cell is in the duty of write high-impedance state, described
First source electrode line SL1 ground connection VSS, described second source electrode line SL2 is unsettled i.e. to be disconnected, described wordline
WL is connected with described 3rd feeder ear VDD, and described bit line BL and the 4th feeder ear VDDw3 is even
Connect；Wherein, the output level of described 4th feeder ear VDDw3 is high level；
By the setting of above-mentioned feeder ear, make the first transistor M1 in the conduction state, the second crystal
Pipe M2 is in cut-off state.
Specifically, when writing the i.e. anti-parallel state of high-impedance state, reset current flows through MTJ from right to left,
The reset current that MTJ needs is less.
During write high-impedance state, wordline WL meets high level signal VDD, makes the first transistor M1 open.
First source electrode line SL1 ground connection VSS, the second source electrode line SL2 disconnect, and bit line BL connects the 4th feeder ear
VDDw3.Now, transistor seconds M2 ends, and is formed by bit line BL through MTJ, first crystal
Pipe M1 eventually arrives at the circuit pathways of the first source electrode line SL1, this path provide less for MTJ
Reset current.
In the present embodiment, this STT-MRAM cell include two i.e. the first transistors of transistor, second
Transistor and a MTJ MTJ, the source electrode of the two transistor is respectively connecting to the first source electrode
Line and the second source electrode line, and the grid of transistor seconds and drain electrode be both connected to the drain electrode of the first transistor with
On connecting line between MTJ, it is achieved in ablation process, the difference of reset current is controlled.At this memorizer
In the structure of unit, the first transistor is master control tubulation, and transistor seconds is that subordinate controls pipe and is controlled by the
One transistor, only when the first transistor is opened, transistor seconds is only possible to open, by according to MTJ
The difference of work resistance state, controls the first transistor and the change of transistor seconds ON-OFF state, thus
When making different write resistance state, the first transistor is different with transistor seconds ON-OFF state, it is achieved right
The difference of MTJ reset current controls, it is to avoid the waste of electricity, improves the dependability of MTJ.
The above-mentioned ablation process to STT-MRAM cell is described, and is explained below
The readout of STT-MRAM memory element.
Fig. 6 is working state schematic representation during spin transfer torque magnetic memory cell of the present invention reading, as
Shown in Fig. 6, when described STT-MRAM cell is in the duty of reading, described first source electrode line
SL1 and the 5th feeder ear VDDr1 connects, described second source electrode line SL2 and the 6th feeder ear VDDr2
Connecting, described wordline WL is connected with described 3rd feeder ear VDD, described bit line BL ground connection VSS；
Wherein, the output level of described 5th feeder ear VDDr1 and described 6th feeder ear VDDr2 is height
Level.
By the control to above-mentioned feeder ear output level, and by the parameter such as device resistance or performance
Reasonable setting so that the first transistor M1 and transistor seconds M2 is in conducting state, and order
Transistor seconds M2 works in linear amplification region.
Specifically, during reading, wordline WL meets high level VDD, makes the first transistor M1 open.
First source electrode line SL1 and the second source electrode line SL2 respectively connect reading high level signal VDDr1 and
VDDr2.The resistance R2 resistance R1 much larger than the first transistor M1 of transistor seconds M2 is set,
The grid voltage making two transistors there are differences.
The grid voltage of transistor seconds M2 is VG2=VDDr1 × RX/ (RX+R1), due to
When VG2 is more than the threshold V T 2 of transistor seconds M2, transistor seconds M2 place path is opened
Open, and source and drain two step voltage of transistor seconds M2 is VDS2=VDDr2-VG2.
Because VG2 is relevant with MTJ resistance RX, when reading high-impedance state, MTJ is in high-impedance state,
RX is RH, and dividing potential drop is relatively big in circuit, and therefore VG2 is bigger；Otherwise, it is in low-resistance at MTJ
During state, RX is RL, and dividing potential drop is less in circuit, then VG2 is less.
Therefore, in the present embodiment, it is in resistance RH during high-impedance state and the first transistor according to MTJ
Resistance R1 the dividing potential drop of the 5th feeder ear output level VDDr1 is determined the grid of transistor seconds M2
Pole level VG2.
Thus, it is slightly larger than or equal to transistor seconds M2 during high-impedance state by arranging VDDr2
VG2, then when reading high-impedance state, VDS2=VDDr2-VG2 is more than or equal to 0 (close to 0),
And when reading low configuration, owing to VG2 is less, then VDS2 is bigger.The most in advance
Set the read-out voltage VDDr2 connect on the second source electrode line SL2, the second crystal when can control to read
Pipe M2 is operated in linear amplification region, thus is amplified the data read, and improves and reads data
Reliability.
It addition, in the present embodiment, arranging transistor seconds M2 is the linear oblique of VA characteristic curve
The rate transistor more than 1.It is that C-V characteristic is linear as shown in Figure 7 by selecting transistor seconds M2
The slope transistor more than 1, is existed by the signal code of transistor seconds M2 when can amplify reading
Difference during high low resistance state.It can be seen from figure 7 that when slope is 1, reading height will not be amplified
The difference window of low signal, as the height produced with tradition 1T1MTJ mode reads, and works as slope
During more than 1, high low resistance state read output signal difference window will be the multiple of slope.In whole readout
Read output signal is transistor seconds M2 place path signal, and the first transistor M1 is assosting effect.
In the present embodiment, different according to MTJ resistance state during reading, thus the grid of transistor seconds M2
Voltage is different, thus the electric current flowing through transistor seconds M2 branch road is different, by making transistor seconds
M2 is in linear amplification region and utilizes its C-V characteristic linear gradient characteristic more than 1, it is achieved high
Differentiate high speed readout.
Fig. 8 is the structural representation of spin transfer torque magnetic memory cell embodiment two of the present invention, as
Shown in Fig. 8, on the basis of embodiment illustrated in fig. 3, this STT-MRAM cell also includes point
Piezoresistance R, described divider resistance R are connected between the grid of described transistor seconds M2 and drain electrode.
Owing to the first transistor M1 is fully on, R1 is the least, therefore at transistor seconds for its resistance
A divider resistance R (can be realized) is added by poly resistance between grid and the drain electrode of M2,
Divider resistance R and MTJ resistance RX dividing potential drop, i.e. divider resistance R is utilized to instead of in Fig. 3 first
The resistance R1 of transistor M1, it is achieved MTJ is transistor seconds M2 drain electrode in the case of different resistance states
Voltage can change, thus changes transistor seconds M2 source-drain voltage, reaches above-mentioned reset current difference
Control, during reading, amplify the purpose of read current signal.
Fig. 9 is the structural representation of spin transfer torque magnetic memory embodiment one of the present invention, such as Fig. 9 institute
Showing, this memorizer includes:
STT-MRAM cell described at least one example performed as described above；
Reading circuit, described reading circuit includes at least one amplifier SA, at least one amplification described
The quantity of device SA is equal with the quantity of described STT-MRAM cell, and each amplifier SA mono-a pair
Answer a described STT-MRAM cell；
The positive input terminal Iread of described each amplifier and described in corresponding STT-MRAM cell
Two source electrode lines connect, and negative input end connects datum Iref.
As it is shown in figure 9, each STT-MRAM cell can laterally cascade, it is also possible to longitudinally cascade constitutes battle array
Array structure.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it,
Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and
The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a spin transfer torque magnetic memory cell, it is characterised in that including:
First source electrode line, the second source electrode line, bit line, wordline, and the first transistor, transistor seconds
With MTJ MTJ；
The grid of described the first transistor is connected with described wordline, the source electrode of described the first transistor and first
Source electrode line connects；The drain electrode of described the first transistor is connected with one end of described MTJ, described MTJ's
The other end is connected with described bit line；
The source electrode of described transistor seconds is connected with described second source electrode line, the grid of described transistor seconds,
The drain electrode of described transistor seconds drain electrode with described the first transistor respectively is connected.
Memory cell the most according to claim 1, it is characterised in that also include divider resistance,
Described divider resistance is connected between the grid of described transistor seconds and drain electrode.
Memory cell the most according to claim 1, it is characterised in that:
When described memory cell is in the duty of write low resistance state, described first source electrode line and first
Feeder ear connects, and described second source electrode line and the second feeder ear connect, and described wordline is with the 3rd feeder ear even
Connect, described bit line；Wherein, described first feeder ear, described second feeder ear and the described 3rd supply
The output level of electricity end is high level；
Described the first transistor and described transistor seconds are in conducting state, and described the first transistor
Turn on prior to described transistor seconds.
Memory cell the most according to claim 3, it is characterised in that:
When described memory cell is in the duty of write high-impedance state, described first source electrode line ground connection,
Described second source electrode line is unsettled, and described wordline is connected with described 3rd feeder ear, and described bit line and the 4th supplies
Electricity end connects；Wherein, the output level of described 4th feeder ear is high level；
Described the first transistor is in the conduction state, and described transistor seconds is in cut-off state.
Memory cell the most according to claim 3, it is characterised in that:
When described memory cell is in the duty of reading, described first source electrode line and the 5th feeder ear
Connecting, described second source electrode line and the 6th feeder ear connect, and described wordline is connected with described 3rd feeder ear,
Described bit line；Wherein, the output level of described 5th feeder ear and described 6th feeder ear is height
Level；
Described the first transistor and described transistor seconds are in conducting state, and described transistor seconds
Work in linear amplification region.
Memory cell the most according to claim 5, it is characterised in that described the first transistor pair
The resistance answered is the first resistance, and the resistance that described transistor seconds is corresponding is the second resistance, described second electricity
Resistance is more than described first resistance.
Memory cell the most according to claim 5, it is characterised in that described MTJ is corresponding
Resistance includes that low resistance state resistance and high-resistance resistors, described low resistance state resistance are described in described MTJ works in
Resistance during low resistance state, described high-resistance resistors is described MTJ resistance when working in described high-impedance state；
The dividing potential drop to described 5th feeder ear output level according to described high-resistance resistors and described first resistance
Determine the grid level of described transistor seconds；
The output level of described 6th feeder ear deducts difference between described grid level for more than 0 and close
In the positive number of 0.
Memory cell the most according to claim 5, it is characterised in that described transistor seconds
The linear gradient of VA characteristic curve is more than 1.
9. a spin transfer torque magnetic memory, it is characterised in that including: at least one is wanted such as right
Seek the spin transfer torque magnetic memory cell according to any one of 1 to 8；
Reading circuit, described reading circuit includes at least one amplifier, at least one amplifier described
Quantity equal with the quantity of described spin transfer torque magnetic memory cell, and each amplifier one a pair
Answer a described spin transfer torque magnetic memory cell；
The positive input terminal of described each amplifier and the institute in corresponding spin transfer torque magnetic memory cell
State the second source electrode line to connect.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510160721.3A CN106158000A (en) | 2015-04-07 | 2015-04-07 | Spin transfer torque magnetic memory cell and memorizer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510160721.3A CN106158000A (en) | 2015-04-07 | 2015-04-07 | Spin transfer torque magnetic memory cell and memorizer |
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| CN106158000A true CN106158000A (en) | 2016-11-23 |
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| CN201510160721.3A Pending CN106158000A (en) | 2015-04-07 | 2015-04-07 | Spin transfer torque magnetic memory cell and memorizer |
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| WO2018117961A1 (en) * | 2016-12-19 | 2018-06-28 | Agency For Science, Technology And Research | Memory cell, methods of forming and operating the same |
| CN111902872A (en) * | 2018-07-02 | 2020-11-06 | 华为技术有限公司 | Self-termination write circuit and method |
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| CN111696600A (en) * | 2019-03-12 | 2020-09-22 | 中芯国际集成电路制造(上海)有限公司 | Magnetic memory |
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| CN112599556B (en) * | 2019-09-17 | 2023-12-19 | 铠侠股份有限公司 | magnetic memory |
| CN112542189A (en) * | 2019-09-20 | 2021-03-23 | 中芯国际集成电路制造(上海)有限公司 | Magnetic memory, program control method and read method thereof, and magnetic storage device |
| WO2021083356A1 (en) * | 2019-11-01 | 2021-05-06 | 华为技术有限公司 | Storage and computation unit and chip |
| CN110956993A (en) * | 2019-12-12 | 2020-04-03 | 中国科学院微电子研究所 | Resistance change type memory cell based on resistance voltage division reading |
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